A Three-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique for 5dB NF

Transcription

1 A Three-Stage 60GHz CMOS LNA Using Dual Noise-Matching Technique for 5dB NF Ning Li 1, Kenichi Okada 1, Toshihide Suzuki 2, Tatsuya Hirose 2 and Akira 1 1. Tokyo Institute of Technology, Japan 2. Advanced Devices Lab, Fujitsu Laboratories Ltd, Japan 2008/12/18

2 Outline 1 Background 60GHz LNA Design Method Circuit and Simulation Results Conclusions

3 Background 2 7 GHz unlicensed band at 60 GHz Gbps data transfer 60GHz Short range Good isolation Reference:

4 Applications WPAN Wireless HDMI Point to Point links 3 Receiver Architecture Ref:

5 Outline 4 Background 60GHz LNA Design Method Circuit and Simulation Results Conclusions

6 Issues When up to mm-wave CMOS LNA High frequency Lower gain MAG is inversely proportional to the logarithm of the operating frequency f c. Higher noise MSG/MAG MAG [db] [db] semi-log scale log-log scale 4 2 NF [db] 5 NF min is proportional to the operating frequency f c Frequency [GHz] W f =2.5 m, N f =32, V gs =0.8V and V ds =0.8V. G MAG 20 lg( ω MAX ω c ) ω c NF min = G m ( R g + ω T R s )

7 Cascode Topology Noise 6 Vdd Zin M 2 I out M 2 M C x RF in M 1 Cascode Stage 1 Stage 2 CS+CG Small signal equivalent circuit F F ( I R + V ) = F 2 2 ω C 0 x 2 + 4R sγ 2gd 02 ω 2 2 ωt g m 2 tot, cascode g1 s g1 ω0 = 1+ = + γg d 01Rs 2 4kTRs ωt 1 1 ω T g = C m1 gs1 C = C + C + C x gs2 sb2 db1 High noise contribution of M2 due to the large interstage node capacitance. Reference: Hirad Samavati, et al., IEEE JSSC, VOL. 35, NO. 5, MAY 2000

8 CS-CS Noise 7 Vdd1 Vdd2 RF in M 1 M 2 Proposed schematic Noise Circles Available Gain Circles Source Stability Circle Common source topology has a smaller NF. Using source degeneration to adjust the value of the input impedance. Reference: D.K. Shaeffer, et al., IEEE JSSC, VOL. 32, NO. 5, MAY 1997.

9 Outline 8 Background 60GHz LNA Design Method Circuit and Simulation Results Conclusions

10 Transistor Model at 60 GHz 9 Based on BSIM4 model Large signal Scalable Back-gate model Measurement condition: W f =2.5 m, N f =32, V gs =0.8V and V ds =0.8V.

11 Slow-wave Transmission Line dB/mm at 60GHz 10µm 13µm Metal 1 Top Metal L Constant C Larger Phase Constant: Small area! β ω LC

12 Proposed LNA Circuit Multi-stage Higher gain Dual noise-matching topology Lower noise

13 Stability 12 Common source is much more sensitive to process variations arising from the bilateral nature of the device. K Input matching Careful layout Frequency [GHz] Circuit is unconditionally stable from DC to 100GHz.

14 For Comparing 13 Vdd1 Vdd2 Vdd3 115 C C1 20 C C2 80 RF in C in Pad V b V b V b Pad C out RF out The same stage used Cascode topology

15 Simulation Results S11, S22 14 S11, S22 [db] S11, S22 [db] Proposed 59GHz~66GHz S11 S22 7GHz bandwidth in Japan Proposed <-11.4dB <-5.1dB Conventional Conventional <-13.3dB <-5.7dB

16 Simulation Results Power Gain 15 Proposed Conventional Gain 15dB 16dB

17 Simulation Results -- NF 16 Proposed Conventional NF 5dB 6.4dB

18 Performance Comparison 17 Technology Simulation Measurement Proposed Conv. [1] [2] [3] [4] [5] 90nm CMOS 90nm CMOS 90nm CMOS 90nm CMOS 90nm CMOS 90nm CMOS Topology dual-cs cascode CS cascode cascode CS cascode Gain [db] (diff.) NF [db] (sim) (sim) 6.1 Power [mw] nm CMOS Reference: [1] Emanuel Cohen, et al., RFIC, pp , [2] Terry Yao, et al., IEEE JSCC, vol. 42, no. 5, pp , [3] Stefano Pellerano, et al., ESSCIRC, pp , [4] Babak Heydari, et al., IEEE JSCC, vol. 42, no. 12, pp , [5] Christopher Weyers, et al., ISSCC, pp , 2008.

19 Outline 18 Background 60GHz LNA Design Method Circuit and Simulation Results Conclusions

20 Conclusions 19 A three-stage LNA employing a dual noise-matching topology Noise matching optimized by using source degeneration A 5dB NF realized by dual noise matching technique Comparing with the conventional 1.4dB NF improvement 1dB gain decrease 3mW power consumption increase

21 Finally 20 Thank you!