Methodology for Simultaneous Noise and Impedance Matching in W-band LNAs

Transcription

1 Methodology for Simultaneous Noise and Impedance Matching in W-band LNAs Sean T. Nicolson and Sorin Voinigescu University of Toronto CSICS-006, San Antonio, November 15, 006 1

2 Outline Introduction Noise matching issues at mm-waves Mm-wave LNA design methodology GHz CMOS LNA examples Summary

3 Motivation GHz applications Automotive radar (SiGe BiCMOS) Active/passive imaging (SiGe BiCMOS, 65nm CMOS) NFMIN of nanoscale MOSFETs is very competitive at mm-waves (P.Chevalier et al. CSICS-006) Issues Pad capacitance and bondwire or flip-chip bump inductance 3

4 SiGe HBT and CMOS LNA Design Philosophy Active device noise matching FMIN f, J=JOPT =0 Bias for minimum FMIN J FMIN W f =W fopt =0 Find optimal Wf (le) for given frequency Wf size Nf or number of transistors connected in parallel for Re{Zsopt }= Z0 Lossless feedback for input impedance matching ZIN and Im{Zsopt} Cascode with series-series inductive feedback is the preferred topology 4

5 Biasing MOSFET LNA Topology for Minimum Noise MOSFET, cascode JOPT = 0.15 ma/µm irrespective of frequency, Wf, and technology node 5

6 Biasing SiGe HBT LNA Topology for Minimum Noise NF MIN at 5GHz and 65GHz for Two SiGe Technologies SiGe B 5GHz SiGe B 65GHz SiGe A 5GHz SiGe A 65GHz SiGe B ft SiGe A ft Collector Current Density (ma/µ m ) Frequency (GHz). Noise Figure (db) JOPT depends on topology, increases with frequency and in more advanced technology node 6

7 Refinements for mm-wave CMOS LNA design: ft and NFMIN of topology with LM VDD M Csb+Cgs LM1 M1 LM1 scales as 1/W f T cascode = Cdb1+Cgd1 gm1 C gs1 C gd1 Both ft and NFMIN improve Similar impact (15..0%) on bulk and SOI cascode 7

8 Selecting MOSFET Wf & Gate Contact Geometry gate metal tapered metal source source Compromise between gate parasitic capacitance and gate resistance Wf gate contacted on one side drain gates contact/via drain Wf RCON Rsq + Wext + N CON L 3 RG = Nf gate contacted on both sides Wf RCON R sq + Wext + N CON L 6 RG = N f 8

9 Experiments in 90nm GP CMOS 77GHz 1-stage cascode with variable Wf gate geometry W (µm) Gate Contact Ncon=1 S1 (db) Sim. Meas. NF (db) A Wf (µm) 1 36 single-sided 3.63 (.1) 4.78 B 36 double-sided 4.36 (.) 4.88 C single-sided 5.04 (3.7)

10 Refinements at mm-waves: source impedance ZSOPT(M1)= RS +j/ω CS LBW CS VIN ZO RS Cpad R s= Z0 0 1 LBW CPAD Z C Without bondwire VIN PAD Z0 R S= k M1 ZS Xs =j ZIN [LBW 1 LBW CPAD Z0 CPAD ] 1 LBW CPAD Z0 CPAD Z0 C P A D Z Z S = j k k k =1 C P A D Z

11 Proposed mm-wave LNA Algorithmic Design Methodology ZS = RS + jxs Wf and bias at JOPT LM to maximize ft/nfmin of JOPT Find optimal Nf such that JOPT Find LS = RS/ ωt such that Rs = Re{ZIN} Find LG such that Xs = Imag{ZIN} = Imag{ZSOPT} Output matching : LD1, CD 11

12 84-94 GHz xfmr-coupled CS-CG LNA in 90nm GP CMOS Peak gain = 1.7 db (91GHz) BW3dB>10 GHz S11, S<-10 db, S1 <-30 db 1. V supply, 3 ma 0.35mmx0.4mm 1

13 75-94 GHz -stage cascode LNA in 90nm GP CMOS Peak gain = 4.8 db (94GHz) BW3dB>0 GHz S11, S<-10 db, S1 <-30 db 1.8 V supply, 16 ma 0.35mmx0.4mm 13

14 3-stage Cascode Amplifier Schematics in 65nm LP CMOS 14

15 Layout and Measured S-params VDS=1V ft/fmax = 140/180 GHz (Wf=µ m) Peak gain = 8.5 db (80 GHz) S11, S<-8dB Isolation > 30 db 0.4mmx0.4mm (including pads) 15

16 Conclusions Algorithmic LNA design methodology at mm-waves developed to account for pad capacitance and bondwire inductance Inductive broadbanding in MOS cascode First 80GHz and 94GHz CMOS amplifiers First transformer in CMOS at 94 GHz Low-VT GP 65nm CMOS technology is needed for GHz LNAs At similar ft, 80-GHz SiGe HBT LNAs have higher gain for similar power dissipation 16

17 Acknowledgments T. Chalvatzis and K.Tang for S parameter measurements Dr. M.T. Yang at TSMC Dr. P. Schvan at NORTEL CITO, STM, NORTEL for funding support TSMC, NORTEL and CMC for fabrication Jaro Pristupa and CMC for CAD support OIT, CFI, ECTI for equipment 17

18 LNA Design Fundamentals G I I P 3 f O I P 3 f F o M LNA = = F 1 P F 1 P Device noise fundamentals: Re{Zsopt} <> Re{ZIN} and Im{Zsopt} approx. Im {ZIN} (within 15%) Re{Zsopt} = k ft/(fgm) FMIN is invariant to number of gate fingers Nf, and number of transistors m connected in parallel, but depends on Wf. Reactive (lossless) feedback does not affect FMIN and Re{Zsopt} Power is dictated by noise impedance matching (by VDD*JOPT /g m) 18

19 Possible MOSFET Layouts source drain source m5 m4 m3 m m1 CD S act ive drain gate resistance must be traded off with gate capacitance 19