CIRF Circuit Intégré Radio Fréquence Low Noise Amplifier. Hassan Aboushady Université Paris VI
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1 CIRF Circuit Intégré Radio Fréquence Low Noise Amplifier Hassan Aboushady Université Paris VI
2 Multidisciplinarity of radio design H. Aboushady University of Paris VI
3 References M. Perrott, High Speed Communication Circuits and Systems, M.I.T.OpenCourseWare, Massachusetts Institute of Technology, D. Leenaerts, J. van der Tang, and C. Vaucher, Circuit design for RF transceivers, Kluwer academic publishers, H. Aboushady University of Paris VI
4 LNA : 1 st block of an RF Receiver Heterodyne Homodyne (Direct conversion) Low-IF 4
5 LNA Requirements: Noise Noise Factor : F = SNR in SNR out Noise Figure : NF = 10 log 10 (F) Si F1 G1 F2 G2 F3 G3 So Friis Equation : F = 1+ ( F 1 1) + ( F 1) ( F 1) ( F 1) 2 G G G G G 1 n 2... G n 1 LNA Requirements to reduce the RF receiver overall Noise Factor: Low Noise Factor, F 1 High Gain, G 1 5 University of Paris VI
6 LNA Requirements: Linearity Vi ω1ω2 A IP 3,1 α 1 2 A IP3 ω x(t) 1 2 A IP3,1 P + α A y(t) db IIP 3 dbm = + A IP 3, 2 β IP3,2 ω1ω2 α β + A ω 2ω1-ω2 2ω2 -ω1 P in dbm A IP 3,3 γ IP3,3 P Vo +... LNA Requirements to improve the RF receiver overall linearity: High A IP3,1 Low α 1 University of Paris VI 6
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17 Common Source Amplifier A = g. Z v m out Rout Cgd Vout Vin M1 - Parasitic capacitance Cgd between input and output nodes. - Low Gain - Complex Load Impedance Z R r ( out = out 0 1 jωc par ) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 17
18 Common Source Cascode with Inductive Load Benefits of Cascode - Isolation between input and output nodes - Higher Gain M2 Lout Vout Vin M1 Purpose of Inductive Load - Real Load Impedance can be obtained 1 jω C ω ( Zout = r0 cascode j 0Lout 0 par ) 18 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
19 Biasing Current Mirror Rref Lout Vout M3 M2 R Vin M1 Current Mirror - The current in M1 is fixed by Rref and the ratio (W1/L1)/(W3/L3). - R is to increase the impedance seen by the input signal. 19 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
20 Matching Input Impedance Rref Lout Vout M3 M2 R Vin Lg M1 Inductive Degeneration Ldeg - Lg compensates the complex impedance due to Cgs1. - Ldeg adjusts the real part of the input impedance to 50 Ω. 20 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
21 Ldeg and Lg (1) Input Impedance Z 1 gm ( L C in s) = + s( Ldeg + Lg ) + scgs Matching Zin to 50Ω R s = g C m gs L deg For a Real Impedance@ ω0 ω 0 = 1 (L + L ) g deg C gs D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI gs deg 21
22 Ldeg and Lg (2) Re{Zin} For different Ldeg values Lg Re{Zin} independent of Lg D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 22
23 Ldeg and Lg (2) Re{Zin} For different Ldeg values Lg Re{Zin} independent of Lg Im{Zin} Lg Ldeg for: Re{Zin}=50 Lg for: Im{Zin}=0 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 23
24 NF of a MOS Transistor Techno. 0.35µm c= -0.4j γ = 2/3 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 24
25 NF Characterization F = N o( total) SNR SNR = i o N = S S i o N o( source) N i( source) o( total) + N = o( added ) S ( S i i N. G) i( source) N o( total) = N G. N o( total) i( source) No( total ) No( source) + No( added ) F = = = 1+ N N o( source) o( source) N N o( added ) o( source) 1) No(added) : Output Reffered Noise due to the LNA. 2) No(source): Output Reffered Noise due to the source. 25 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
26 Noise Sources Résistance R R i 2 R = 4 kt R D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
27 Noise Sources Résistance Transistor R R i 2 R = 4 kt R i 2 d = 4 kt γg d 0 f i 2 g = 4 kt δ g gs f D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 27
28 Noise Sources Résistance Transistor Inductance R R Csub Ls Rsub Rsub Rs Rs i 2 R = 4 kt R i 2 d = 4 kt γg d 0 f i 2 g = 4 kt δ g gs f D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 28
29 Noise Sources Resistance Transistor Inductance R R Csub Ls Rsub Rsub Rs Rs i 2 R = 4 kt R i 2 d = 4 kt γg d 0 f F = 1+ N N o( added ) o( source) i 2 g = 4 kt δ g gs f N o(added ) NF = f ( G. N i, i N o(source) 2 d H d, i 2 g H g, i 2 R H R, i 2 Rs H Rs, i 2 Rsub H Rsub ) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 29
30 Noise Sources I I in H d ( s) = I I out in ( s) ( s) 30 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
31 Characterization Gain : Vin Circuit out Gain ( s) = Vout( s) Vin( s) Input Impedance: Vin Iin Circuit out Zin ( s) = Vin( s) Iin( s) Noise Factor: in Circuit out F = 1+ N N o( added ) o( source) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 31
32 Characterization Example out 1) scv. 2) V in out V = ( s) = 1 1/ R 1/ R + sc Vin ( s) 0 = 1 0 Vout ( s) 1 1/ R 1/ R + sc Gain( s) 0 1 V = V src out in ( s) ( s) 1 = 1+ src in ( s) V R out Gauss-Jordan 32 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI ( s)
33 Automatic Characterization Procedure Netlist Description Cairo+ Create Matrices Gain Matrix Zin Matrix Matrices of Noise Transfer Functions of each Noise Source Small Signal Parameters Maxima Solve Matrix Substitution Numerical solution of the matrix GiNaC (C++) Zin, Gain, No(added) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 33
34 Design Procedure Transistors Length: Minimum L to reduce parasitic capacitances. Width: Ids calculated for NFmin. Layout: Maximum number of fingers to reduce Gate resistance. Inductors Ldeg : Adjusted for Re {Zin} = 50 Ω. Lg : Adjusted for Im {Zin} = 0 Ω. Lout : Adjusted for the desired Zout and Gain. D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 34
35 CAIRO+ Circuit Design Parameters Transistors Sizes And Biasing Small Signal Parameters LinearCircuit Performance Temp W 1 g m,1 A d0 V IN,i V gs1 g ds,1 F T V OUT,i V eg,i I B,i L i V ds1. W n. C gs,1 g m,n 2 i d 2 i g? φ ṃ. Sizing Biasing Small Signal Characterization Performance Modeling [Ramy ISKANDER Knowledge-aware synthesis for analog integrated circuit design and reuse Ph.D. Thesis UPMC,LIP6 2008] 35
36 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 36 University of Paris VI
37 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caractérisation de NF, Gain, Zin 37 University of Paris VI
38 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances L L out deg et L g : valeurs initiales pour Re{ Z } 50 in Ids++ No Calculate NF NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 38 University of Paris VI
39 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 39 University of Paris VI
40 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF I++ Non NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 40 University of Paris VI
41 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 41 University of Paris VI
42 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 42 University of Paris VI
43 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Ids++ No Calculate NF NF min? Yes Ldeg for Re{Zin}=50 Lg for Im{Zin}=0 Impedance Matching Gain Adjustment No Gain OK? Yes Caracterization of NF, Gain, Zin 43 University of Paris VI
44 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 44 University of Paris VI
45 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Choiceof Lout : A = G. Z Z v out = m f ( L out out ) Transistors Sizing Choose Inductances Calculate NF Ids++ No NF min? Yes Gain Adjustment Impedance Matching No Gain OK? Yes Caracterization of NF, Gain, Zin 45 University of Paris VI
46 Automatic Sizing Procedure Techno Rs f0 Vdd Gain Topology Ids-min (Wmin,Lmin) Transistors Sizing Cairo+ Choose Inductances GiNaC Calculate NF GiNaC Ids++ No NF min? Yes Impedance Matching GiNaC Gain Adjustment No Gain OK? Yes Caracterization of NF, Gain, Zin 46 University of Paris VI
47 Matching Input Impedance Introduction Les paramètres de conception Circuit proposé Méthode de conception Caractérisation automatique Conception automatique Exemple de conception 47 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
48 Design Example I: A 2.4GHz LNA in 130 nm CMOS Technologie Vdd Résistance de source (Rs) Fréquence centrale (f0) Gain Spécifications Résultats de la procédure proposée W (um) L (um) Vgs (V) Vds (V) Ids(mA M ) M M um 1.2 V 50 Ω 2.4 GHz 15 db R= 100 KΩ, Rref = KΩ, Ldeg = nh, Lg = nh, Lout = 3 nh D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 48
49 Estimated and Simulated Input Impedance Zin (Cairo+) (Ω) Zin (ELDO) (Ω) D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
50 Estimated and Simulated Gain and NF Gain (db) NF (db) Cairo ELDO D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
51 Simulated S Parameters S21 (db) S11 (db) F (Hz) 2.4 GHz = db 2.4 GHz = db D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 51
52 Simulated IIP3 Fondamentale IM3 IIP3= dbm D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 52
53 Comparison with state of the art FOM S = 10 log(100( ( F 21 ( lineaire) 1) P f 2 0 dc( mw ) )) [Chandrasekhar 2002] [1] [2] * [3] [4] [5] [6] * (*) résultats de simulation [V. Chandrasekhar, C.M. Hung, Y.C. Ho, and K. Mayaram. A Packaged 2.4GHz LNA in a 0.15umCMOS Process with 2kV HBM ESD Protection, ESSCIRC, 2002] D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI 53
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CIRF Circuit Intégré Radio Fréquence. Low Noise Amplifier. Delaram Haghighitalab Hassan Aboushady Université Paris VI
CIRF Circuit Intégré Radio Fréquence Low Noise Amplifier Delaram Haghighitalab Hassan Aboushady Université Paris VI Multidisciplinarity of radio design H. Aboushady University of Paris VI References M.
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