POSTECH Activities on CMOS based Linear Power Amplifiers

Transcription

1 1 POSTECH Activities on CMOS based Linear Power Amplifiers Jan Bumman Kim, & Jongchan Kang MMIC Laboratory Department of EE, POSTECH

2 Presentation Outline 2 Motivation Basic Design Approach CMOS PA Linearization 3.3 V Operating Single-chip CMOS PA Lumped Doherty CMOS PA Conclusions

3 Motivation 3

4 Motivation 4

5 Challenges for CMOS PA 5

6 Small-signal equivalent circuit 6 C. E. Biber, M. L. Schmatz, T. Morf, U. Lott, and W. Bächtold, A nonlinear microwave MOSFET model for SPICE simulators, IEEE Trans. Microwave Theory and Techn., Vol. 46, No. 5, pp , May 1998.

7 Nonlinear Transconductance (g m ) 7 dominant nonlinear source at normal operation 0.3 gm1, gm2, gm3 [A/V] [A/V 2 ] [A/V 3 ] gm3 zero- crossing point gm1 gm2 gm [Extracted g m ] [Nonlinear expansion coefficients for g m ] Vgs [V] i = g v + g v + trans 2 3 m1 gs m2 gs m3 gs 1 i = g v 2 g 2 trans,2ω m2 gs, ω i = g v 2 * trans, 2ω ω1 m3 gs, ω2 gs, ω1 2 4 v v

8 Nonlinear gate-source capacitance (C gs ) 8 the dominant nonlinear source for a class AB PA Vds [V] Cgs [pf] Cgs1, Cgs2, Cgs3 [pf] [pf/v] [pf/v 2 ] [Extracted C gs ] [Nonlinear expansion coefficients for C gs ] i Cgs,2ω ω 2 1 C = C + C v + C gs v 2 gs1 gs2 gs gs3 gs i = j( ω ω ) C v v * Cgs, ω ω 2 1 gs2 gs, ω gs, ω i = jω C v 2 Cgs,2ω 2 gs2 gs, ω i ω = jω C v 4 3 = j(2ω 2 ω1) Cgs3v 4 + j(2ω ω ) C Cgs,3 2 gs3 gs, ω gs2 2 gs, ω 2 v * * [ v v + v v ] gs,2ω 2 * gs, ω 1 gs, ω 1 gs, ω 2 gs, ω ω 2 1

9 Analysis of PA linearity using Volterra Series 9

10 Harmonic balance simulation of Volterra series 2nd harmonic termination at the output & biasing close to g m3 zero crossing point 10 IMD3 [dbc] Harmonic distortion from C gs is larger than that from g m!

11 Harmonic balance simulation of Volterra series Assuming 0.3 nh of parasitic source inductance for grounding 11 The 2nd harmonic termination at the source suppresses the harmonic distortion at the input and output

12 Linear CMOS PA Design Approach 12

13 Unit power cell with DNW structure 13

14 DC_IV Comparisons 14

15 15 Nonlinear gate-source capacitances (C gs ) 0.30 Cgs1, Cgs2, Cgs3 [pf] [pf/v] [pf/v 2 ] Cgs1 of the device with DNW Cgs2 of the device with DNW Cgs3 of the device with DNW Cgs1 of the standard device Cgs2 of the standard device Cgs3 of the standard device Vgs [V] [Extracted C gs ] [Nonlinear expansion coefficients for C gs ] J. Su, H. Hsu, S. Wong, C. Chang, T. Huang and J. Y. Sun, Improving the RF Performance of 0.18 um CMOS With Deep n-well Implantation, IEEE Electron Device Letters, Vol. 22, No. 10, pp , Oct 2001.

16 The calculated contributions for IMD3 generation using 16 Volterra series analysis Std. DNW Std. DNW g m contribution dbc dbc C gs contribution dbc dbc r ds contribution -72 dbc dbc C jd contribution -74 dbc dbc IMD3 of the standard device = dbc IMD3 of the device with DNW = dbc Center Frequency = 2.45 GHz, Tone-spacing = 2 MHz, Pin = -14 dbm

17 DNW Effects of 0.18 um Balanced CMOS PA 17

18 CMOS Chip Photo of Balanced PA MIM Cap for drain 2fo short 18 MIM Cap for drain 2fo short Driver stage Power stage

19 RF performance comparison of the 19 Balanced PA s P out : 20.2 dbm, Gain : 18.7 db, PAE : 35 % at P 1dB Linearity maintains under -45 dbc of IMD3 and -57 dbc of IMD5 for an output power backed-off more than 5 db from P 1dB. PA with DNW improves the IMD3 and IMD5 about 7dB without disturbing the power performances (P out, PAE)

20 V Operating Single-Chip CMOS PA

21 Prototype of 3.3 V operating linear CMOS PA 21 Modified selfbiased cascode 0.13um or 0.18um CMOS Thick gate-oxide 0.35um NMOS

22 Modified Self-Biased Cascode 22 Voltage swing V ds2 Gate oxide voltage =V ds2 -V GS2 V gs2 V DD V GS2 V DD /2 Maximum V ds1 time

23 One-turn Inductor vs. Slab Inductor 23 L Q=5-15 Q=20-30 W L'<4L L M3 M2 M4 W' P1 P2 M1 C s1 Cs2 P1 P2 C s1 C s2 R s Slab inductor provides higher Q, thus lower loss

24 Magnetically Coupled Transformer 24

25 Integrated transformer performance 25 MIM Cap Metal Substrate Cu or Al (3um) Si (15 S/m) MIM Cap Conductivity 4.7e-7 7 ~3.4e- 7 S/m MIM Cap for 2fo short Size 600 x 700 Loss 0.5~0.8 db PAE 89~80 % Zout 13 +j*1

26 V operating Single-Chip CMOS PA (0.18 um process)

27 3.3 V operating Single-Chip CMOS PA (1 x 1.7 mm 2 ) 27 MIM-Cap for source 2fo short Driver cell Power cell Balun Transformer Power cell Driver cell MIM-Cap for drain 2fo short

28 RF performance of 3.3 V Operating Single-Chip CMOS PA (2.4 GHz) 28 Technology Power Supply Frequency 0.18 um CMOS 3.3 V 2.4 GHz Area 1 x 1.7 mm 2 RF performances at P 1dB P out Power gain PAE OFDM signal Test measured 24.5 dbm 19.8 db 31 % 54 Mbps/64 QAM EVM 4.5 % 3 % Average power PAE 18.8 dbm 15.8 % 17.9 dbm 14 %

29 29 Lumped Doherty CMOS PA for 2.4 GHz WLAN

30 30 Lumped Doherty Conversion Concept

31 31 Prototype of 2-Stage Lumped Doherty Circuit

32 Example of 3.2 V operating Doherty 32 CMOS PA (1 x 1 mm 2 )

33 RF performance of 3.2 V Operating Lumped Doherty CMOS PA 33 P 1dB = 22.7 dbm PAE = 60 % at P 1dB PAE = 35 % at P 5dB

34 34 Comparison of Measured Results PAE Design Technology (um) Gain [db] Pout max [dbm] Pout max P 1dB 4 db Back-off 8 db Ballweber Giry Sowlati Ding This work

35 Conclusions 35 Basic design approach and linearization methods for CMOS PA are established. 3.3 V operation single-chip CMOS PA A circuit prototype for a linear CMOS PA with high voltage operation is proposed. The integrated transformer is a prominent solution for a balanced single-chip PA with low loss. Lumped Doherty CMOS PA Proposed first-step for the fully integrated CMOS Doherty PA. Demonstrated good performances of CMOS PA comparable to GaAs based PA