Analysis and Design of Analog Integrated Circuits Lecture 6. Current Mirrors

Transcription

1 Analysis and Design of Analog Integrated Circuits ecture 6 Current Mirrors Michael H. Perrott February 8, 2012 Copyright 2012 by Michael H. Perrott All rights reserved.

2 From ecture 5: Basic Single-Stage CMOS Amplifiers Common Common Gate Follower Z Z W 1 Vout i d W 1 i d W 1 i in Z Common with Degeneration Z i d W 1 Z src V src I src Z src Z S 2

3 A Closer ook at oad Impedance Common Common Gate Follower Z Z W 1 Vout i d W 1 i d W 1 i in Z Common with Degeneration Z Z S i d W 1 To achieve high gain (or low attenuation in the case of a source follower), it is very desirable to achieve high load impedance, Z - Unfortunately, using a simple resistor of high value has issues What are these issues? 3

4 Issue #1: Headroom imitations Common V dd R I d Want V ds > ΔV The bias current of the device is a direct function of R I d = V dd V ds R - V dd is < 3.6V for most modern CMOS processes - V ds must be greater than V to maintain device saturation arge R implies small I d (implies small g m, poor frequency response, etc.) 4

5 Issue #2: Area of Circuit Common V dd R I d Want V ds > ΔV The most common resistors for precision analog circuits are often based on unsilicided polysilicon layers - The sheet resistance of unsilicided polysilicon is often < 1k /square arge polysilicon R implies relatively large circuit area (implies high relative cost) 5

6 An Elegant Approach to Achieving High Gain Common V dd I bias I d V ds1 > ΔV 1 Replacement of resistor load with a current source yields the highest possible DC gain out of the amplifier - Current source determines I d of device We can make current sources out of transistors - Generally smaller area than polysilicon resistors What is the small signal gain of the above circuit? 6

7 A Simple Transistor Based Current V dd V bias Vsd2 > ΔV 2 M 2 I d V ds1 > ΔV 1 Simply use a PMOS load that is properly biased - If we keep the PMOS in saturation, its current is relatively constant despite V sd variations This is the desired behavior of a current source What are the nonideal issues of the above approach? 7

8 Issue #1: Impedance of PMOS Device V dd V bias Vsd2 > ΔV 2 M 2 Z I d V ds1 > ΔV 1 An ideal current source has infinite impedance PMOS devices have finite impedance - What is Z in the above circuit? - How does finite Z impact the gain of the circuit? We will later examine techniques to increase Z 8

9 Issue #1: High Bias Sensitivity V dd V bias W 2 M 2 I d V ds1 > ΔV 1 The PMOS device current, I d, is very sensitive to the value of V bias - We want I d to be relatively constant across temperature and process variations How can we achieve tighter control over I d across temperature and process variations? 9

10 Key Technique: Use Current Mirror V dd W 3 V bias W 2 V sd2 > ΔV 2 M 3 M 2 I bias I d V ds1 > ΔV 1 Key idea: use a different PMOS device, M 3, to transform a bias current, I bias, into bias voltage, V bias - V bias now yields a consistent current, I d, in M 2 (assumed to be in saturation) across temperature and process variations - Note that layout of M 2 and M 3 must be done properly to achieve good device matching How does I d relate to I bias? 10

11 NMOS Devices Can Also Be Used for Current Mirrors I bias I d W 2 M 2 V bias W 1 V ds1 > ΔV 1 We often use both NMOS and PMOS versions in designs - We ll explore this issue further later in the semester General issue: current mirrors involve direct feedback between drain and gate Can we apply proposed Thevenin modeling approach to current mirrors? 11

12 Issue: Thevenin Impedances Are Not Adequate R S ooking as purely Thevenin impedances But, in reality Issue: coupling between source, drain, or gate - Do we have to abandon the Thevenin method? 12

13 Try Proposed Thevenin Model g d i test v test R ths i s R thg v g A v v g αi s Rthd s R s Key Calculations (ignore R thd for now): 13

14 Proposed Thevenin Model Works! g d i test v test R ths i s R thg v g A v v g αi s Rthd s R s Now include R thd : 14

15 Check Thevenin Resistance Calculation Diode-Connected Device Derive Using Hybrid-π Model Resulting One-Port Model v gs g m v gs -g mb v s (g m +g mb ) r o 1 g m g m R S R S v s R S Plug in Hybrid- to do the analysis - Answer agrees with proposed Thevenin model approach Easiest to just memorize this result: Diode connected MOS looks like a resistor of value 1/g m 15

16 Now Apply Thevenin Approach to the Current Mirror I bias node1 node2 I ref M 2 M 2 node1 node2 node2 g1 d1 1 g m2 R thg1 v g1 g m1 v g1 R thd1 R thd1 = r o1 Diode-Connected Common Key parameter of current source: output resistance - Corresponds to r o of device 16

17 Cascoded Current I ref I bias V bias V bias V ds3 > ΔV 3 M 3 M 3 M 2 V ds1 > ΔV 1 r o1 Offers increased output resistance - Calculate using Thevenin resistance method - How does I ref compare to I bias? 17

18 Double Cascode Current I 1 I 2 V bias2 M 3 V ds3 > ΔV 3 V bias1 M 2 V ds2 > ΔV 2 M 4 V ds1 > ΔV 1 Offers further increased output resistance - Calculate using Thevenin resistance method - How does I 2 compare to I 1? 18