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1 The Equivalence of and Models in Modeling the Induced Gate Noise of MOSFETs Jung-Suk Goo, William Liu, Chang-Hoon Choi, Keith R. Green, Zhiping Yu, Thomas H. Lee, and Robert W. Dutton, Stanford Compact Modeling Group, Texas Instruments, Dallas

2 Outline Induced Gate Noise Noise Model Model Comparison Method Validation for Device Validation for Circuits Conclusions

3 Induced Gate Noise (Physical Origin) At Low Frequency Gate Source Drain

4 Induced Gate Noise (Physical Origin) At High Frequency Gate Source capacitive coupling Drain Noticeable i g if f > f t /10

5 Induced Gate Noise (Continue) (Impact on Noise Figure) MOSFET * NF 50Ω Power-Constrained LNA 15 5 IDD =5mA NF 50Ω [db] /f Noise w/ i g Induced Gate Drain Noise Thermal Noise g w/o i Noise Figure [db] f = 4GHz Zin =50Ω w/ i g w/o i g Frequency [Hz] Gate Bias [V] * by A.J. Scholten et al. (IEDM, 1999)

6 i g i d i d R s v Rs i dp Induced Gate Noise (Continue) (SPICE Models) BSIM3 Solid Physical Basis de facto Standard Released in Mar.000 No Induced Gate Noise New Approach

7 i g i d v x i dp Noise Model (Modeling Strategy) Connected to Gate Connected to Source R x >>R s is assumed

8 i g i d v x i dp Noise Model (Modeling Strategy) Connected to Gate Frequency Dependent Connected to Source Frequency Independent

9 i g i d v x i dp Noise Model (Modeling Strategy) Connected to Gate Frequency Dependent Correlated with i d (3 Noise Parameters) Connected to Source Frequency Independent Uncorrelated with i dp ( Noise Parameters)

10 Noise Model (Continue) (Arguments) is easy to implement. What is the physical relationship to the van der Ziel model? How to extract the parameters? What is the underlying assumption? How small is the discrepancy?

11 i g;short i g id i d;short i g i g;short = (Y11 + Y1)v x v x idp i d;short Noise Model (Continue) (Physical Relationship to ) From i g;short

12 i g;short i g id i d;short i g i g;short = (Y11 + Y1)v x v x idp i d;short Noise Model (Continue) (Physical Relationship to ) From i g;short From i d;short i d = (Y1 + Y)v x + i dp

13 v x = i g =jy 11 + Y 1 j i dp = i d jy 1 + Y j v x Noise Model (Continue) (Physical Relationship to ) Exact Fit

14 i g i Λ d = i g(y 1 + Y ) Λ =(Y 11 + Y 1 ) Λ =[i g i Λ d ] Noise Model (Continue) (Physical Relationship to ) x = i g =jy 11 + Y 1 j v i d jy 1 + Y j v x = i dp Exact Fit Discrepancy 4 x nmos 100/0.5 VGS =1.5V VDS=1.5V 0 is assumed in Frequency [GHz]

15 Model Comparison Method (Parameter Extraction Procedure) Measured Data [NFmin,Rn,Yopt] Extract [i g,igi Λ d, i d ] Extract [v x,i dp ] Transformation [i g,ig i Λ d, i d ] Transformation [NFmin,Rn,Yopt] Ziel Transformation [NFmin,Rn,Yopt] Comparison

16 4 C vnv Λ n C i nv Λ n C v ni Λ n C i ni Λ n R n CA = A 1 CA A y 1 + CA 1 Fmin 1 R n Y Λ opt Model Comparison Method (Continue) (Noisy Two-Port Theory) Cascade Connection (Chain Parameter) 3 vn in Noiseless Two-Port A, 4 a 11 a 1 a 1 a C A, 3 Fmin 1 = kt Measured 4-Noise Parameters R n Y opt R n jy opt j 5 4

17 C Y 4 C i1i Λ 1 C i i Λ 1 = C Y1 + C Y C i1 i Λ C i i Λ Model Comparison Method (Continue) (Noisy Two-Port Theory) Parallel Connection (Y Parameter) 3 i1 Noiseless Two-Port i Y, 4 y 11 y1 y1 y 5 3 C Y, 5 = kt<[y ] Model

18 C Z = C Z1 + C Z Model Comparison Method (Continue) (Noisy Two-Port Theory) Series Connection (Z Parameter) 3 Noiseless Two-Port v 1 v Z, 4 z 11 z1 z1 z 5 3 C Z, C v1v Λ 1 C v 1v Λ 4 v v Λ 1 C v v Λ C 5 = kt<[z]

19 Validation for Device (4 Noise Parameters) NF min R n Minimum Noise Figure [db] Measured Frequency [GHz] nmos 100/0.5 VGS =1.5V VDS=1.5V Noise Resistance [Ω] Measured Frequency [GHz] nmos 100/0.5 VGS =1.5V VDS=1.5V

20 Validation for Device (Continue) (4 Noise Parameters) G opt B opt Optimum Conductance [ms] Measured Frequency [GHz] nmos 100/0.5 VGS =1.5V VDS=1.5V Optimum Susceptance [ms] Measured Frequency [GHz] nmos 100/0.5 VGS =1.5V VDS=1.5V

21 Validation for Circuits (Shunt-series Feedback Amplifier) R s Z in R f Z out R L Noise Figure [db] = 100MHz f = 100mA IDD Zin =Zout= 50Ω. ~ Gate Bias [V] (Y NFmin + s Yopt) Rn NF, Gs Y s >>Y opt Same jy sj Rn ß Constant Gs

22 Z in Validation for Circuits (Continue) (1/g m Termination Amplifier) 10 R s Noise Figure [db] Ω Zin= = 100MHz f Gate Bias [V] By the same reason. Validates a non-grounded source electrode condition.

23 Validation for Circuits (Continue) (Inductive Degeneration Tuned Amplifier) R s Z in Lg L s Noise Figure [db] =5mA IDD = 4GHz f 50Ω Zin= Gate Bias [V] Y opt is comparable to Y s. Another non-grounded source electrode case.

24 Validation for Circuits (Continue) (Tuned Amplifier with Cascode Stage) 5 R s Z in L g M M1 L s Noise Figure [db] DD =5mA I = 4GHz f in =50Ω Z gs;m1 =0.7V V Gate Bias of M [V] More noticeable discrepancy.

25 Conclusions First independent comparison between and models for induced gate noise. reproduces the model but introduces errors in the correlated term. In practical circuits, noticeable errors arise for very low gate bias conditions only. The two models are equivalent in most practical circuits.