A Novel Noise Cancelling Technique for CMOS Low Noise Amplifier

Transcription

1 A Novel Noise Cancelling Technique for CMOS Low Noise Amplifier Thesis submitted in partial fulfillment of the requirements for the degree of Master of Science (by Research) in Electronics & Communication Engineering by Mohd Anwar Center for VLSI & Embedded System Technologies (CVEST) International Institute of Information Technology (IIIT-H) Hyderabad , INDIA January 2015

2 Copyright 2015 by Mohd Anwar All Rights Reserved

3 INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY Hyderabad, India CERTIFICATE This is to certify that the work presented in this thesis, titled A Novel Noise Cancelling Technique for CMOS Low Noise Amplifier by Mr. Mohd Anwar, Roll No , submitted in partial fulfillment for the award of the degree of Master of Science by Research, jointly in Center for VLSI and Embedded System Technologies (CVEST), International Institute of Information Technology Hyderabad (IIIT-H) and Electrical Engineering Department (EED), Indian Institute of Technology Hyderabad (IITH), has been carried out under our supervision and is not submitted elsewhere for a degree. Advisor: Dr. Azeemuddin Syed Assistant Professor Center for VLSI & Embedded System Technologies International Institute of Information Technology Hyderabad, India Co-Advisor: Dr. Mohammed Zafar Ali Khan Associate Professor & Head of the Dept. Electrical Engineering Department Indian Institute of Technology Hyderabad, India

4 Acknowledgement First of all thanks to The Most Beneficent and The Most Merciful God for blessing me the abilities and ways to carry out my education. And, thanks to my parents and younger brothers for their kind support and patience while I was engaged in my work. I would like to express my deep gratitude to my research guide Dr. Azeemuddin Syed for his time-to-time positive critiques, patient guidance, priceless education, encouragement to improve needed skills and providing me the required funding as well as facilities during this research. I would like to offer my special thanks to my co-guide Dr. Mohammed Zafar Ali Khan for his regular advices, useful feedbacks, highlighting the different approaches for this research, providing required funding and facilities in Indian Institute of Technology Hyderabad. I would also like to thank International Institute of Information Technology Hyderabad for providing excellent infrastructure and facilities during my academics. Moreover, thanks to faculty members of CVEST for their offering of necessary courses which have provided me a good understanding related to this work. Thanks to my colleagues Mr. Bhuvanan, Mr. Vasu, Mr. Anirban, Mr. Gopi, Mr. Ajinkya, and others for many constructive discussions and their cooperation in arranging required facilities and making a joyful study environment in campus. I would also like to acknowledge industry experts Mr. Shiva and Mr. Mahboob from AMD Hyderabad, and Mr. Avinash from Bangalore for their technical help in this work. I

5 Abstract Since FCC had authorized UWB frequency range from 3.1 GHz to 10.6 GHz for wireless communication, several technologies developed for communication applications. And, demand of low cost, high data rate wireless communication systems rapidly increased. Although, current wireless design circuits built for cellular or non-cellular applications, trade-off with matching, signal detection, linearity, gain and noise parameters. In wireless receiver systems, effect of noise of all the subsequent stages is reduced by the gain of low noise amplifier (LNA) and its noise injects directly into the receiver. Thus, it is necessary to boost the desired signal power while adding as little noise and distortion as possible so that the retrieval of this signal is possible in the later stages in the system. As LNA is first block in receiver chain, it must provide high gain for the next blocks. Moreover, noise of LNA is critical, since the received input signal is extremely weak and can be easily corrupted by even small amount of thermal noise. Additionally, it is desirable to integrate the circuit with CMOS technology to achieve low cost and chip area. This block has the job of matching the antenna input with the rest of the circuitry and simultaneously amplifying it for further processing. Recent demonstrations show that LNAs ranging from few MHz to 10 GHz are included in wireless receivers which uses single LNA for contiguous broadband signal processing. And, there are various techniques to design narrow band and wide band LNAs such as design using basic common source and common gate configurations with few improvement methods such as using noise cancellation techniques. In contrast to existing LNA topologies implementing noise cancellation techniques which usually do not consider much about gain improvement, this work proposes a design of common gate LNA employing a noise cancelling technique which not only reduces the noise but also improves the gain and is novel to best of our knowledge. In order to cancel the dominant thermal noise, we have analyzed the noise contributions from both, active and passive components in an existing CG LNA. The input matching device viz. first CG transistor was identified as the most dominant noise source which contributes 42% of overall LNA noise and remains flat i.e. (2.8 ± 0.3) db over the entire range. However, second stage common source transistor contributes 22% in whole range and is more near the corner frequencies which is due to the narrow band characteristics of common source amplifiers. Hence, this work s target is to cancel the most dominant thermal noise through proposed noise cancelling technique. The proposed technique is based on combining two paths one with reversed phase noise-signal and the other with non-reversed phase noise-signal, simultaneously the RF-signals in the two paths should be in-phase. The two parallel paths were designed by symmetrical cascade combination of CG-CS and CS-CG stages. Moreover, theoretical model of noise cancellation is presented along with the derived equations of overall noise figure. Finally, implementation is done using TSMC 0.18 µm CMOSRF technology on Cadence Spectre RF tool. Significantly, II

6 proposed LNA achieve a reduction of 22.49% in base noise figure and 31.48% improvement in peak power gain when compared to LNA without noise cancelling technique. Ultimately, peak power gain of 28.4 db and base NF of 3.17 db with good stability and linearity are achieved over the spectrum from 2.5 GHz to 4.5 GHz. Additionally, this work implement a design of UWB LNA which include interstage matching network to carry forward desired signal with the stoppage of undesired signal. Also includes a Chebyshev band pass filter for input matching and a shunt-series inductive peaking network to compensate the gain roll-off at higher frequencies. This design provides a peak power gain of db and base noise figure 3.4 db within the frequency range from 3.1 GHz to 10.6 GHz. Also demonstrate a good input matching i.e. well below -10 db in the desired frequency range. The entire circuit consumes 11.2 mw with 1.8 V supply and occupies 1 mm x 0.9 mm of layout area. Moreover, a detailed survey of various existing methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. III

7 Contents: Acknowledgement Abstract List of Figures List of Tables Abbreviations Award and Publications Page No. I II VI VIII IX XI 1. Introduction 1.1. Motivation 1.2. Contributions of this thesis 1.3. Outline of this thesis 2. Background 2.1. Design methodologies of CMOS low noise amplifier Narrow band and wideband design methods Noise reduction and gain improvement methods 3. A CMOS LNA employing a novel noise cancelling technique 3.1. Introduction 3.2. Investigation for major noise sources in existing CG LNA 3.3. A novel noise cancelling technique for CG UWB LNAs 3.4. A high gain reduced NF CMOS LNA employing novel noise cancelling technique 3.5. Results and analysis Performance summary 3.6. Conclusion and limitations 4. Other Work on Low Noise Amplifier 4.1. Introduction 4.2. A CMOS LNA with Peaking and Inter-stage Matching Input impedance matching stage Inter-stage matching Shunt-series inductive peaking and gain stage Noise analysis 4.3. Simulation results 4.4. Conclusion and limitations IV

8 5. Layout Techniques 6. Summary and Conclusions 6.1. Summary 6.2. Conclusions 6.3. Recommendations for future research Appendix A Appendix B Bibliography V

9 List of Figures: Figure No. Page No. Chapter Block diagram of a UWB receiver Improvement of receiver sensitivity due to LNA: (a) without LNA (b) with noiseless LNA (c) with LNA noise (all values are in db) 2 Chapter (a) common gate configuration (b) cascode common gate configuration Feed forward noise cancelling technique CG-CS single ended to differential output configuration Single ended noise cancelling LNA Two stage noise canceling LNTA configuration Composite type inductor less noise cancelling LNA (a) Simplified schematic architecture (b) Half circuit model (c) Composite NMOS/PMOS transistors 11 Chapter LNA without noise cancellation Noise contribution by LNA components for entire range of 3.1 GHz to 10.6 GHz Noise figure contribution of LNA major components at all frequencies Noise cancellation concept for LNA Major noise sources of LNA Proposed LNA with noise cancellation technique (biasing not shown) Two transistor analog RF adder and its simplified small signal equivalent circuit Simulated noise figure plot for proposed LNA with noise cancellation Simulated power gain plot for proposed LNA with noise cancellation Simulated input reflection coefficient plot for proposed LNA with noise cancellation Simulated and theoretical noise figure plots for LNA with noise cancellation Simulated stability factor plot for LNA with noise cancellation Simulated IIP3 plot for proposed LNA AC analysis of RF adder Transient analysis of RF adder Layout of the proposed LNA 22 VI

10 Chapter Simplified schematic of UWB LNA Equivalent circuit of input impedance matching network Equivalent circuit of UWB LNA with matching networks Equivalent circuit of input impedance of second stage Load of first stage Load of second stage Noise model of the input matching network Simulated noise figure of UWB LNA Simulated input reflection coefficient of UWB LNA Simulated forward transmission gain of UWB LNA Layout of the UWB LNA 33 Chapter Transistor fingering and poly routing with its response Metal connection immediately after poly with its response Array of capacitors connection Single and multiple parallel vias with its response Placing of M1 transistor near to input terminal Supply wires routed with top metal layer Wide wires connected to input transistor 40 Appendix A A.1 Idea of noise cancellation with additional gain block 43 A.2 Proposed noise cancelling LNA with phases of noise signal and RF signal at different nodes 44 A.3 Noise contributing components for noise figure calculation (a) left branch containing CG-CS transistors (b) right branch containing CS-CG transistors 44 Appendix B B.1 LNA with Inductor as an inter stage impedance network 48 B.2 Equivalent circuit for calculation of input and output impedances of two stages 49 B.3 Equivalent circuit for calculation of output impedance of first stage 49 B.4 Equivalent circuit for calculation of input impedance of second stage 51 B.5 LNA with LC network between two stages 53 B.6 Equivalent circuit for the calculation of input and output impedances of two stages 53 B.7 Equivalent circuit setup for the calculation of input impedance of second stage 53 VII

11 List of Tables: Table No. Page No. Chapter Aspect ratios and parameter values of proposed circuit Performance summary of the noise cancelling LNA 23 Chapter Performance summary of the UWB LNA 34 VIII

12 Selected Symbols and Abbreviations: Symbol Meaning LNA Low noise amplifier VGA Voltage gain amplifier LO Local oscillator LPF Low pass filter BPF Band pass filter DSP Digital signal processing FCC Federal Communications Commission CMOS Complementary metal oxide semiconductor SNR Signal to noise ratio SNR min Minimum signal to noise ratio which receiver can sense S Signal N RX Noise of the receiver RX Receiver G Gain of low noise amplifier (used in receiver architecture) db Decibel CS Common source CG Common gate RF Radio frequency TSMC Taiwan Semiconductor Manufacturing Company µm Micro meter UWB Ultra wideband NF Noise figure MHz Mega hertz GHz Giga hertz Q Quality factor of inductor NB Narrow band WB Wide band DC Direct current R f (or) R F Feedback resistance A v Voltage gain Z in Input impedance g m Transconductance of MOSFET ms Milli Semen s Ω Ohm T Absolute temperature IX

13 k γ f T MOSFET V S R S V n V out V b IIP3 LNTA NMOS PMOS g m,n g m,p g m,eff C gd C gs L M C by C pad L LD R LD L G2 C g L S W(s) C t Z o ρ Z in1 Z in1 ' Z in2 Z in2 ' Z o1 V gs I cgs V x Boltzmann constant Transistor parameter Unity gain frequency Metal oxide semiconductor field effect transistor Source voltage Source resistance Noise voltage Output voltage Biasing voltage Third order input intercept point Low noise transconductance amplifier N type MOSFET transistor P type MOSFET transistor Transconductance of N type transistor Transconductance of P type transistor Effective transconductance Gate drain capacitance of MOSFET transistor Gate source capacitance of MOSFET transistor Inductor connected in between two stages of UWB LNA Bypass capacitance Pad capacitance Load inductor Resistance of load inductor Inductor connected at gate terminal of second stage transistor Capacitor connected at gate of transistor Inductor connected at source terminal of first stage transistor (Degeneration inductor ) Transfer function of band pass filter Total capacitance Characteristic impedance Ripple factor of band pass filter Input impedance of UWB LNA without gate inductor Input impedance of UWB LNA with gate inductor Second stage input impedance of UWB LNA with interstage LC passive network Second stage input impedance of UWB LNA with interstage inductor Output impedance of first stage of UWB LNA Gate source voltage Current flowing through gate source capatance Test voltage for input or output impedance calculation X

14 I x X cgs r ds (or) r o M Test current for input or output impedance calculation Equivalent impedance of gate source capacitance Drain source resistance of MOSFET Mutual inductance Award and Publications: Award: Commendation Award from International Institute of Information Technology Hyderabad for commendable contributions and involvement in the campus life activity. (2014) Publications related to this thesis: M. Anwar, S. Azeemuddin, M.Z.A. Khan, Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs, International Symposium on VLSI Design & Testing (VDAT), Springer CCIS 382, pp , July M. Anwar, S. Azeemuddin, M.Z.A. Khan, A CMOS UWB LNA with Shunt-Series Inductive Peaking and Interstage Matching, IEEE Applied Electromagnetics Conference, Dec Other publication: S. Sharma, S. Azeemuddin, M. Anwar A self learning VLSI Lab along with Web-based Platform to design Schematics and Layouts, IEEE International Conference on Technology for Education (T4E), pp July VLSI virtual lab on web: XI

15 Chapter-1 Introduction 1.1 Motivation Low noise amplifier is an important block in wireless receiver system. This block has the job of matching the antenna input with the rest of the circuitry and simultaneously amplifying it for further processing. A simplified block diagram of wireless receiver is shown in Figure 1.1. Figure 1.1: Block diagram of a UWB receiver Since the international and national authorities in different parts of the world had allotted frequency bands for wireless communication applications, such as, in North America, allotted UWB range is GHz, in Europe GHz, in Japan GHz or GHz, several technologies developed for communication market [1-3]. Although, demand of low cost and high data rate wireless communication increased, however, matching, signal detection, gain and noise challenges in current wireless design are yet to be confronted with. As LNA is first block in receiver chain, it must provide high gain for the next blocks. Noise is critical in this block since the input is extremely weak and can be easily corrupted by even small amounts of thermal noise. Additionally, it is desirable to integrate with CMOS technology to achieve low cost and chip area. The need of low noise amplifier for the improvement of receiver sensitivity is discussed in this part of the introduction section. Figure 1.2 shows three different cases of receiver in which SNRa, SNRb and SNRc are signal to noise ratios for cases (a), (b) and (c) respectively. First, when LNA is not placed at the front end of the receiver, the value of receiver noise, NRX, is significantly comparable to signal strength, S, hence SNRa < SNRmin. Second, a noiseless LNA is placed at the front end of the receiver, and due to the gain (G) of LNA, the signal to noise ratio - 1 -

16 becomes much greater than the SNRmin, hence sensitivity of the receiver improves significantly. However, practical LNA contributes an amount of noise to the receiver as represented in case (c). In this case, the noise of LNA, NLNA, directly adds with the receiver noise and reduces the SNR at the input than in case (b). Nevertheless, SNRc value is more than the SNRmin, and less than SNRb. Hence, to maintain this condition, large LNA gain is an essential requirement. Moreover, the noise contribution of large gain LNA is dominant in overall receiver noise at the input which can be illustrated from the noise expression in case (c). Hence, the LNA noise should be as less as possible to achieve better sensitivity. S Signal = S Noise =N RX SNR a = (S-N RX ) SNR a <SNR min (a) N RX RX (b) S Signal = S Noise =N RX -G SNR b = S-(N RX - G) = S+G-N RX N RX -G LNA SNR b >SNR min N RX RX Gain= G (c) S Signal = S Noise =(N RX -G)+ N LNA SNR c = S-{(N RX - G)+N LNA } = S+G-N RX -N LNA SNR b >SNR c >SNR min >SNR a N RX -G N RX LNA RX N LNA Gain= G Figure 1.2: Improvement of receiver sensitivity due to LNA: (a) without LNA (b) with noiseless LNA (c) with LNA noise (all values are in db) 1.2 Contributions of this thesis This thesis proposes a noise cancelling technique for CMOS low noise amplifier which not only reduces the noise but also improves the gain and is novel to best of our - 2 -

17 knowledge. In order to cancel the dominant noise, we analyzed the noise contributions from both active and passive components in an existing three stage CG LNA. The input matching device viz. first CG transistor was identified as the most dominant noise source. Theoretical model of noise cancellation is presented along with the derived equations based on two port model of overall noise figure. The circuit implementation is done using TSMC 0.18 µm CMOSRF technology on Cadence Spectre RF tool. This thesis also implement a design of CMOS UWB LNA with shunt-series inductive peaking and interstage matching. This design includes inductive source degeneration cascode topology with interstage matching network. Additionally a Chebyshev band pass filter at the input and shunt-series inductive peaking at the output are placed which provide better impedance matching and improved power gain. A detailed survey of various existing design techniques of low noise amplifier is also presented. In this survey, the design methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. 1.3 Outline of this thesis The outline of this thesis is described below. Chapter 2 presents a detailed discussion of various existing design topologies of low noise amplifiers. In this, the design methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. LNA design topologies such as design using common source and common gate configurations along with their drawbacks rectifications are discussed. The goal to achieve an LNA design with high gain and low noise figure is pursued seeking radically different existing design approaches. Chapter 3 starts with an investigation of major noise sources in a three stage common gate low noise amplifier. Thereafter, a novel noise cancelling technique with theoretical analysis for common gate low noise amplifiers is proposed. Moreover, design of common gate low noise amplifier employing proposed noise cancelling technique is implemented which not only reduces the noise but also increases the gain. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this chapter. On implementing this technique, significant reduction of noise figure (NF) was observed. At the end of this chapter, simulation results and performance summary are discussed. Chapter 4 focuses on a broadband design of low noise amplifier. In this chapter, a CMOS UWB LNA is designed with shunt-series inductive peaking and interstage matching. Theoretical analysis with small signal equivalent models of input impedance matching, interstage matching - 3 -

18 and shunt-series inductive peaking stages are presented. Moreover, the gain and noise models with derived equations of different stages are described. The design and analysis includes inductive source degeneration cascode topology with interstage matching network. Additionally a Chebyshev band pass filter at the input and shunt-series inductive peaking at the output are placed which provide better impedance matching and improved power gain. Simulation results and conclusions are available at the end of this chapter. Chapter 5 draw conclusions and the original contributions are summarized. Finally few recommendations for further research are given

19 Chapter-1 Introduction 1.1 Motivation Low noise amplifier is an important block in wireless receiver system. This block has the job of matching the antenna input with the rest of the circuitry and simultaneously amplifying it for further processing. A simplified block diagram of wireless receiver is shown in Figure 1.1. Figure 1.1: Block diagram of a UWB receiver Since the international and national authorities in different parts of the world had allotted frequency bands for wireless communication applications, such as, in North America, allotted UWB range is GHz, in Europe GHz, in Japan GHz or GHz, several technologies developed for communication market [1-3]. Although, demand of low cost and high data rate wireless communication increased, however, matching, signal detection, gain and noise challenges in current wireless design are yet to be confronted with. As LNA is first block in receiver chain, it must provide high gain for the next blocks. Noise is critical in this block since the input is extremely weak and can be easily corrupted by even small amounts of thermal noise. Additionally, it is desirable to integrate with CMOS technology to achieve low cost and chip area. The need of low noise amplifier for the improvement of receiver sensitivity is discussed in this part of the introduction section. Figure 1.2 shows three different cases of receiver in which SNRa, SNRb and SNRc are signal to noise ratios for cases (a), (b) and (c) respectively. First, when LNA is not placed at the front end of the receiver, the value of receiver noise, NRX, is significantly comparable to signal strength, S, hence SNRa < SNRmin. Second, a noiseless LNA is placed at the front end of the receiver, and due to the gain (G) of LNA, the signal to noise ratio - 1 -

20 becomes much greater than the SNRmin, hence sensitivity of the receiver improves significantly. However, practical LNA contributes an amount of noise to the receiver as represented in case (c). In this case, the noise of LNA, NLNA, directly adds with the receiver noise and reduces the SNR at the input than in case (b). Nevertheless, SNRc value is more than the SNRmin, and less than SNRb. Hence, to maintain this condition, large LNA gain is an essential requirement. Moreover, the noise contribution of large gain LNA is dominant in overall receiver noise at the input which can be illustrated from the noise expression in case (c). Hence, the LNA noise should be as less as possible to achieve better sensitivity. S Signal = S Noise =N RX SNR a = (S-N RX ) SNR a <SNR min (a) N RX RX (b) S Signal = S Noise =N RX -G SNR b = S-(N RX - G) = S+G-N RX N RX -G LNA SNR b >SNR min N RX RX Gain= G (c) S Signal = S Noise =(N RX -G)+ N LNA SNR c = S-{(N RX - G)+N LNA } = S+G-N RX -N LNA SNR b >SNR c >SNR min >SNR a N RX -G N RX LNA RX N LNA Gain= G Figure 1.2: Improvement of receiver sensitivity due to LNA: (a) without LNA (b) with noiseless LNA (c) with LNA noise (all values are in db) 1.2 Contributions of this thesis This thesis proposes a noise cancelling technique for CMOS low noise amplifier which not only reduces the noise but also improves the gain and is novel to best of our - 2 -

21 knowledge. In order to cancel the dominant noise, we analyzed the noise contributions from both active and passive components in an existing three stage CG LNA. The input matching device viz. first CG transistor was identified as the most dominant noise source. Theoretical model of noise cancellation is presented along with the derived equations based on two port model of overall noise figure. The circuit implementation is done using TSMC 0.18 µm CMOSRF technology on Cadence Spectre RF tool. This thesis also implement a design of CMOS UWB LNA with shunt-series inductive peaking and interstage matching. This design includes inductive source degeneration cascode topology with interstage matching network. Additionally a Chebyshev band pass filter at the input and shunt-series inductive peaking at the output are placed which provide better impedance matching and improved power gain. A detailed survey of various existing design techniques of low noise amplifier is also presented. In this survey, the design methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. 1.3 Outline of this thesis The outline of this thesis is described below. Chapter 2 presents a detailed discussion of various existing design topologies of low noise amplifiers. In this, the design methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. LNA design topologies such as design using common source and common gate configurations along with their drawbacks rectifications are discussed. The goal to achieve an LNA design with high gain and low noise figure is pursued seeking radically different existing design approaches. Chapter 3 starts with an investigation of major noise sources in a three stage common gate low noise amplifier. Thereafter, a novel noise cancelling technique with theoretical analysis for common gate low noise amplifiers is proposed. Moreover, design of common gate low noise amplifier employing proposed noise cancelling technique is implemented which not only reduces the noise but also increases the gain. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this chapter. On implementing this technique, significant reduction of noise figure (NF) was observed. At the end of this chapter, simulation results and performance summary are discussed. Chapter 4 focuses on a broadband design of low noise amplifier. In this chapter, a CMOS UWB LNA is designed with shunt-series inductive peaking and interstage matching. Theoretical analysis with small signal equivalent models of input impedance matching, interstage matching - 3 -

22 and shunt-series inductive peaking stages are presented. Moreover, the gain and noise models with derived equations of different stages are described. The design and analysis includes inductive source degeneration cascode topology with interstage matching network. Additionally a Chebyshev band pass filter at the input and shunt-series inductive peaking at the output are placed which provide better impedance matching and improved power gain. Simulation results and conclusions are available at the end of this chapter. Chapter 5 draw conclusions and the original contributions are summarized. Finally few recommendations for further research are given

23 Chapter 2 Background Overview: This chapter presents a detailed survey of various existing design techniques of low noise amplifier. In this survey, the design methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons. Although, few methods are improved versions of basic design topologies and achieve better performance in parameters than earlier, however, trade-off remains with the other parameters. 2.1 Design methodologies of CMOS low noise amplifier In wireless receiver systems, effect of noise of all the subsequent stages is reduced by the gain of LNA and its noise injects directly into the receiver. Thus, it is necessary to boost the desired signal power while adding as little noise and distortion as possible, so that the retrieval of this signal is possible in the later stages of the system. Recent demonstrations show that LNAs ranging from few MHz to 10 GHz are included in wireless receivers which uses single LNA for contiguous broadband signal processing [4-6]. There are various techniques to design narrow band and wide band LNAs such as design using basic common source and common gate configurations with few improvements. Common source configuration with inductive degeneration LNA provides good input matching for wide band range but requires a passive network at the input which consists large number of high Q inductors. Moreover, LNA of this configuration shows good noise performance for narrow band (NB) applications but not at corner frequencies for wide band applications [7]. In this section, we review various design topologies of existing LNAs and noise cancelling methods Narrow band and wideband design methods There are few well known basic design topologies of LNA which can achieve the minimum performance with some drawbacks. First, common source amplifier with resistive load is a basic and simple LNA topology. It does not provide proper impedance matching and time constant (RC) at the output prohibits the operation at high frequencies; also resistive load consumes more DC voltage [8]. In contrast, common source amplifier with inductive load consumes less DC voltage across inductor (ideally zero DC voltage drop). Moreover, inductive load resonates with total capacitance at the output node, affording much higher frequency than common source amplifier with resistive load. However, this topology faces the performance degradation due to the - 5 -

24 significant parasitic capacitances and not enough isolation between input and output, and so rarely used in modern RF design. Cascode common source with inductive degeneration topology provides isolation between input and output; also separates the inductive load with the input resistance. Another topology of common source amplifier is with the resistive feedback. In this topology, the feedback resistance (Rf) senses the output voltage and returns a current to the input. This topology does not suffer from a direct trade-off between gain and supply because Rf carries no bias current and provides flat gain (Av = ½(1-Rf/Rs)). Moreover, this topology provides good wideband input matching as, Zin=1/gm, if gm = 20 ms then Zin = 50 Ω. The approximate expression for noise figure of this topology, (1+ γ + γgmrs), shows that noise figure exceeds 3 db. However, this topology can be considered if the desired operation of frequency is less than the ft of the transistor. In addition, LNA design with common gate configuration as shown in Figure 2.1(a) provides ultra wide band input matching due to its low input impedance (1/gm), resulting in an improved reverse isolation and therefore provides better stability. Indeed, a 50 Ω input matching can be obtained just by setting the gm of the input MOSFET at the value of 20 ms. Drawback of this topology is that simultaneous power and noise performance is not possible. So if this LNA architecture is used without additional techniques such as noise cancellation, the noise figure is very high. Moreover, noise figure of CG LNA is considerably large when compared to CS LNA but it can be improved by using gm boosting technique which trades off with gain [34]. The noise figure of common gate LNA is given by equation (2.1 and 2.2). NF = 1+ γ g m R s + R s R 1 (1+ =1+ γ+4 R s R ) g m R s (2.1) (2.2) (a) V b1 M1 R 1 V out C 1 (b) V b2 M2 R 1 V out C V b1 M1 V S R S V S R S Figure 2.1: (a) common gate configuration (b) cascode common gate configuration - 6 -

25 From equation (2.1), this can be observed that a higher gm yields a low NF but also a lower input impedance. Therefore, NF can be lower if impedance mismatch is permitted at the input (a tradeoff between Zin and NF). Chen et al. has used the common gate topology to design an UWB LNA in a 0.18 µm CMOS technology [9]. The first stage is a common gate stage with a bandwidth enhancing inductor, and the second stage is a cascode stage with an inductive series peaking. As expected the noise figure is high especially in the high frequency range. In contrast to the common source LNA, the contribution of load resistance (R1) noise to the NF in CG is more. We know for CG LNA that the voltage gain from input to the output node at the resonance frequency is equal to R1/Rs. Equation for noise figure of CG LNA indicates that R1 s noise contribution i.e. 4Rs/R1, is equal to 4 divided by the voltage gain from the input source to the output. Thus, for a typical gain of 10, this contribution reaches 0.4, a significant amount. For inductive degenerated CS LNA, the R1 s contribution is equal to 4Rs/R1 multiplied by (ω0/ωt) 2. Thus, for operating frequency well below the ft of the transistor, the noise contribution of R1 becomes negligible. An alternative approach to lowering the input impedance in CG LNAs is to add a cascode transistor as shown in Figure 2.1(b), however, in approximation, input impedance remains 1/gm. Although, the addition of cascode device entails two issues: the noise contribution of cascode transistor and the voltage headroom limitation due to stacking two transistors. Distributed Amplifiers: The principle of the distributed amplifier is to produce two artificial transmission lines coupled by several elementary amplifiers. The input and output capacitor of the elementary amplifiers are all or part of the capacitors constituting the transmission lines. The inductive part of the artificial transmission lines is synthesized by either inductors or by sections of transmission lines. In this topology the amplifier stages are not cascaded, but in parallel. Therefore distributed amplifiers provide lower gains compared with other architectures, but theirs main advantage is the ability to achieve very large bandwidths, lower boundary in MHz and upper boundary in 10 s GHz with good linearity and input-output matching. The main disadvantages are the silicon area used to synthesize artificial transmission lines, and a heavy DC power consumption resulting from the numerous stages commonly required to obtain a high gain value and occupying significant chip area. Zhang et al. has used a distributed amplifier architecture to design a UWB LNA in a 0.18 µm CMOS technology [10]. The strength of this design is the power consumption which is below 10 mw. This low DC power consumption for a distributed amplifier has been obtained by using a low number of stages and also by biasing the MOS transistors in a weak inversion mode. But, as expected, the power gain is low (8 db) and also the silicon area is high (1.16 mm 2 ) because of the great number of spiral inductors. Heydari et al. has also used a distributed amplifier architecture in a 0.18 µm CMOS technology [11]. The originality of this design is to use bandwidth enhancing inductors. So the full FCC bandwidth is obtained with a good noise figure but with high power consumption (21-7 -

26 mw). However, the gain is low (8 db) and the number of inductors very high (11 spiral inductors). Amplifiers with LC-Filters: In LC filter amplifier architecture the input matching cell is designed with inductors and capacitors like in a standard band-pass filter. The strength of this architecture is to provide a well-controlled band-pass response. This band-pass response reduces the noise equivalent bandwidth and so the noise output voltage. The main drawback is to need of more number of inductors and so low silicon area cannot be addressed with this architecture. Bevilacqua et al. has implemented a third order band-pass input matching cell in a 0.18 µm CMOS technology [12]. This LNA uses five spiral inductors and consequently consumes a large silicon area. The power consumption is low (9 mw) but the noise figure is high especially in the high frequency range Noise reduction and gain improvement methods Recently, few topologies implementing noise cancellation techniques have reported. The thermal noise cancellation technique which uses resistive feed forward CS configuration was implemented for an LNA operating below 2 GHz [13, 14]. However, this technique was extended to higher frequencies by using inductive peaking which shows reduction in noise figure in GHz frequency range [15]. In addition, various other noise cancellation techniques [16-21] have been reported in literature such as simultaneous noise and third order distortion cancellation technique in CG-CS cascade LNA operating till 2.1 GHz [16, 17] and resistive feed forward noise cancellation technique in two stage differential transconductance LNA operating till 4.5 GHz [18]. However, few reported topologies are based on trade-off optimization [22-26]. Hence it is evident that noise cancellation techniques usually do not consider much about gain improvement. Feed-forward noise cancelling Technique: Feed forward noise cancelling technique, shown in Figure 2.2, lowers the noise figure within the targeted band and breaks the trade-off between noise factor and input impedance. Feed forward configuration senses the desired signal and cancel the thermal noise and distortion of the input transistor along with the noise of its biasing circuit. The main advantage of this type of LNA is, it consume less power and occupy small chip area with good stability. However, it operates below 2 GHz as reported in [13]

27 X R F Y M1 Out V S R S -A v Z Figure 2.2: Feed forward noise cancelling technique In this configuration, there is an auxiliary voltage-sensing amplifier and a matching amplifier. These amplifiers are placed in such a way that the noise from the matching device cancels at the output, while adding signal contributions. As shown in figure, thermal noise current generated from the channel of the transistor flows through the feedback resistance and have same polarity at node X and Y, but the signal, on the other hand, experiences inversion. However, due to a voltage-sensing amplifier connected between input and output, the signal becomes in phase and noise becomes out of phase, which, on combining, cancels the noise components and adds the signal components at the output. CG-CS noise cancelling technique: This topology of noise cancellation, shown in Figure 2.3, is single-ended to differential output [8]. The noise of CG transistor i.e. Vn1 follows common drain path to input node, X, and common source path to output path, Y, exhibit opposite polarities at these two nodes. And, the signal follows CG path through X and Y, exhibiting the same polarity. In a condition when input is matched, transistor M1 produces half of its noise voltage at X. Common source transistor, a voltage sensing amplifier, connected between input and output, senses this noise and amplifies it by a factor of gm2r2. Hence, for the noise cancellation, the two output should have equal noise voltages i.e. gm1r1vn1/2 = gm2r2vn1/2 and reverse polarities. X R 1 R 2 V out Y V b1 M1 V S R S M2 Figure 2.3: CG-CS single ended to differential output configuration Niknejad et al. has presented an improved noise cancelling LNA design as shown in Figure 2.4, which simultaneously exploits the noise and distortion cancellation [27]. This design - 9 -

28 includes a cascaded common gate and common source configuration, the simplified topology is shown in Figure 2.4. This LNA achieves, gain of 14.5 db with NF 2.6 db and a peak IIP3 +16 db over a bandwidth from 800 MHz-2.1 GHz using 0.13 um CMOS technology. R 1 R 2 V out M4 V b1 M1 M3 V S R S M2 Figure 2.4: Single ended noise cancelling LNA Two stage noise cancelling LNTA: This technique includes two stages, first stage is LNA which provides input matching in the frequency band of interest and the second stage translates the voltage signal into current. The main noise contributor is transistor M1. The drain noise current of M1 flows through RF and RS generating noise voltages at both nodes X and Y. Noise voltages at nodes X and Y are in-phase but have different amplitudes which depend on the values of R and Rs. First stage gain of the LNA is given in equation (2.3) where the noise voltage Vn, Y is approximately A times of Vn,X. A R/Rs Vn, Y/ Vn, X (2.3) V S R S X R F Y M1-1 Second Stage A Z Out Figure 2.5: Two stage noise canceling LNTA configuration Therefore, if Vn, X is amplified by A and subtracted from Vn, Y, then it is possible to cancel them out as depicted in Figure 2.5. In [18], it is reported that the LNTA achieves 14 db first

29 stage gain and 115 ms for two stages, with 3.62 db in band NF over 4.5 GHz 3 db bandwidth. However, LNTA consumes 40 mw of power. Composite type noise cancelling LNA: The LNA architecture shown in Figure 2.6(a) is similar to conventional broadband LNA with resistive matching, however, the overall NF is reduced due to the composite configuration of NMOS and PMOS transistor which are connected in series [28]. This configuration amplifies the differential voltage and rejects the common-mode one. Due to series configuration of the two transistors, shown in Figure 2.6(c), the effective transconductance, gm,eff, is represented by the series combination of the NMOS and PMOS transistors. And, the value of effective transconductance is given by equation (2.5). As a result, the output current is given by equation (2.4). i o = g m, eff (V 1 -V 2 ) (2.4) g m, eff = g m, n g m, p g m, n + g m, p (2.5) R 1 V op R F (a) R F R 1 V on (b) R F R 1 V on M N1 M P1 R b V in V ip R S V S R b M N1 M P1 V ip V in R b M N1 M P1 V 1 gm n gm eff(v 1 -V 2 ) V 2 gm p Figure 2.6: Composite type inductorless noise cancelling LNA (a) Simplified schematic architecture (b) Half circuit model (c) Composite NMOS/PMOS transistors Where gm,n and gm,p are the transconductance of the NMOS and PMOS transistors, respectively. The cross connection leads to partial noise cancellation of the noise generated by the NMOS and PMOS transistors. (c)

30 Chapter 3 A CMOS LNA employing a novel noise cancelling technique Overview: This chapter presents a design of common gate low noise amplifier (LNA) employing an innovative noise cancelling technique which not only reduces the noise but also increases the gain. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this chapter. On implementing this technique, significant reduction of noise figure (NF) was observed. 3.1 Introduction In this work, we propose a design of common gate LNA employing a noise cancelling technique which not only reduces the noise but also improves the gain and is novel to best of our knowledge. In order to cancel the dominant noise, we analyzed the noise contributions from both active and passive components in CG LNA reported in [29]. The input matching device viz. first CG transistor was identified as the most dominant noise source. The technique is based on combining two paths one with reversed phase noise signal and the other with non-reversed phase noise signal, simultaneously the RF signals in the two paths will be in-phase. The two parallel paths were designed by symmetrical cascade combination of CG-CS and CS-CG stages. Theoretical model of noise cancellation is presented along with the derived equation based on two port model of overall noise figure, and implementation is done using TSMC 0.18 µm CMOSRF technology on Cadence Spectre RF tool. 3.2 Investigation for major noise sources in existing CG LNA A three stage LNA as shown in Figure 3.1 is taken for detailed analysis and identification of noise sources [29]. First stage is a CG stage followed by cascode CS stage and resistive feed forward cascode CS stage with a buffer at the output. As expected, major noise contribution of this LNA is from the CG transistor (M1) which is approximately 42% over the entire range of GHz shown in Figure 3.2, extracted from noise simulation results. Second stage CS transistor (M2) contributes 22% for the entire range and its noise contribution is more near the corner frequencies. This is due to the restriction of narrow band characteristics of CS amplifier while CG amplifier shows WB characteristics and its noise contribution is almost equal (2.8 ± 0.3) db for the entire range as shown in Figure 3.3. Third stage noise contribution is negligible as it receives the amplified signal from the earlier two stages. Therefore, it is desirable to suppress the noise contribution of M

31 RF Input Lo V b3 V b5 M3 V b1 M1 L 2 M2 L 1 Rf M5 M4 L L M6 RF Output Figure 3.1: LNA without noise cancellation M1 42% M2 22% M5 L1 other 5% L2 6% Lo 11% M4 9% M3 5% Figure 3.2: Noise contribution by LNA components for entire range of 3.1 GHz to 10.6 GHz Noise Figure (db) Frequency (GHz) 3.1 GHz GHz M M Lo M f N F (db) Figure 3.3: Noise figure contribution of LNA major components at all frequencies

32 3.3 A novel noise cancelling technique for CG UWB LNAs Hence, noise cancelling circuit was designed in order to cancel the noise generated by M1. Figure 3.4 shows simplified noise cancelling technique in which, is thermally generated channel noise current equal to 4kTγgm1Δf. Equivalent noise voltage, at the gate of M1 is 4kTγΔf/gm1. And, we observe a phase shift of 180 o in noise voltage at node B with respect to, at the gate of M1 because of CS stage (source of M1 is common terminal) while it is inphase at node A because of source follower stage (drain of M1 is common terminal). Therefore, noise voltage at node A and at node B becomes 180 o out-of-phase. After that, there is a phase shift of 180 o between the noise voltages at node A and node C because of CS stage (M2) and hence the noise voltage at node B and node C are in-phase. This CS amplifier (M2) also amplifies the RF input signal Vs. I 2 n, M 1 2 V n,m 1 Figure 3.4: Noise cancellation concept for LNA The noise voltage generated by M1 is observed to be in-phase at nodes C and D due to CG stage (M3). While, the noise voltage at node E is 180 o out-of-phase with respect to noise voltage at node B due to CS stage (M4). This finally results in noise voltages at nodes D and E to be 180 o out-of-phase and hence is cancelled by adding them at the output. Simultaneously, RF input signal is amplified through paths A-C-D and A-B-E and the phase shift in both these paths are identical. Finally, the amplified RF signal at node D and E are in-phase and hence added at the output through an adder circuit. Hence this topology amplifies the RF input signal and simultaneously cancels the noise of most dominating thermally generated noise source

33 2 V n,x4 2 V n,xo 2 Vn,X1 2 Vn,M4 2 Vn,M3 2 Vn,M1 2 Vn,M2 2 V n,rs 2 Vn,X2 Figure 3.5: Major noise sources of LNA For theoretical analysis of proposed design, noise sources of first two stage components are shown in Figure 3.5. Theoretical values of noise voltages for transistors and resistors are 4kTγΔf/gmi and4. Where k is Boltzmann constant, T is absolute temperature, γ is transistor ktri parameter, g is transconductance of i th transistor, Ri, and Xi are equivalent resistor and impedance associated with i th inductor respectively. In the analysis below, it is assumed that the noise of M1 is being cancelled and remaining components of first two stages are contributing to overall noise figure. Let and are noise factors at two different output nodes z and z' as shown in Figure 3.5. Equations (3.3, 3.4 and 3.6) are derived for, and overall noise factor of the circuit considering first two stages are having major contribution in noise: F z =1+ Noise power at node z due to R, R, R, M Noise power at node z due to R (3.1) F z' =1+ Noise power at node z' due to R, M, M, R Noise power at node z' due to R (3.2) R F z = 1+ g m1 X 2 + R 2 R 4 γ + R 4R s s g m1 g m4 X X R g m1 X o 2 g m4 R α α 4 (3.3)

34 R 1 F z' = 1+ R g m2 X γ 2 2 α g 2 m2 R α 2 (3.4) F = 1 + (F z - 1) + (F z' - 1) (3.5) R R 4 F = 1+ R 2 + 4R g m1 X o 2 + R s g m1 g m4 X o X R γ g m1 X o 2 g m4 R α 1 2 α R 1 R g m2 X 1 2 α 2 2 (3.6) Equations (3.7 and 3.8) describe the noise factors of M1 at z and z' respectively and a term r is defined as the ratio of these two noise factors as given in equation (3.9). Moreover, term r signifies the fraction of noise of M1 cancelled at the output and for the condition of complete noise cancellation, the value of r should ideally be equal to one. Noise factor of M1 at z = Noise factor of M1 at z' = γ g X r 4kTR (3.7) γ X 2 R s X 2 R s +1 g m1 4kTR (3.8) r = Noise of M1 at z Noise of M1 at z' (3.9) 3.4 A high gain reduced NF CMOS LNA employing novel noise cancelling technique Figure 3.6 shows schematic of the proposed LNA topology. In addition to the conceptual design shown in Figure 3.4, extra gain stages i.e. resistive feed forward cascode CS stage marked by A are added to improve the overall signal gain and bandwidth of amplifier. Additionally, noise cancellation is achieved by combining the outputs of these gain stages with an adder circuit

35 Figure 3.6: Proposed LNA with noise cancellation technique (biasing not shown) Realization of analog RF adder: Figure 3.7 shows schematic of an analog RF adder which is realized with a pair of complementary transistors. In this circuit, small signal modulated currents generated by the signals at the gate of the transistors flow through the load which results in addition of signal voltages across load. Moreover, the addition of small signal transistor currents results in addition of RF signal at the output. And, the voltage across the load is constituted by an addition of signal voltages. v 2 M p v o i p r op v o v 1 M n Z L i n r on Z L Figure 3.7: Two transistor analog RF adder and its simplified small signal equivalent circuit Let, v1 and v2 are the input signals applied to the gate terminal of the transistors, in and ip are channel currents in NMOS and PMOS transistors respectively. From the small signal analysis of adder circuit, the expression for output voltage (vo) is given in equations ( ). v = - (r r Z )(i + i ) (3.10)

36 v = - (r r Z )(g v + g v ) (3.11) v = - (r r Z )(g v + g v ) (3.12) If ron rop high; ZL = 50 Ω and gmn = gmp = 20 ms then vo v1 + v2. But practical realization of adder does not have gm1 gm2 20 ms. So the output voltage of adder is not exact addition of voltages from two branches which results in degeneration in amplifier gain and in noise figure as well. Hence, there is a trade-off among impedance matching, gain and noise figure. Figure 3.14 and Figure 3.15 show AC and transient analysis results of designed adder which demonstrate the addition phenomenon of two signals. 3.5 Results and analysis The proposed noise cancelling LNA topology is designed for operating from frequency range of 2.5 GHz to 4.5 GHz. Small size of M1 transistor demonstrates wideband input matching characteristic. Transconductance (gm1) of M1 transistor is fixed at 20 ms for 50 Ω input matching with bias current of 1.8 ma and L2 is 5.10 nh, which keeps input reflection coefficient well below -10 db over the entire range of 2.5 GHz to 4.5 GHz as shown in Figure The gm of M2 (43.53 ms), M3 (43.56 ms) and M4 (47.55 ms) are decided by considering the radio frequency circuit design tradeoffs and cancellation of the noise of M1 at output. Simulated noise figure plot is shown in Figure 3.8 and report minimum noise figures of 3.17 db. Figure 3.9 shows the circuit simulated power gain of 22.4 db (average) in the frequency range of 2.5 GHz to 4.5 GHz. Figure 3.11 compares simulated and theoretical noise figures which shows a good agreement between both in range from 2.5 GHz to 4.5 GHz. However, simulated noise figure value increases towards higher frequencies due to the noise contribution of circuit and parasitic components that were not considered during NF analysis and are not included in equation (3.6). The proposed circuit is unconditionally stable and stability plot is shown in Figure Third order intercept point (IIP3) is reported in Figure 3.13 which shows a good linearity of -7.5 db. Moreover, in this work an LNA is designed which exploits thermal noise cancellation of its first stage CG transistor (M1). Equation (3.6) is used to get the plot for theoretical noise figure as shown in Figure 3.11, which in turn is compared with the simulated noise figure plot and they are found to be in close agreement near a frequency of 3 GHz. Table 3.1 and 3.2 present aspect ratios and performance comparison of LNA respectively

37 8 7 NF (db) Noise Figure (db) db Frequency (GHz) Figure 3.8: Simulated noise figure plot for proposed LNA with noise cancellation Forward Transmission Gain (db) db S21 (db) Frequency (GHz) Figure 3.9: Simulated power gain plot for proposed LNA with noise cancellation

38 Input Reflection Coefficient (db) Frequency (GHz) S11 (db) Figure 3.10: Simulated input reflection coefficient plot for proposed LNA with noise cancellation Noise Figure (db) NF Simulation NF Theory 3.3 db Frequency (GHz) Figure 3.11: Simulated and theoretical noise figure plots for LNA with noise cancellation

39 Stability Factor (K) Stability Factor (K) Frequency (GHz) Figure 3.12: Simulated stability factor plot for LNA with noise cancellation Pout (dbm) Fundamental Third Order Pin (dbm) Input Referred IP3 = -7.5 dbm Figure 3.13: Simulated IIP3 plot for proposed LNA Output Voltage (db) E+09 1E+10 Frequency (Hz) Figure 3.14: AC analysis of RF adder Vout (db)

40 Vout V1, V2 Voltage (uv) Time (ns) Figure 3.15: Transient analysis of RF adder 325 uv 200 uv Figure 3.16: Layout of the proposed LNA

41 Table 3.1: Aspect ratios and parameter values of proposed circuit Parameter Value Parameter Value Paramter Value (W/L)1 80 µm/ 0.18 µm L nh Vdd 1.8 V (W/L)2, 3, 4, 5, µm/ 0.18 µm L nh Vb1 600 mv (W/L)6, 8, n, p 100 µm/ 0.18 µm L nh Rf 6 K L nh Lo 9.13 nh L nh Performance summary Table 3.2: Performance summary of the noise cancelling LNA Parameter Without Noise Cancellation [21] With Noise Cancellation Pre Layout Post layout Frequency (GHz) 3.1 ~ ~ ~ 4.5 S11 (db) < -10 < -10 < -10 S21 (db) (av.) (max) (av.) (max) NF (db) (av.) (max) IIP3 (dbm) Technology 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS

42 3.6 Conclusion and limitations A CMOS CG LNA in GHz range has been demonstrated in a standard TSMC 0.18 µm CMOSRF technology and analysis of all noise contributing sources is performed. Moreover, a noise cancelling technique is implemented in order to cancel the noise, contributed by major noise source. This results significant reduction of 22.49% in noise figure with the proposed topology when compared to LNA without noise cancelling technique. A peak power gain of 28.4 db and base NF of 3.17 db with good stability and linearity is achieved over the 2 GHz spectrum

43 Chapter 4 Other Work on Low Noise Amplifier Overview: This part of the work focuses on a broadband design of low noise amplifier. Hence, a CMOS UWB LNA is designed with shunt-series inductive peaking and interstage matching. This design includes inductive source degeneration cascode topology with interstage matching network. Additionally a Chebyshev band pass filter at the input and shunt-series inductive peaking at the output are placed which provide better impedance matching and improved power gain. 4.1 Introduction Inductive source degeneration with cascode transistor LNA is very popular architecture for CMOS RF integrated circuit and microwave circuit design [30]. In this type of LNA architecture, cascode transistor reduces the miller effect and improves reverse isolation. As in LNA design, virtual gate drain capacitance of first stage i.e. miller capacitance [CM = Cgd (1+Av1)] limits the bandwidth at high frequency to 1/RCM where CM gets amplified by its own gain (Av1). Therefore cascode transistor protects from direct shorting of input and output through this capacitance. Moreover, an inductor can be used for further isolation between two stages [31]. Inter-stage inductor causes reduction of input impedance of second stage, resulting in more current pump towards output [32]. This work implement a design of UWB LNA which include interstage matching network to carry forward desired signal with the stoppage of undesired signal. And, also includes a Chebyshev band pass filter for input matching and shunt-series inductive peaking network at the output to boost the desired signal power. Simulation work is done with TSMC 0.18 µm CMOS technology using Cadence SpectreRF tool. 4.2 A CMOS LNA with Peaking and Interstage Matching A simplified schematic design of the UWB LNA is shown in Figure 4.1. All components in the figure are integrated on-chip with CMOS technology. A second order Chebyshev band pass filter is used in this design for better input matching in the desired range. Inductor LG2 and capacitor Cg are connected to couple the output of the first stage to the second stage. The inductance LM is large enough in the frequency range of interest to block the path from M1 to M2. These passive networks in between two stages are designed in such a way that desired signal can carry forward

44 towards output and undesired signal should bypass to ground. Inductors at the output show shuntseries peaking and compensate the gain roll-off of the amplifier which improves the linearity as well. A buffer stage is also added at the output. R LD L LD L P V b2 M 2 M 3 V out C g I m C pad L G2 L M C by V in L 1 C 1 L g M 1 Z O C pad C 2 L 2 C p V S L S V b1 Figure 4.1: Simplified schematic of UWB LNA Input impedance matching stage Figure 4.2 shows the equivalent circuit for input impedance matching network. The inductors and capacitors network form a second order Chebyshev filter whose pass band is 3.1 GHz to 10.6 GHz. The input impedance of matching network is given by equation (4.1). ' Z in1 = Z in1 W(s) = ω TL s W(s) (4.1) Where W(s) is the transfer function of the filter which is equal to Zin1/Z`in1. W(s) is approximately unity in the pass band and tends to zero out of band. The input impedance of the amplifier is equal to ωtls in the pass band and it is very high out of band. Zin is input impedance of amplifier without extra LC network at the input which follows relation Zin = ωtls = Zo under resonance condition ωo = 1 / [(Lg+LS)Ct] ½. Here Lg and LS are inductors connected at the gate and source of M1, Ct is total capacitance connected between gate and source terminals of M1; where Ct is equal to Cgs1+Cp. Unity current gain frequency ωt is equal to gm/cgs1 for M1. From equation (4.1), matching of input impedance equal to Zo is obtained for entire band of interest. Assume that the ripple in the pass band is ρ and then the input reflection coefficient can be expressed as (1-1/ρ). To achieve the reflection coefficient less than -10 db, equation yields ρ < 0.5 db. We can

45 derive the component values for this second order Chebyshev filter using a standard filter formulas tool. L 1 L g L S C t =C p +C gs1 Z O C 1 C 2 L 2 W T *L S C gd1 Figure 4.2: Equivalent circuit of input impedance matching network Interstage matching Figure 4.3 and Figure 4.4 are small signal equivalent circuits for interstage impedance calculation. Inductor LG2 and capacitor Cg are connected between drain of M1 and gate of M2 which couples output of first stage to input of second stage. The resonance circuit composed of LG2, Cg, Cgs2 and bypass capacitor (Cby) present narrow band characteristics. Therefore second stage gain is maximized at around resonance frequency which may affect the linearity of overall gain and bandwidth. Z O Zin1' LC-Network Filter Tr.Func. = W(s) Cgs V gs g m1 Vgs L S r ds1 Zin1 Zin2 Zo1 L M C g L G2 C by 1/g m2 C gs2 Figure 4.3: Equivalent circuit of UWB LNA with matching networks I x L M I x -I 1 Vx I 1 C g C by 1/g m2 C gs2 L G2 Zin2 Figure 4.4: Equivalent circuit of input impedance of second stage

46 Inductor LM value is fixed in such a way that it should provide a high impedance path for desired signal from first stage and low impedance path for undesired signal. Resonance circuit formed by LM and Cby resonates outside the frequency of interest. LG2 and Cg values can be selected independent of LM when LM exceeds a certain value on which resonance started outside the frequency of interest. Inductors LP, LLD and resistor RLD form shunt series peaking circuit which is responsible to enhance the bandwidth and linearity of LNA. Charging of load capacitance speeds up due to LLD and initially transistor has to drive its own output capacitance for some time because LLD and LP delay the current [33]. Expression for output impedance (Zo1) of first stage looking at the drain of M1 is given in equation (4.2) [32]. Z o1 = 2r ds1 + j ω o Z ω o + ω 2 o L T ω s (4.2) T Where resistive part (2r ds1 + ω 2 o L s ) is very high and reactive part is small when Cgd is ω T neglected. For the calculation of second stage input impedance Zin2, looking away from the drain of M1 as shown in Figure 4.4. Let Vx, Ix be voltage and current at input of second stage and Ix is divided into branches as I1 and (Ix I1). Voltage across Cg and LG2 is written in equation (4.3). V x = I 1 ( 1 sc g +sl G2 ) (4.3) Voltage across LM, Cby, 1/gm2 and Cgs2 is written in equation (4.4). A simplified expression for Zin2 is given in equation (4.5) which can be deduced by further solving equations (4.3 and 4.4). V x = (I x -I 1 ) (sl M ) (4.4) sc by g m2 sc gs2 Z in2 = 1 [y -1 + ( 1-1 +sl sc G2 ) ] g (4.5) Where ωt2 = gm2 / Cgs2 and y = (sl M + 1 sc by 1 g m2 1 ) sc gs2 In equation (4.5), Zin2 has only resistive value which can be calculated by substituting a proper value of ωt2. The approximate value of Zin2 is less than 1/gm2 which causes more current pumping into the second stage, thus improving forward transmission performance

47 4.2.3 Shunt-series inductive peaking and gain stage The total gain of the proposed LNA is equal to the product of the gain of the first and second stages. Compared with the gm of the transistor, the effective transconductance (Gm) is more suitable parameter to estimate the gain performance of the radio frequency amplifier. The parameter Gm is defined as the amplitude of the output current (iout) flowing into the load, divided by the input voltage (Vin) of the amplifier. The Gm is proportional to the gm of the input transistor and the proportional coefficient depends on the input matching network. Gm of the second stage is gm2 straightforwardly. From Figure 4.3, the gate-source voltage (Vgs) of M1 is equal to VinW(s) / sctωtls. Therefore Gm of the first stage (Gm1) can be expressed as given in equation (4.6). G m1 = i m1 V in = g m1 W(s) sc t ω T L S = g m1 W(s) sc t R s (4.6) The equivalent circuits of the loads of first and second stages are shown in Figure 4.5 and Figure 4.6. From Figure 4.5, the load impedance of first stage (ZL1) is written in equations ( ). Z L1 = V out i m1 (4.7) =[ (sl G2 + 1 sc g + 1 sc gs2 ) {(sl M +R M )+ 1 sc by }] 1 sc par (4.8) R M +sl M = (R M +sl M )+(sl G ) 1 (4.9) sc gs2 sc g sc gs2 where RM is the parasitic resistor of inductor LM and Cpar is the total parasitic capacitance at the drain of transistor M1. I m1 L G2 C g C par L M C gs2 I m2 L LD R LD C by C X R LD C L V out Figure 4.5: Load of first stage Figure 4.6: Load of second stage

48 Practically, the capacitance Cby in Figure 4.1 is chosen to be large enough so that the source of the transistor M2 can be seen as AC ground. If LM and RM exhibit higher impedance than LG2, Cg and Cgs2 in series, the resonance frequency is mainly determined by the LG2 and Cg. Note that the resonance presents a narrow band characteristic. Therefore, the gain is maximized near the resonant frequency which is designed to enhance the gain at the middle of the desired band. The staggered-compensation series peaking technique as in [34] is adopted for reference. This work implements shunt-series peaking in the second stage to compensate for the high frequency gain roll-off. The equivalent circuit of the load of second stage is shown in Figure 4.6. The load impedance of the second stage can be written as in equation (4.10). R LD Z L2 = V out = i m2 1+sR LD (C x +C L )+s 2 L LD C L +s 3 (4.10) L LD C x C L R LD Where Cx is the total parasitic capacitor at the drain of the transistor M2, and CL is the total capacitor at the input of the buffer. LLD and LP resonate with Cx, thus the response shows a peak at resonance frequency which compensates the gain roll-off of the amplifier at high frequency. Combining the gain versus frequency characteristic of the two stages, the gain flatness can be achieved over the entire bandwidth Noise Analysis In the proposed LNA, the noise of the second stage is reduced by the gain of the former stage and the overall noise performance of LNA is dominated by the first stage [35]. The two main noise contributors of the first stage are the losses of the input matching network and the transistor M1. The expression for noise factor F(w) of the amplifier is written in equation (4.11) and the detail derivation can be seen in [12]. Where F(w)=1+ P(w)γ G m R s α (4.11) P(w)= (ραχ)2 (1- c 2 ) 1+2 c ραχ+(ραχ) 2 +(wc tr s ) 2 (1+ 2 c ραχ+(ραχ) 2 ) (4.12) χ= δ 5γ ; ρ= C gs C t ; α= g m g d0 (4.13) In equation (4.12), c is correlation coefficient between the gate noise and the drain noise, δ and γ are the excess noise parameters and α accounts for short channel effects. For CMOS devices, δ

49 4, γ 2, α 0.85 and c 0.4j [33]. Equation (4.11) shows that increasing the transconductance improves the noise performance while keeping all other parameters constant. Simulation reveals that, for a given current budget there is a value of M1 s width that yields the best noise figure over the bandwidth. For further analysis, a noise model of the input matching network is shown in Figure 4.7. e nrl1 L 1 C 1 L g +L S R LgLs e nrlgls Z O e ns R L1 C 2 L 2 R L2 e nrl2 C t e nin Z O =W T *L S Figure 4.7: Noise model of the input matching network The L1 and C1 are components of the Chebyshev filter. RL1 is the parasitic resistor of L1, RL2 and RLgLs are the parasitic resister of L2 and Lg + LS. Voltage source enrl1, enrl2 and enrlgls represent the thermal noise generated by resistors RL1, RL2 and RLgLs. Transfer Functions for these noise sources are written in equations ( ). TF RL1 = e nin W(s) (4.14) = e nrl1 [W(s)+1]sC t R s TF RL2 = e ( 1 ) Z nin sc gs Z 1 = 2 1 e nrl2 Z 2 + ( 1 ) Z sc gs Z Z 1 gs (sc t ) 2 TF RL2 = e nin 1 1 = e n R LgLs Z gs + ( 1 ) Z sc 1 Z (sc 2 t ) 2 (4.15) (4.16) Where Z 2 =sl 2 +R L2 ; Z gs =s(l g +L s )+R LgLs + 1 (sc t ) +Z o; Z 1 =sl 1 +R L1 + 1 (sc 1 ) +Z o Where W(s) is filter transfer function and Z1= Zo for the second order Chebyshev filter. The noise contribution from the passive devices of the third order filter is much larger than that of their second order counterpart, so a second order Chebyshev filter is more suitable to shoot for low noise

50 Noise Figure (db) 4.3 Simulation Results: This section include simulation results of UWB LNA. Noise figure in Figure 4.8 shows an excellent performance of 3.42 db to 6.85 db in frequency range of 3.1 GHz to 10.6 GHz. As shown in Figure 4.10, the power gain ranges from db to db over the entire bandwidth of interest. This result also shows a gain roll-off at higher frequencies which is due to the shuntseries inductive peaking. Figure 4.9 presents input reflection coefficient, in which, well matched S11 over the entire range of 3.1 GHz to 10.6 GHz demonstrate a successful design of input matching network. Table 4.1 summarizes the performance of designed UWB LNA. Layout of the UWB LNA is shown in Figure 3.11 which occupies 0.9 mm x 1 mm area. Simulations are done with TSMC 0.18 µm CMOS technology Frequency (GHz) Figure 4.8: Simulated noise figures of UWB LNA

51 S21(dB) S11(dB) Frequency (GHz) Figure 4.9: Simulated input reflection coefficients Frequency (GHz) Figure 4.10: Simulated forward transmission gains Figure 4.11: Layout of the UWB LNA

52 Parameters Table 4.1: Performance summary of the UWB LNA Freq (GHz) Gain (db) NF (db) S11 (db) Power (mw) Values < Conclusion and limitations The design and simulations of an ultra-wideband low noise amplifier for 3.1 GHz to 10.6 GHz is presented. The design employs Chebyshev band pass filter for input matching and interstage matching network to carry forward the desired signal with bypassing the undesired signal. Also a shunt-series inductive peaking network is used to compensate the gain roll-off at higher frequencies. The UWB LNA provides peak power gain db and minimum noise figure 4.4 db within the bandwidth of 3.1 GHz to 10.6 GHz. This LNA also demonstrate a good input matching i.e. well below -10 db in entire bandwidth. LNA consumes 11.2 mw with 1.8 V supply and occupies 1 mm x 0.9 mm of layout area

53 Chapter 5 Layout Technique Overview: This chapter highlights major layout techniques which was considered during the implementation of low noise amplifier layout design. It is observed that the proper layout technique can significantly change the post layout simulation results. Following are some important and noticeable facts which are observed during my layout design experience and should be considered by layout designers for effective layout outcome. Layout examples are kept at the end of this chapter. In initial floor planning of layout, large size components i.e. inductors are placed properly because later it is most difficult to change place of such components. While fixing inductors space it is necessary to keep in mind that power supply connection wires should be thick and smaller in length. In this layout, power supply connection to inductors are done with more thicker top layer metal and inductors are placed in such a way that its suppl y terminals are near to supply pad which require lesser length of supply wire. This way parasitic resistance caused by high current density wire can be reduced significantly. Six metal layers are used for routing which is planned in the following ways: Metal-6 for Vdd or supply Metal-5 for Gnd Metal-4 for RF Signal Metal-3 for RF Signal Metal-2 for Gnd Metal-1 for Vdd or Supply Poly should never be used for routing because it causes large resistance which can influence overall result performance as it is shown in Figure 5.1 results large noise figure of 48dB. There should be metal connection immediately after poly while routing gate terminal of the transistors as shown in Figure 5.2. Vias resistance can be reduced if multiple parallel vias are used instead of single via. Improvement in result can be seen in Figure 5.4. Isolate the large transistors with guard ring to avoid noise coupling with unwanted circuitry and are placed around the transistor as shown in Figure 5.2. This can immobilize the substrate/bulk/well potential when it is connected to ground. For n-channel, transistor guard

54 ring made of p-active (p+) material is used. For p-channel, transistor guard ring made of n- active (n+) layer is used. These active materials are connected to metal-1 through multiple vias, which is routed until ground. Transistor fingering is done to avoid large gate parasitic as shown in Figure 5.1 and Figure 5.2. During place and route it is observed that if we keep most dominating noise source i.e. transistor M1 far from input terminal, connecting wire parasitic resistance adds significant noise to overall circuit performance. Hence placing of M1 transistor near to input terminal is better. Improvement in result can be seen in Figure 5.5. A resistance connected to transistor M1can add significant parasitic resistance hence it should be placed near to transistor as shown in Figure 5.5. The width of the supply lines is based on the resistivity of the metal used for routing the supply. In this layout, supply wires are connected by top metal layer as shown in Figure 5.6. The convention in IC design for resistance (or parasitic resistance) calculation is to characterize each conductor layer in terms of resistance per square. One square is defined as the condition when the length of the conductor equals the width. The formula for calculating the resistance of a conductor is R = ρl/w, where R is the resistivity of the layer measured in Ω/, L is the length, and W is the width of the conductor. ρ is a material property and characteristic of the manufacturing process which cannot be controlled by the layout designer. From this formula it is apparent that there are two ways to minimize the resistance of a wire. (i). Reduce the length of the wire. (ii). Increase the width of the wire. Above is important for good design practices which can reduce resistance for various layout design styles. A transistor in CMOS is made of source (active), gate (poly-silicon), and drain (active) regions, but to make it work we need signals connected to all three terminals. Thus, contacts to the source and drain are important to consider. From layout experiments, it is observed and is interesting to note that the active resistance is dominant and is 1,000 times more resistive than metal-1 and 10 times more resistive than a metal-1 contact. These numbers give us a good starting point for minimizing the overall resistance from the two metal lines i.e. try to minimize the active resistance. The contacts are three-dimensional columns of metal or poly, and they add to the resistance of paths. The number of contacts in any connection is important to consider, because for each contact the resistance is reduced by introducing another parallel current path from the conductor. This is especially important for high current carrying signals such as power supplies. Transistor with more number of contacts can be consider as lowest resistance

55 configuration of transistor and achieves highest reliability. Performance and reliability in RF circuits such as low noise amplifier is important, so to make use of fully contacted transistor is preferable. In LNA layout design, fully contacted transistor model provided by TSMC is used. Selection of resistance depends on the layer used in it. An appropriate choice of layers possible by considering the following factors: Resistivity of the various layers Variation in resistivity under different temperature conditions Variation in layer area under different process conditions Area of resistor for chosen layer In most cases gate poly is chosen as the resistor material, as its resistance is relatively high, the resistivity and width are tightly controlled, and the resulting area is reasonable. In this layout typical poly resistors are used. Parasitic in it arises due to the effect of contact resistance. These are more area efficient solutions, as they sometimes have to fit in the areas of transistors without using too much space. The disadvantage of such resistors is that the resistance is not easily calculated because of the corners in the poly layer. As a best approximation, we can use the centerline of the poly divided by the width to calculate the total resistance of the line. In RF layout designs, we may have to shield the resistor fingers from itself to avoid coupling. In LNA layout such resistors are used. Capacitance affects several different characteristics of a design. When two equivalent designs are compared, the design with the higher capacitance will have a resulting increase in signal delay, power consumption, coupling effect to and from neighboring structures. A review of the definition of capacitance gives an understanding how good design practices reduce capacitance for various layout design styles. The general formula for the calculation of the capacitance of a conductor is C = ɛa/d, where A is the surface area of the specific conductor layer, d is the physical distance between the conductor layers, and ɛ is a constant representing the characteristics of the insulating layer between the conductor layers. From this formula it is apparent that there are two ways to minimize the capacitance of a signal: (1). Reduce the area of the capacitor, this means reducing the overlapping regions of the two plates or wires. (2). Increase the distance between the plates of the capacitor. An array of capacitors is good way of layout instead of big size single capacitor as shown in Figure 5.3. Following are figures demonstrating different layout examples and response results:

56 Figure 5.1: Transistor fingering and poly routing with its response Figure 5.2: Metal connection immediately after poly with its response Figure 5.3: Array of capacitors connection

57 Figure 5.4: Single and multiple parallel vias with its response Figure 5.5: Placing of M1 transistor near to input terminal

58 Figure 5.6: Supply wires routed with top metal layer Figure 5.7: Wide wires connected to input transistor