Designing of Low Power RF-Receiver Front-end with CMOS Technology

Transcription

1 Sareh Salari Shahrbabaki Designing of Low Power RF-Receiver Front-end with CMOS Technology School of Electrical Engineering Thesis submitted for examination for the degree of Master of Science in Technology. Espoo October 2, 2017 Thesis supervisor: Prof. Kari Halonen Thesis instructor: D.Sc. Shailesh Singh Chouhan A Aalto University School of Electrical Engineering

2 aalto university school of electrical engineering abstract of the master s thesis Author: Sareh Salari Shahrbabaki Title: Designing of Low Power RF-Receiver Front-end with CMOS Technology Date: October 2, 2017 Language: English Number of pages:10+46 Department of Electronics and Nanoengineering Professorship: Microelectronics circuit design Supervisor: Prof. Kari Halonen Code: ELEC3037 Instructor: D.Sc. Shailesh Singh Chouhan This thesis studies how to design ultra low power radio-receiver front-end circuit consisting of a low-noise CMOS amplifier and mixer for low power Bluetooth applications. This system is designed in 65-nm CMOS technology with voltage source of 1.2 V, and it operates at 2.4 GHz. This research project includes the design of radio frequency integrated circuit with CMOS technology using CAD software for circuit design, layout design, pre and post-layout simulations. Firstly, brief study about both Low noise amplifier (LNA) and mixer has been done, and then the design structure such as, input matching network of LNA, noise of system, gain and linearity have been discussed. Later, next section reports simulation results of LNA, mixer and eventually their combination. Furthermore, the effect of packaging and non-ideal on-chip circuit performance has been considered and shown in comparison tables for more clarity. Finally, after the layout design, the obtained results of both post-layout and pre-layout simulations are compared and shown the stability of the design with parasitics consideration. Keywords: Ultra low power front-end receiver, Low noise CMOS amplifier, Gilbert mixer, Bluetooth, Radio frequency receiver

3 iii Acknowledgments First and foremost, I would like to express my deepest thanks and gratitude to my kind supervisor Professor Kari Halonen who has supported me throughout my thesis work with his patience, motivation and immense knowledge whilst allowing me the room to work in my own way. I am deeply thankful to my instructor Shailesh Chouhan for his friendly help, encouragement and support from the preliminary to the concluding level of this work. I would like to express my gratitude to Aalto university and Department of Electronics and Nanoengineering for providing such friendly, productive and modern environment. I would like to thank all of my colleagues for their kindness and creating friendly environment. I owe a very important debt to my parents and siblings who have always supported me in my life, and encouraged me to follow my dreams. Last but not least, I would like to show my greatest appreciation to my beloved husband Sajjad Mirmoosa who has always believed and helped me, without him I was not the person who I am now. I would like to dedicate this work to him who is my best friend. Sareh Salari Shahrbabaki Otaniemi,

4 iv Contents Abstract Acknowledgments Contents Abbreviations and Acronyms Symbols List of Figures and Tables ii iii iv vi vii ix 1 Introduction 1 2 Low Noise Amplifier (LNA) Common gate Inductively degenerated common-source LNA Input impedance Gain Linearity Cascode stage Common source with resistive feedback Mixer Down-conversion mixers Single-balanced and double-balanced mixers Passive mixers Active down-conversion mixers Mixer input stage Conversion gain Mixer noise Linearity Design Description LNA design procedure Stability of LNA Simulation result Differential cascode LNA Mixer design procedure Physical Layout and Post-Layout Simulation Results Layout design Post-layout simulation results Conclusion and Future Work 41

5 References 42 v

6 vi Abbreviations and Acronyms AC CS CG CMOS DC FET GHz IC IF IIP2 IIP3 IP2 IP3 LC LO LNA MHz mm NF RF Alternating Current Common Source Common Gate Complementary Metal Oxide Semiconductor Direct Current Field Effect Transistor Giga Hertz Integrated Circuit Intermediate Frequency Input Reffered Second-Order Intercept Point Input Reffered Third-Order Intercept Point Input Reffered Second-Order Intercept Point Input Reffered Third-Order Intercept Point Inductor-Capacitor Local Oscillator Low Noise Amplifier Mega Hertz Millimetre Noise Figure Radio Frequency

7 vii Symbols A A v BW 3dB C L C c C gd C gs C bs C in C par F f f LO f RF f S11 = 10dB γ g m g m,rf I bias I D L L L d L S L g M n N dsb NF P dc Q R R in R S R B R L S 11 V DD V DS V in V RF V IF V th W Gain Voltage gain -3dB bandwidth Load capacitance Coupling capacity Gate-drain capacitance Gate-source capacitance Bulk-source capacitance Input capacitance Parasitic capacitance Noise factor Frequency Frequency local oscillator Frequency radio frequency Frequency where S 11 equals -10 db Process-dependent noise factor Transconductance Transconductance RF stage Bias current Drain current Channel length Inductor Drain Inductor Source Inductor Gate Inductor MOS transistor, n=1,2,3,... double-sideband noise factor Noise figure Dc power Quality factor Resistor Equivalent Resistor Source Resistor Bias Resistor Load Resistor Input matching coefficient or reflection coefficient Supply voltage Drain-source voltage input voltage RF voltage IF voltage threshold voltage Channel width

8 viii Z Z in α ω ω 0 κ Impedance Input Impedance Noise parameter Angular frequency Center angular frequency Ratio of the transistor substrate transconductance

9 ix List of Figures and Tables List of Figures 1 Front-end receiver Common-gate LNA (a) Inductive degenerated common-source LNA (b) equivalent circuit neglecting C gd and C sb Inductively degenerated common source LNA with cascode stage (a) Common-source with resistive feedback LNA (b) simplified circuit [22] Simple mixer model Single-balanced passive mixer Double-balanced passive mixer single-balanced active mixer Double-balanced active mixer (Gilbert mixer) Transconductance stage of mixer: (a) grounded CS stage and (b) differential pair with a tail current source Loss of RF current to ground through C p Low noise amplifier with bias system Input impedance of inductively-degenerated CS stage Input stage of LNA: (a) equivalent circuit for inclusion of pad capacitance and (b) input stage with pad Input stage without pad Pad equivalent circuit in our design Inductively-degenerated cascode common-source LNA Equivalent circuit of non-ideal inductor Equivalent circuit of non-ideal inductor Properties of Single-ended amplifier with pad inclusion Comparison of single-ended amplifiers with pad inclusion and without pad Differential LNA which consists of two single-ended LNA that introduced in the previous section Properties of differential amplifier with pad inclusion Differential LNA connected to the gilbert mixer Example of common-centroid array Modeled R B layout Mixer layout Differential LNA connected to the Gilbert mixer layout Comparison of pre-layout simulation and post-layout simulation results of differntial LNA Comparison of pre-layout simulation and post-layout simulation of whole system Variations in Monte Carlo simulation

10 x List of Tables 1 Component values of LNA in both conditions when the pad has considered and has not Obtained properties of single-ended LNA Result comparison of various LNA design Table of Gilbert mixer value when the pad has been considered and has not Obtained results from simulation of Gilbert mixer Table of Gilbert mixer value when the pad has been considered and has not Achieved conversion gain conversion in pre-layout and post-layout simulation

11 1 1 Introduction Low power, low-voltage and highly integrated circuits are always the most important subjects for integrated circuit design. Especially, in sensor design due to the crucial need for minimal size and low power circuits. These properties result in remarkable development in sensors applications such as personal health care, home automation and short distance devices (Bluetooth applications). Therefore, sensor industries require minimized transceiver power consumption. Since the wireless communication system is very lossy, the received signal from the antenna has very weak strength. Therefore, low noise amplifier (LNA) has to be used after and close to the antenna to amplify the signal for appropriate operation. Furthermore, in order to translate the amplified signal to the desire lower center frequency to permit channel-selection filtering, usage of another block in receiver topology is necessary which is a mixer. In fact, the mixer multiplies the signal to another signal that generated by a local oscillator (LO) and since the multiplication in the time domain corresponding to the convolution in the frequency domain, thus the frequency shift is performed by ±ω LO. Finally, by filtering we would have amplified signal at the desired frequency. Figure 1 shows the schematic front-end receiver. Figure 1: Front-end receiver. A front-end receiver should operate at a low supply voltage with a small battery or environment energy. In the last few years, plenty of low power receiver implementations have been reported [1 4]. However, their power dissipation is still too high. Therefore, in this work, we tried to minimize the power dissipation as much as possible. This work is a part of low-power transceiver design for short distance devices. It presents the design of a low power LNA+ mixer which are the main parts of the front-end receiver. This receiver is designed for Bluetooth applications, thus the performance frequency is at 2.4 GHz. The conventional architecture of receiver generally integrated discrete and coupled together with inter-stage matching network, balun or filters. These intermediate stages lead to additional power consumption and unwanted parasitics due to the complexity of the system. This work reports ultra-low power fully differential LNA connected to an active downconversion mixer. Active mixers have a capacitive input impedance, therefore the

12 only issue is to re-evaluate the LC load of LNA. The integrated architecture is designed, simulated and verified in a 65-nm CMOS technology. The thesis is organized as follows. Section 2 and 3 introduce LNA and mixer respectively and describe the most common LNA and mixer topologies. Section 4 explains the design procedure and important factors which should be considered during the design. Moreover, section 4 shows the simulation results and performance comparison with other existing systems. Section 5 demonstrates the layout design of the integrated system, followed by post-layout simulation results in contrast with pre-layout simulation. At the end, this thesis is concluded and briefly discussed future work in section 6. 2 Low Noise Amplifier (LNA) Low Noise Amplifier (LNA) which is usually the first amplifying stage of RF receiver is the most challenging part. Based on Friis equation the LNA sets the minimum noise figure of the receiver [5]. The Friis equation is used to calculate the total noise figure of a successive system, each stage with its noise figure and gain. The total noise figure is expressed as Equation 1: 2 F total = F 1 + F 2 1 G 1 + F 3 1 G 1 G 2 + F 4 1 G 1 G F n 1 G 1 G 2...G n, (1) where the F i and G i are the noise figure and gain of the i th stage respectively. As a result of this equation, the total noise of a receiver is generated dominated by the first stage of the system which is the LNA. The noise of subsequent stages degrade by LNA gain as Equation 2 shows. F receiver = F LNA + F rest 1 G LNA, (2) in which F rest is the noise of next stages. Thus, the LNA should provide enough gain in order to overcome the noise of the next stages, while it may threaten the sensitivity of receiver. In addition to the noise figure and gain, enough broad bandwidth is an important issue. To cover the whole reception band with some design margin, but narrow enough to filter unwanted interferers. In order to fulfill the filtering role of LNA a good input impedance matching with source input is also required. Moreover, linearity performance of total front-end or receiver typically is dependent on the linearity of this stage (LNA). Linearity like bandwidth should be sufficient to tolerate large blockers and not to produce undesired inter-modulation tones in the considered band. Therefore, to design a proper LNA there are several conditions to be satisfied. Whereas, fulfillment of all requirements together because of simultaneous parameter

13 optimization is difficult, thus designers have to find compromise according to their own desires. A large number of various LNA topologies is presented in Ref. [6]. Here, we just present and compare the most useful structures the common gate and common source LNAs. 2.1 Common gate The common gate (CG) LNA is shown in Figure 2.1 and some details related to the CG LNA performance are discussed here in this section. The CG LNA is wellknown for being robust and also having a wide frequency range which makes it suitable topology for ultra wide band applications. This topology provides resistive input without the need of using an inductor. The input impedance of CG amplifier is equal to R in = 1 G m, where G m is the transistor transconductance of the transistor, if the channel length modulation and body effect are neglected. Vdd 3 C Vout R Rs C Vin Iss 100mA Vss Figure 2: Common-gate LNA. The input impedance of low noise amplifier should be matched with source resistance R S that is in the majority of cases 50 Ω. Impedance matching has to be done for transferring the maximum power from input to the amplifier. Therefore, dimensions of the amplifier and bias current should be chosen so as G m = 1 R S or G m =20 ms, which results in high power consumption or large W ratio. Thus, we L have some limitations in order to choose the design parameters. The CG stage does not suffer from the Miller effect and hence a sufficient reverse isolation can be achieved with a single transistor stage. Therefore, the input matching network and load can be designed separately. For instance in Refs. [7 10] shunt feedback resistor

14 4 used to adjust input impedance. In other words, shunt resistance improves the input matching, while the size of the transistor or its power consumption is not large. One of the main limitations of CG amplifier is the noise performance. The minimum noise figure is given by, F min,cg = 1 + γ 1 α (κ + 1) 1 = 1 + γ 2 g m R S α. (3) According to Equation 3, where γ is the channel thermal noise coefficient and it is 2/3 for long channel devices and considerably larger for short channel devices. κ is the ratio of the transistor substrate transconductance g mb and g m, R S is the source resistance and α for the long channel devices is equal to gm g ds0. According to Equation 3, the noise performance of the common-gate stage is independent of the operation frequency. Thus, CG can be a good option for high frequencies [11]. α is ideally one and it is smaller for short channel devices. Theoretically, achievable noise figure (NF) is around 3 db or larger [12]. Therefore, the NF limits the usage of commongate LNA. However, according to Ref. [13], NF can be lowered by imperfect input matching as F min,cg = 1 + γ 1 + S 11 1 S 11, (4) where α is neglected and S 11 is the return loss coefficient (reflection coefficient). In addition, if the load of LNA is resistive we have to take into account contribution of its noise in the noise figure as given by Equation 5 F = 1 + ( γ α + (1 + g mr S ) 2 1 ) = 1 + γ g m R L g m R S α + 4R S. (5) R L Therefore, as it is explained explicitly in Ref. [11] the resistive load has significant role in overall NF. There is a possibility to improve the noise performance by using differential CG LNA. In this method, gates are driven by the opposite polarity input which halves the required g m and reduces the minimum noise as expressed in Equation 6 [14] F min,cg = 1 + γ 2α. (6) 2.2 Inductively degenerated common-source LNA The inductively degenerated common-source (IDCS) amplifier depicted in Figure 3(a) is one of the most popular CMOS LNA topologies. In Refs. [15 19] this type of LNA has been used and has been explained with details. This topology has very

15 good NF and it provides both current and voltage gain which results in reducing the noise of next stages [16]. According to the equivalent circuit of this amplifier which has been shown in Figure 3(b), the transistor M 1 is simply replaced with the small signal model having only gate-source capacitance C gs and transconductance g m. In order to improve and optimize noise performance of this structure another capacitor (C d ) can be connected parallelly with the C gs of the input device, as indicated in Ref. [20, 21]. 5 Vdd R C Vout R Rs C Lg n cd Ls (a) (b) Figure 3: (a) Inductive degenerated common-source LNA (b) equivalent circuit neglecting C gd and C sb Input impedance Input impedance of IDCS low noise amplifier can be expressed as below [22] Z in = jωl g + jωl s j ωc gs + g ml s C gs. (7) The resistive term of Equation 7 is directly proportional to the source inductor value. Therefore, this amplifier can provide the specified input impedance without using a physical resistor which causes noise to the amplifier. Reactance is almost noiseless, thus it does not generate thermal noise. However, the series resistance of inductors L g and L s would have a slight effect on NF. For having 50 Ω input impedance, the real part ( gmls C gs ) should be equal to 50 Ω and imaginary part should be zero at the frequency of interest, thus it results in R s = g ml s C GS, ω 0 2 = 1 (L s + L g )C GS, (8)

16 6 where C GS is the sum of C gs and C d. If the size of the transistor is small, using C d is a useful way to realize input matching network. In other words, L s, L g and C d + C gs can be adjusted simultaneously to obtain the best matching performance. Typically, L g is realized as wire-bond inductance with high quality factor (Q) and L s has low value with smaller Q which is implemented as an on-chip spiral inductor. The effect of the series resistance of L s can be lowered by using bond-wire [23, 24] Gain Voltage gain is defined as a ratio of output and input voltages as follows A v = V out V in, (9) The output voltage at the load impedance (Z L ) is V out = I out Z L, where I out is the output current of the input stage, thus the voltage gain can be written as A v = V out V in = I outz L V in = g m,eff Z L, (10) where the g m,eff is the effective transconductance of the input stage. The g m,eff of common source LNA is evaluated as g m,eff = I out V in = g mv gs V in = g mi in sc gs V in = g m sc gs Z in, (11) in which g m is the transconductance of transistor and C gs, is the gate-source capacitance of the transistor. Moreover, Z in is the input impedance that is presented in Equation 7. Therefore, according to the calculation in Ref. [13], at resonance frequency the g m,eff is independent of g m of the input stage transistor, although g m has effect on the resistive part of the input impedance as given in Equation 8. Additionally, g m,eff can be written as g m,eff = I out V in = g mv gs V in = g m Q in, (12) where Q in is the voltage gain between the input of the matching network and the gate-source voltage of the input transistor. By increasing this gain we can decrease the g m value which leads to a smaller input transistor and then a smaller C gs. In this situation, the matching network becomes sensitive to the parasitic capacitances at the input matching circuits. Therefore, the use of inductor at the source of CS is practically effectless, when the input transistor is very small Linearity Linearity is an important factor which shows the stable performance of the circuit. The most commonly used receiver linearity test is 1-dB compression point and thirdorder intercept point (IP3). These concepts are clearly explained in Refs. [13,22,25].

17 Inductive degeneration common source amplifier has linear performance. Inductive degeneration induces negative feedback at input transistor s source node. Since negative feedback reduces the distortion, thus causes more linear performance. This amplifier provides even more linear performance than the resistive degeneration with the same bias current Cascode stage Common source amplifiers often have a cascode stage as shown in Figure We can utilize the advantages of this stage in our design. For instance, a cascode transistor has a smaller input impedance than the load impedance. Thus, the Miller effect of the input stage is reduced, which improves the LNA stability. 7 Vdd Z C Vout M2 R Rs C Lg M1 Vin Ls Figure 4: Inductively degenerated common source LNA with cascode stage. The noise contribution of a cascode stage to the overall noise of the LNA is small but it is not negligible. At high frequencies, the impedance looking into the drain of M 1 is low [16]. The noise contribution of this stage would even decrease by minimizing the parasitic capacitances between input and cascode transistors. Several methods for minimizing the parasitic effects have been presented in Refs. [26 29]. For the load of cascode we use the LC resonator tuned at the carrier frequency f 0. Therefore, at resonance the tank impedance is large which results in a narrowband and large gain. The loss is minimized by having a large inductor value with a high Q-value and a small capacitor. The supply voltage reduction has the price of larger layout due to the extra inductor. The inductor and capacitor values of the resonator are determined by considering the values of parasitic capacitors of the transistor M 2 and carrier frequency similar to the method as shown in Equation 8.

18 Common source with resistive feedback The source inductor in a common source LNA limits the achievable bandwidth. If we remove the source inductor, we would need another input matching network. Using the resistive input termination due to increasing noise is not a good option. However, the LNA matching network can be realized by using resistive feedback as shown in Figure 5(a). M 2 acts as a current source and R F senses the output voltage and returns current to the input. (a) (b) Figure 5: (a) Common-source with resistive feedback LNA (b) simplified circuit [22]. Since R F is in series with the current source (M 2 ) and M 1 is seen as diode connected device, thus the g m1 = 1 R in. If the input resistance is considered equal to the R s, then g m1 = 1 R s. The gain of this topology according to Figure 5(b) is evaluated as A v = 1 R F R s. (13) Practically, the R F is much larger than R s, therefore the voltage gain is approximately A v R F R s. (14) This circuit is independent of supply voltage effect because the R F does not carry bias current, while this LNA has relatively large NF based on the Equation is given by 15 NF 1 + ( 4R s R F + γ + γg m2 R s ). (15) For γ 1, the NF is larger than 3 db even if the second term is less than 1 [22]. Therefore, this topology is not a good choice in order to minimize the noise figure.

19 9 3 Mixer Mixer is another important part of almost all receivers and transmitters. The main role of a mixer is frequency translation by multiplication of two waveforms and possibly their harmonics. In the receiver, the down-conversion mixer senses the RF signal at its RF port and the local oscillator waveform at its LO port and the output that is called IF is at IF port. Typically, the down-conversion receiver mixer moves RF signal to much lower frequency by multiplication to the LO signal, thus, IF signal which is in lower frequency can be more easily amplified. A mixer can simply be realized as Figure 6(a), where V LO works as a switch on and off. Mixers can be accomplished with any non-linear devices (diodes, transistors) or time-varying elements (switches), while due to the high performance of a transistor as a switch, it is the most applicable method. Abrupt switching is a significant factor to be considered, if switching becomes slower mixer suffers from lower gain and higher noise. Figure 6: Simple mixer model. Generally, mixers are classified into passive and active topology, each can be formed as a single-balanced or a double-balanced circuit. When the transistor in mixer does not amplify, a mixer is known as passive as Figure 7 shows. Typically, active mixers can produce gain, while passive mixers are lossy but more linear. An active mixer can be realized so as to obtain conversion gain in one stage. However, the main drawback of an active mixer is generating noise, especially 1/f noise for direct conversion receiver since the output signals are at baseband. The mixer noise is mainly created in switching process by switching transistors. A passive mixer does not consume any power. In addition, there is a claim that since there is no DC current flowing through the mixer, passive mixers are free of 1/f noise. However, according to Refs. [30 32] passive mixer has flicker noise and the authors showed that the magnitude of it, is proportional to the input signal amplitude and inversely proportional to the slope of the gate voltage waveforms at LO transitions. Therefore, choosing the type of mixer depends on the system requirements and application. A mixer can be implemented with a single device, while single balanced mixers suffer from lack of isolation between RF and LO signal which can be minimized by

20 replacing the differential output instead of single to convey IF signal close to the DC. There is still some leakage from the LO or RF to IF port which is not important in direct conversion receiver, because of high frequency differences that can be simply filtered. Doubled-balanced mixers are more complicated, they need differential RF input which needs an LNA with differential output. This requires more power for having low noise, or using a balun at the output node of the single-ended LNA in order to convert a single-ended output to a differential one. However, balun has a complex structure and practically it is not easy to realize because if it is made of transformer it would increase the size of on-chip devices and also parasitics [33]. Moreover, there is another way to convert a single-ended output to a differential one, which is using CG transistor in order to shift the output of LNA 180 degree as shown in Ref. [34], while this method causes frequency phase shift, thus due to the sensitivity of mixer to the frequency it is not a proper topology. Therefore, using a differential LNA with an off-chip balun for the input of LNA in order to have a balanced signal from the antenna is the preferable architecture. In this thesis, the main focus is the most common active mixer topology, the Gilbert cell mixer, therefore at the first glance, a short overview of other types of the mixer is given. 3.1 Down-conversion mixers To design a down-conversion mixer there are several concerns that should be considered such as gain, noise and linearity. Designing a mixer is demanding due to the non-linearity and noise requirement. In the direct conversion receiver, dc offsets and 1/f noise of the mixer are the biggest problems. Since the most important data is located close to dc. Down-conversion mixers must provide sufficient gain to adequately suppress the noise contributed by subsequent stages. Additionally, because the output of LNA goes to the input of the mixer, thus mixer linearity should be higher than the LNA linearity by the gain of the LNA. In a receiver chain, the input noise of the mixer following the LNA is divided by the LNA gain when referred to the receiver input while the IP3 of the mixer is reduced by the gain of the LNA [22]. As a result, there will always be a compromise between the noise figure and IP3. Generally, in designing of the mixer the aim is to maximize the linearity, while not raising its NF. Mixer is usually a dominant source for the second-order nonlinearity especially for down-conversion or low IF as explained in Ref. [35]. Moreover, there is another important issue that we should consider, which is the port to port feedthrough. Mixers suffer from coupling (feedthrough) from one port to another. For instance, in direct conversion RF-LO and RF-IF feedthroughs are problematic, thus to avoid these effects, a buffer is typically placed between the LO and the mixer. Furthermore, when ω LO and ω IF are too close to each other LO-IF feedthrough can be a big problem, while when they have enough difference to be separated by filtering, thus in this case LO-IF feedthrough is not an important problem. This issue is strongly dependent on the mixer architecture. For example, if 10

21 the mixer is made of a MOSFET, then the gate-source and gate-drain capacitances create feedthrough from the LO port to the RF and IF ports Single-balanced and double-balanced mixers Single-balanced mixers suffer from significant LO-IF feedthrough. Figure 7 illustrates single-balanced mixer. The coupling V RF to V Out1 by αv LO and αv LO to V Out2, then V Out1 V Out2 = 2αV LO to eliminate this effect, we connect two singlebalanced mixers such that their output LO feedthrough cancel but the input signals do not. This topology builds double-balanced mixer. This topology as shown in Figure 8 operates with both balanced LO waveform and balanced RF inputs. Singleended RF is possible with grounding one port at the price of higher input noise. In 11 Figure 7: Single-balanced passive mixer. comparison of these two mixers in terms of conversion gain, Ref. [22] shows that the conversion gain of a double-balanced mixer is half of the single-balanced counterpart. Moreover, the input noise of single-balanced is lower than in a double-balanced. 3.2 Passive mixers A typical passive mixer is built of four NMOS transistors as analog switches as shown in Figure 8. These transistors act as switch and their work is to be on or off. There is no need for a bias current, thus this structure is low power and has low noise. The DC bias voltage of the gate of switch transistors has an important role in mixer performance. Gate voltage should be chosen somehow close to the threshold of conduction in order to obtain the lowest on-resistance. Therefore, noise from the switches is minimized and good linearity is achieved. Furthermore, if the voltage swing across the switch transistors is kept as small as possible, linearity performance would be maximized. For instance, in Ref. [36] this type of a passive mixer is discussed.

22 A passive mixer has non-unilateral nature, i.e. the signal flows bidirectionally from input to output, thus causing several problems. For example, while the passive mixer is connected to the output of the LNA, the circuit after the mixer can load the LNA and degrade its gain and selectivity [32]. Furthermore, the passive mixer needs large LO amplitude in order to minimize the overlap period when all switches are on [37]. As a result, the output impedance of the mixers is lowered, which increases the noise of first baseband stage. Additionally, the parasitic capacitances at the switch source and drain nodes lower the mixer s output impedance. With larger switches, there will be larger source-drain junction capacitances, which results in larger stored noise. These capacitances cause an equivalent resistor, which is inversely proportional to the LO frequency and the value of parasitic capacitances [30]. 12 Figure 8: Double-balanced passive mixer. 3.3 Active down-conversion mixers Active mixers can provide gain and they can convert RF voltage to the current, and then multiply RF current by the LO, and convert IF current to voltage. Figures 9 and 10 illustrate single-balanced and double-balanced mixers respectively. The most common mixer is probably the Gilbert-cell mixer and its variants. This type of mixer was proposed by Barrie Gilbert as a four-quadrant multiplier in

23 13 Figure 9: single-balanced active mixer [38]. Gilbert mixer as shown in Figure 9 is composed of a balanced grounded transconductance stage, which converts the input voltage signal to the current mode. After input transconductor, the signal is fed to the switching stage, which is driven by a large LO (i.e. 150 mv pp ). Typically the Gilbert-cell mixer is driven with balanced RF and LO signals. If a double-balanced structure either of the RF or LO signals are supplied alone, there is no output signal. Whereas, either of the input signals can be single-ended and the other sides can be ac-grounded. Therefore, The output of the single-ended LNA can be connected to the mixer like in Ref. [39]. In this case, the conversion gain is decreased because only half of the mixer input stage transconductance is utilized. Usually, double-balanced mixers are more interesting for down-conversion receivers, since they generate less even-order distortion, provide high port-to-port isolation, and usually have better noise performance than the single-balanced ones. In addition, single-balanced mixer despite being low power has big problem, which is large LO feedthrough at its output that may saturate the following stage [37] Mixer input stage The mixer input stage consists of a balanced grounded CS amplifier or a differential pair with a tail current source as shown in Figures 11(a) and 11(b), respectively.

24 14 Figure 10: Double-balanced active mixer (Gilbert mixer). It is crucial that all transistors work in their active mode in order to have a linear system. Typically, each MOS transistor should work in its active mode if the V GS is larger than the threshold voltage and also, V DS is more than the subtraction of gate-source voltage (V GS ) and the threshold voltage (V th ). Thus, if two structures are biased with the same current and device dimensions, the grounded CS stage has better IIP3 (third-order nonlinearity) performance than the differential pair with a tail current source [40]. However, the tail current source offers a common-mode rejection ratio, and the trade-off of the grounded CS stage is greater sensitivity to supply noise [40] Conversion gain The ratio of the output voltage signal at the IF frequency to the RF input voltage signal is called voltage conversion gain. The conversion gain based on the presentation in Ref. [22] is calculated as V IF V RF = 2 π g m1r D. (16) Now, it is important to understand the limiting factors of conversion gain. The gain is related to the linearity and voltage headroom. To provide linearity it is important that switching stage transistors perform in their active region.

25 15 RFin RFin 100mA (a) (b) Figure 11: Transconductance stage of mixer: (a) grounded CS stage and (b) differential pair with a tail current source. On the other hand, size of the input transistor is determined with respect to the overdrive voltage, V GS1 V TH1 and then V DS,min. The transconductance of M 1 2I depends on the drain current and it is expressed as g m1 = D1 V GS V TH1. Also, the value of R D is limited by the maximum allowable dc voltage across it. Therefore, according to the analysis performed in Ref. [22] the conversion gain is given by A V,max = 2 π g m1r D,max = 8 π V R,max V GS1 V TH1, (17) which shows that the low supply voltages strongly limit the gain of the active mixer. Thus, a question arises how we can improve the gain. The overdrive of input transistor has limited flexibility unless both the LNA gain and noise of mixer can be lowered. The overdrive of switching transistors can be reduced by widening these transistors, while raising the parasitic capacitors. When switching transistors are close to equilibrium, the RF current is split approximately equal between them, thus it performs as a common-mode current and it causes small conversion gain. Eliminating the LO swing would reduce the gain. Another factor that degrades the gain is related to the capacitance seen at the drain of the input transistor. Let us consider a single-balanced mixer as illustrated in Figure 12. When fast LO switching causes M 2 on and M 3 off, total capacitance at node P is C P = C DB1 + C GS2 + C GS3 + C BS2 + C SB3, (18) where C DB1, C GS2, C GS3, C BS2 and C SB3 are the parasitic capacitances of three transistors seen at node P. Therefore, RF current splits between C p and resistance has seen at source of M 2, g which is 1/g m2, that causes the reduction of gain by the factor of m2 SC p+g m2. As it is discussed in Ref. [22] the effect of the C p may become significant for relatively large frequencies.

26 16 Figure 12: Loss of RF current to ground through C p Mixer noise Switching transistors can be counted as one of the main sources of noise in the mixer, if they are not sufficiently fast. The thermal noise due to the transconductor stage is at the same frequency as the input RF signal. In down-conversion receiver, it will be down-converted to around DC frequency, just where the IF signal is located. Similarly, any periodic LO waveform down-converts the noise from the odd-harmonics of the LO signal. Noise of the switching capacitances should be noted, since the noise of these transistors increase by the factor of the differential gain. However, as explained before practically these switches are not fast enough, thus the large LO swing saturates the differential pair, thereby lowering the gain Linearity The linearity, more specifically IIP3, is controlled by both the transconductance stage and the switching stage. As explained before, the linearity of an active mixer is directly proportional to the drive current and the input transistor overdrive voltage. The IIP3 of a common source; increases when the overdrive voltage increases and subsequently this also increases the noise as it is illustrated in the following equations

27 17 [22] IIP 3 (V GS V TH ), V n,in 2 = 4KT γ 2I D (V GS V TH ). (19) Last but not the least, linearity degrades if the switching transistors enter the triode region.

28 18 4 Design Description 4.1 LNA design procedure In this section, various steps of designing an ultra low power LNA with specific characteristics are introduced and discussed. To obtain our purpose in this project, based on the explanations in the previous sections 2.2 and 2.2.4, the inductively degenerated common source LNA with a cascode stage shown in Figure 13 has been chosen. This project is implemented in a 65-nm CMOS technology. Since this Vdd Ld Vdd Vout I 100m C Vdd M2 Rs Lg M1 R M3 Vin C C Ls Figure 13: Low noise amplifier with bias system. receiver is going to be used in Bluetooth applications, the operation frequency is 2.4 GHz and the needed bandwidth is around 100 MHz. Firstly, we started the work with the design of input matching network in order to to achieve high gain, low noise and low return loss. Figure 14 shows the impedance seen from input which should be equal to 50 Ω. The method used to achieve low noise and impedance matching simultaneously is explained here. Such type of input system is well-studied, and it is common for the most RF receiver designers especially for the ones who choose IDCS-LNA. Figure 13 indicates the considered LNA for our design. Later in this section, output load design and bias system for this LNA is explained and discussed.

29 19 50V Cgs M1 Zin Ls Figure 14: Input impedance of inductively-degenerated CS stage. For matching, we need to find a topology in which the input is isolated from the inductive load with active devices to provide 50 Ω input resistance without the noise of a resistor. According to the expression for the input impedance which is written in Equation 7, L S, L g and C gs are the main components that have to be noted during input matching adjustment. As we explained before, the real part of the equation should be equal to 50 Ω. Since gm C gs ω T (ω T = 2πf T, where f T is the maximum operating frequency of the transistor), the input resistance is approximately equal to L S ω T and directly related to the f T of the transistor. In our case for the used 65-nm technology, ω T 2π 160 GHz, thus L S is calculated to be 50 ph [22]. Practically, the degenerating inductor (L S ) is often realized as a bond wire, since the use of packaging is inevitable in the design. In order to minimize the inductance, the source can connect to the ground plane in the package directly. However, the value of inductor from geometry is around 1nH, therefore, in this case the input impedance is much higher than 50 Ω. In order to obtain input matching at a frequency lower than f T we can use a capacitor in parallel with C gs. Moreover, one of the important aims of this work is to design ultra low power amplifier. To realize this goal transistors dimensions should be small which results in small parasitic capacitances in femto farad range or even smaller. Therefore, a parallel capacitor can be used in order to neglect the effect of these parasitic capacitors. The value of this capacitor can be chosen with respect to two issues: firstly, to overcome the effect of parasitic capacitors, and secondly to maintain the impedance matching. In addition, the effect of pad capacitance lowers the input resistance. Usually, a pad is modelled by a capacitor. Figure 15(a) shows the equivalent circuit of the input stage, where R 1 is the resistance of the transistor. The effect of the parasitic and pad capacitances cannot be matched just by L s, thus another inductor must be placed in series with the gate as shown in Figure 15. Let us explain about our LNA, since the transistors are small, then for matching we used a parallel capacitor (C=113 ff) which can be equal the summation of pad

30 20 Ls Cpad Cgs R1 Zin (a) Rs Lg 50V Cpad Cgs M1 Ls (b) Figure 15: Input stage of LNA: (a) equivalent circuit for inclusion of pad capacitance and (b) input stage with pad. capacitor and C gs. Also, L g is added in the gate that is off-chip inductor. The value of these components are calculated from Equation 20 with respect to the frequency of 2.4 GHz. ω 0 2 = 1 LC = 1 (L S + L g )(C gs + C pad ). (20) Therefore, after finding out the component values, we began the simulation in order to obtain the best impedance matching. Figure 16 shows the final schematic we obtained without considering the pad effect. 50 2pf 38nH 113fF M1(3u/0.7u) 50V 1nH Figure 16: Input stage without pad.

31 Later, after including the bonding pad connection to the schematic the simulation results changed, thus, we had to adjust the matching network again, and hence the component values have changed. Figure 15(a) illustrates the equivalent circuit of used pad connection. in other words, the practical pad connection has some other parasitic effects than just capacitance as it is depicted in Figure In n 2.2 Gate 260f Figure 17: Pad equivalent circuit in our design. As a consequence, the components that depicted in Figure 17 have also contributed in impedance matching. Therefore, the repetition of the whole optimization stages is necessary to gain the best possible input matching. We must admit this structure degrade the NF of the system while in reality avoiding all parasitic effects are impossible. Now, it is the turn of designing the output node of the topology. As explained earlier, an inductive load connected to the common source stage produces a negative resistance due to the feedback through C GD. Thus, we add a cascode transistor in the output in order to abolish this effect. Figure 18 shows the resulting circuit, where R 1 model the loss of L D. The voltage gain is dependent on the R 1 and the circuit transconductance which has been analysed in Ref. [22]. Vdd C1 Ld R1 Vout 100m C Vdd M2 Rs Lg M1 Vin C Ls Figure 18: Inductively-degenerated cascode common-source LNA. However, in our design, we use non-ideal inductor which has its own model like Figure 19. As the Figure shows non-ideal inductor has capacitance and resistance,

32 22 Figure 19: Equivalent circuit of non-ideal inductor. therefore R 1 and C 1 can be removed. In this part by using simulations we try to obtain maximum gain at the resonant frequency of (2.4 GHz). The best option here is to use a capacitor in output bigger than all parasitic capacitances (drain-bulk and drain-gate of M 2 and L D )in order to neglect the effect of parasitic capacitances. Thus, this capacitor would resonate at resonance frequency with respect to the value of L D. Furthermore, the dimensions of the cascode device are chosen equal to the input transistor. Therefore, in the layout stage since the source of cascode device is connected to the drain of the input transistor they can be placed on each other. Finally, the overall LNA appears as shown in Figure 20, where the antenna is capacitively tied to the receiver to isolate the LNA bias from external connections. The bias current of M 1 is formed by M B and I B, and resistor R B and capacitor C B to isolate the signal from the noise of M B and I B. R B is chosen much larger than R S to avoid noise contribution. The dark gray box represents the pad that has been introduced in Figure 17. Moreover, the pad should be placed between all on-chip and off-chip components and connections such as ground, V dd and the bias current source. We avoid drawing whole pad equivalent circuit for simplicity and the convenience of the reader. Table 1 indicates the component values of inductively degenerated LNA in either with pad consideration or without the pad Stability of LNA The stability is an important issue for an amplifier. It can be determined using S-parameters, matching network and termination. This system becomes unstable if either output or input sees negative impedance [25]. The stability of a system can be determined by Stern stability factor, K = 1 S 11 2 S S 12 S 21 (21) where the = S 11 S 22 S 12 S 21. A system is stable provided that two important conditions K > 1 and < 1 are valid. Based on the Equation 21 the designed

33 23 Figure 20: Equivalent circuit of non-ideal inductor. inductively degenerated LNA is stable since K = 980 and = Simulation result Here in this section obtained simulation results have been collected and shown. Figure 21 shows the simulated characteristics of designed LNA drawn in Figure 20. Obtained gain is demonstrated in Figure 21(a), Figure 21(b) indicates achieved return loss (S 11 ), and Figure 21(c) shows the noise figure (NF) of this topology. Furthermore, simulated gain, 1-dB comparison point and IIP3 of the LNA are collected in Table 2. Further, In Figures 22(a) and 22(b), S 11 and NF in the two situations with and without pad effect have been shown. As it can be seen and explained, NF is slightly smaller when we have not considered pad affects in addition to the NF, input band-width has compressed.

34 24 Table of transistor parameters and component values Component in simulation without pad in simulation with pad 4µm M µm 4µm M 2 M B 0.07µm 2.8µm 0.07µm 4µm 0.07µm 4µm 0.07µm 2.5µm 0.07µm I B 70 µa 55 µa R B 7 KΩ 7 KΩ Supply Voltage 1.2 V 1.2 V L s 1 nh 1 nh L d 2.95 nh 5.16 nh L g 38 nh 16 nh C out 960 ff 480 ff C g 113 ff 260 ff C 1 2 pf 10 pf C pf Table 1: Component values of LNA in both conditions when the pad has considered and has not. Simulation results table I dc 70 µa Supply Voltage 1.2 V I ds 95 µa P dc 114 µw 1 db compression point -18 dbm BW 130 MHz NF IIP3 Gain 5.09 db dbm db Table 2: Obtained properties of single-ended LNA.

35 25 (a) Gain (b) Return loss (c) Noise figure Figure 21: Properties of Single-ended amplifier with pad inclusion.

36 26 (a) Return loss (b) Noise figure Figure 22: Comparison of single-ended amplifiers with pad inclusion and without pad.

37 4.2 Differential cascode LNA In previous sections, the advantage of the double-balance mixer compares to the single-balance counterpart have been explained. Furthermore, we discussed that in practice with our technology using differential LNA is more efficient than using single-ended LNA. Additionally, the preference towards using differential LNA architecture due to the ability in rejecting common-mode noise is derived in Ref. [41]. Therefore, we duplicated our single-ended LNA to provide fully differential LNA with the same characteristics which we had for the single-ended LNA. Figure 23 demonstrates the differential LNA schematic and Figure 24 shows the simulation results of this system. 27 Figure 23: Differential LNA which consists of two single-ended LNA that introduced in the previous section. Moreover, In Table 3 the simulated performance of the designed LNA is compared with other similar LNAs found from the literature.

38 28 (a) Gain (b) Return loss (c) Noise figure Figure 24: Properties of differential amplifier with pad inclusion.

39 29 Comparison Table Parameter LNA of This work [42] [43] [44] [45] CMOS Technology 65 nm 65 nm 18 µm 18 µm 13 µm Frequency 2.4 GHz 2.45 GHz 2.57 GHz 2.44 GHz 2.4 GHz Gain [db] NF [db] S 11 [db] Supply Voltage [V] P dc 228 µw 100 µw 12.6 mw 2.7 mw 60 µw IIP3 [dbm] Table 3: Result comparison of various LNA design.

40 4.3 Mixer design procedure In this section, we discuss some practical steps in the design of the down-conversion mixer that we have chosen and also some details of simulations. Furthermore, mixer properties and then the obtained results are shown in Tables 4 and 5, respectively. In this work according to what we have discussed earlier in section 3, we decided to choose the active double-balanced mixer, Gilbert-cell mixer, as depicted in Figure 10. As we explained overdrive voltage and operation region of the transistors are very important in mixer performance. Therefore, transistor sizes in both transconductance and switching stages are significant. We start our design with some simultaneous changes for the size of transistors and bias voltages in order to ensure that all transistors are performing in the active region. Moreover, the value of R should be selected carefully, since very large value reduces voltage head-room of switching transistors and small one degrades the conversion gain. In Table 4 mixer properties has been gathered and shown. Table of component values of Figure 10 Component in simulation without pad in simulation with pad M RF M LO 1.5µm 0.07µm 2.4µm 0.07µm 3µm 0.07µm 3µm 0.07µm V Bias,LO 1.2 V 1.2 V V Bias,RF 700 mv 700 mv f RF 2.4 GHz 2.4 GHz f LO 2.41 GHz 2.41 GHz R 4 KΩ 4 KΩ I RF 94.5 µa 96 µa Supply Voltage 1.2 V 1.2 V Table 4: Table of Gilbert mixer value when the pad has been considered and has not. 30 Furthermore, ideal LO waveforms are a square wave from a zero source impedance with a large voltage swing, the time which four devices are on at the same time is zero. This guarantees for fast switching and then maximum conversion gain. However, at very high frequency, the LO wavefront is similar to a sinusoid, therefore there is a period of time that all transistors are on which causes wasting of the input signal. As a result, we choose large amplitude for LO so as to achieve high slew rate and minimize overlap time [22]. Our desire is to design direct-conversion mixer, but due to some simulation problems in zero frequency we select LO frequency close to the RF frequency but not equal to it, as it can be seen in Table 4. Now, after ensure about the DC operation of all transistors we can check other performance of our topology such as conversion gain, noise figure and linearity. The

41 achieved results of the simulation are classified in Table 5. As it can be seen that the noise of our topology is high, while LNA gain is almost close to the noise of the mixer, thus it is acceptable. Table of Gilbert mixer results Parametert result Conversion Gain 5 db NF IIP3 18 db dbm Table 5: Obtained results from simulation of Gilbert mixer. 31 Now we connect the designed differential LNA and Gilbert mixer. These two systems are going to be placed on the same chip with a short distance, and since our frequency is not that high we do not need intermediate impedance matching. Therefore, we just need to consider the effect of the input capacitance of RF transistor of mixer in the output of LNA. Additionally, we need to add a coupling capacitor to block DC and to be shorted in AC. Figure 25 illustrates the whole circuit. In this design, we have used the same pad as in the LNA, therefore the component values and results in both with pad and without pad design are collected and indicated in Table 6. Additionally, we have to remind the reader that, the pad should be connected to all nodes which are going out from the chip. However, as in LNA design, we avoid drawing all pad connections in Figure 25 in order to have more understandable and clear schematic view. Furthermore, some simulation results of this architecture such as ( V IF 1 V IF 2 V in1 V in2 ) conversion gain of LNA+ mixer and ( V IF 1 V IF 2 V RF 1 V RF 2 ), conversion gain of mixer and noise (NF) are shown in Table 6. Corresponding figures from the simulations of the whole system are shown in the next section in Figure 31 in order to ease the comparing of pre-layout and post-layout simulation results.

42 32 Table2 of component values of Figure 25 Component in simulation without pad in simulation with pad M RF 1.5µm 0.07µum 2.4µm 0.07µm M LO 4µm M µm 4µm M 2 M µm 2.8µm 0.07µm 1.5µm 0.07µm 2.4µm 0.07µm 3µm 0.07µm 3µm 0.07µm 2.5µm 0.07µm V B 1.2 V 1.2 V g m,rf µυ µυ g m µυ 987 µυ V th,rf mv mv V th,lo mv 651 mv I B 70 µa 55 µa V Bias,LO 1.2 V 1.2 V V Bias,RF 700 mv 700 mv f RF 2.4 GHz 2.4 GHz f LO 2.41 GHz 2.41 GHz R 6 KΩ 4 KΩ I RF 94.5 µa 96 µa V in1 V in2 ) 21.9 db 20 db ( V IF1 V IF2 ( V IF1 V IF2 V RF1 V RF2 ) 2.1 db 3.6 db NF 14.4 db 16 db Supply Voltage 1.2 V 1.2 V C out 450 ff 450 ff C c 2 pf 2 pf Table 6: Table of Gilbert mixer value when the pad has been considered and has not.

43 5V 50V 33 VDD R1 R2 IF -IF LO M2 M3 M5 M6 LO -LO Vbias,RF Vbias,RF 5V M1 M4 Vdd C3 Vdd C3 Ld Ld Vdd M2 Cout Vdd Vdd M2 Cout Vdd C1 Lg M1 100mA Rb Ib C1 MB Lg M1 Rb Ib 100mA MB C2 Cg Cb C2 Cg Cb Ls Ls Figure 25: Differential LNA connected to the gilbert mixer.

44 5 Physical Layout and Post-Layout Simulation Results 5.1 Layout design In this section, the LNA+mixer layout and post-layout simulations are discussed. The tool used for the layout and post-layout simulation is virtuoso layout editor. In layout design there are some issues which should be noted in order to obtain the best performance. Microscopic fluctuations in dimensions, doping, oxide thickness and other parameter cause random mismatches which affect on the component values. Although these effects cannot be entirely eliminated, but they can be minimized. Therefore, there is a method called common-centroid layout that can be used in order to firstly reduce some mismatches, and secondly to shrink large devices to smaller ones with the same properties. The common-centroid layout is the most useful technique for minimizing stress-centroid mismatches. In this arrangement, device should be split into two identical parts which are located symmetrically compared to the center axis. Figure 26 shows an example of common-centroid layouts produced by arraying segments of matched elements along one dimension. This type of layouts are called interdigitated arrays. Since the sections of one element interpenetrate the section of the other like the intermeshed fingers of two hands, more details about matching and this type of arrangement can be found in Ref. [46]. 34 (a) Figure 26: Example of common-centroid array. In addition to device mismatches, the wiring also causes parasitic effect in the circuit. Generally, the on-chip wires are characterized as RC lines, thus the signals attenuate over the long signal paths, and may also couple to each other. Therefore, the following considerations must be taken into account to avoid unwanted parasitic effects. Firstly, metal selection for connection is an important issue. For instance, the path between devices and supply voltage must be wide and with low impedance in order to minimize the voltage variation. This is a noticeable issue since it may lead the transistors in the triode region and degrade the linearity. Secondly, to protect the structure from coupling and cross-talk, an appropriate distance between two metal paths should be always kept. Moreover, we have to avoid using long parallel paths with the same type of metal. In our design due to limited number and small size of transistors we prefer to

45 use interconnection method. Due to the large size of the resistors, we divided them to the several smaller resistors and then connected them in series. Therefore, we created a more compact structure with smaller resistors. The designed resistor R B is indicated in Figure 27, the 7 KΩ resistor is divided to the eight 875 Ω resistors and then they are connected in series. By the help of this method size of the resistor has reduced significantly. 35 Figure 27: Modeled R B layout. Initially, we started with the single-ended LNA layout, we tried to design symmetrical architecture to minimize the parasitics and size of the structure. During the design we run DRC (design-rule-checking) Calibre regularly, to be sure that the designed layout satisfies the parameters of design rules such as proper distances and size of elements. After that, LVS(Layout versus schematic) Calibre was run in order to confirm the similarity of layout and schematic. The parasitics of the designed layout was extracted by running PEX Calibre, and then these parasitics were imported into the simulation as in section 5.2. After finding proper performance from the single-ended layout, with duplication the differential LNA layout was created. Later, we designed mixer layout as shown in Figure 28 and then we combined the two systems as depicted in Figure 29. This Figure shows the final layout of the differential inductively degenerated common source LNA connected to the Gilbert mixer. Due to the large area of inductors, the other components are hardly seen. After all, the on-chip parasitics cannot be completely removed, thus the on-chip performance usually differs from circuit-level simulation results. Therefore, postlayout simulations must be carried out in order to obtain more realistic results. The following section describes the post-layout simulation results. 5.2 Post-layout simulation results Here in this section, all of the simulations in previous sections are repeated with the on-chip parasitic extraction.

46 36 Figure 28: Mixer layout. Figure 29: Differential LNA connected to the Gilbert mixer layout. In Figure 30 the comparison of the pre-layout simulation and the post-layout simulation of differential LNA is reported. As it can be clearly seen, the results are very close in both conditions, thus the parasitics do not affect the performance of the differential LNA so much. However, according to Figure 30(a) The gain of the LNA in the post-layout simulation has dropped by 2 db, but it has considerably larger bandwidth. The second plot illustrates S 11 comparison, where the induced parasitics have changed the matching slightly, thus resonance has shifted gently, while S 11 is still very good at the frequency of resonance. Finally, the noise figure of the differential LNA has increased approximately by 1 db based on Figure 30(c). From all of these results, we can conclude that in the LNA layout design, we relatively