A 900 MHz CMOS RF Receiver

Transcription

1 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 1 A 900 MHz CMOS RF Receiver Illinois Institute of Technology ECE 524 Project Spring 2002 Yeu Kwak and Johannes Grad Abstract A radio frequency receiver chip is implemented in a foundry 0.25um CMOS process. The target RF frequency is 900MHz and the intermediate frequency was chosen to be 100MHz. A low noise amplifier provides a 50Ω input impedance and utilizes a tuned load to provide high selectivity. The amplified signal is converted to a 100MHz intermediate signal with a double-balanced down-conversion mixer. A third order low-pass filter and a feedback amplifier perform the final filtering and amplification. The 50Ω output load is driven by an optional source follower device. The overall gain is 51dB, while a noise figure of 1.7 db is achieved. The receiver consumes 2.5mA from a 3.3V supply. I. INTRODUCTION obile wireless transceivers face relentless pressure for low cost, low power, and small size. A highly Mintegrated CMOS realization is therefore of great interest. Current interest and demand for portable wireless communication services has increased the emphasis on the development of radio-frequency communication integrated circuits (ICs) 100MHz INPUT IMPEDANCE ( 50 Ω ) LNA LOCAL OSCILLATOR (1GHz) IF FILTER IF AMP OUTPUT IMPEDANCE ( 50 Ω ) Figure 1: 900 MHz Receiver Block diagram There has been a great deal of progress in CMOS technology. The difference between BiCMOS and GaAs technologies and CMOS technology is that only CMOS has the ability of integrating a RF front end and DSP components in one single chip. Therefore it is for the first time possible to incorporate for instance a complete set of cellular phone electronics onto a single highly integrated die. In this paper, we are focusing on a 900MHz RF signal receiver that can convert the RF signal to some desired intermediate frequency (IF), while offering narrow bandwidth characteristics to improve selectivity. A double balanced down conversion mixer is used to obtain the desired intermediate frequency, which in this design was chosen to be 100MHz. Fig. 1 summarizes the signal flow, as well as all frequencies involved. Tight specifications and denser spectral distribution of information of 900MHz RF signal receiver make it the least amenable to direct conversion of design in chips. The chip was designed in a 0.25 um CMOS technology, which is quite competitive with today s bipolar implementations. It is generally accepted that RF-CMOS circuits are good for short-range communicators such as DECT or Bluetooth and cellular standard such as GSM.

2 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 2 II. SPECIFICATIONS This section presents the initial specifications that were chosen for this project. They are a mixture of typical values from current research or simply educated guesses. The 900MHz RF signal is received through the antenna, where the antenna gain and loss are not of interest here. The LNA gain shall be approximately 30dB, while maintaining a bandwidth as narrow as possible, to suppress the image frequency of 1.1GHz. The intermediate frequency was set to be 100 MHz and is achieved using a doublebalanced down-conversion mixer. Every active mixer could theoretically supply conversion gain, however it will depend on implementation issues if such gain will become available. Two ideal RC low pass filters are used to filter the intermediate frequency (IF), with a typical 3db loss in each filter. A feedback-op amp is used for IF amplification and final filtering. The noise figure of the system should be below 5dB, but no more than 5mA of current should be consumed by the receiver (excluding output driver). Both, input and output have to interface with 50 Ω loads. Table 1 summarizes the initial specifications. Table 1: Initial 900 MHz Receiver Specifications Element Specification RF Frequency 900 MHz LO Frequency 1 GHz IF Frequency 100 MHz Input Impedance 50 Ω Output Impedance 50 Ω Noise Figure 4 db Gain 40 db Current Consumption 5 ma Supply Voltage 3.3 V Technology CMOS, L eff = 0.25µm III. DESIGN APPROACH AND ARCHITECTURE DESCRIPTION Every RF CMOS design has to cope with a host of difficulties. This section discusses some of these challenges and shows how they have been approached and implemented. A fundamental problem in all designs with frequency down-conversion is the image frequency. In this particular design, if the local oscillator (LO) provides 1 GHz, both frequencies, 900MHz and 1.1GHz will be converted to the IF of 100 MHz. Suppression this image frequency of 1.1GHz prior to the mixer is therefore of essential importance. Usually an external antenna filter will perform a great deal of attenuation already, leaving only part of the burden on the integrated circuit. Usually low- or band-pass filters are used immediately after the LNA. In this design, a tuned load was incorporated into the LNA. An inductor was chosen, such that it resonates with the capacitive load of the mixer input, providing highly selective LNA gain and an image suppression that deemed sufficient for typical applications. If the LNA is to interface directly with the antenna (or the antenna filter), a 50 Ω input impedance has to be established. However, a resistive input of this quantity would greatly degrade noise performance. Since the noise figure of cascaded stages is almost exclusively determined by the gain and noise figure of the first stage, care has to be taken to avoid as many noisy components as possible. This in turn implies to use as many reactive components as possible, since those are ideally free of noise. In this design, inductive source degeneration is used to compensate the gate-source capacitance of the transconductance device such that at resonance a purely resistive part remains. The input impedance match is therefore provided only with the

3 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 3 use of reactive devices. One problem that was not clear in the beginning are the absolute values necessary for these reactive devices. In a 0.25um process, the gate-source capacitance even of a very wide device is rarely greater than 200fF. The corresponding inductor would need to be as big as 150nH for RF resonance of 900MHz. This value is clearly not yet available in standard CMOS processes. A perfect input impedance match is therefore not realizable for this relatively low frequency of 900MHz, but the match is still within an acceptable range. In CMOS, the input resistance of any two-port is almost purely capacitive. In order to provide a good match between the LNA output and the mixer input, the LNA load is tuned to resonate with the mixer load capacitance. In exchange for possible conversion gain, the mixer tail devices are made wide and long to provide large and stable capacitances. An inductive load of 26nH was found to provide perfect resonance at 900MHz. This tuned LNA load also obviates a dedicated image suppression filter, improving both, area and noise figure considerations. In an active CMOS mixer with square-wave LO switches, conversion gain is easily available. However, the gate overdrive voltage on the switch devices has to be carefully chosen, since excessive overdrive will dramatically increase LO feed through, even though a double-balanced mixer is supposed to suppress LO. For this design, a LO amplitude of 1.2V was chosen, providing enough overdrive to provide low on resistance in the switching path. But this voltage is still low enough to avoid excessive channel-charge current spikes. This gate feed through can severely influence both, LO feed through and linearity and is therefore kept to a minimum here. All bias currents are derived from an on-chip bias generator. A self-biasing bootstrap circuit was chosen that employs an external resistor as a current reference element. Since its tolerance can be arbitrarily low, very good die to die and waver to waver bias stability is possible. A small bias current of 25uA is supplied to all circuits to limit the power consumption to an absolute minimum. The final IF amplification is performed by a textbook feedback operational amplifier structure. It not only provides an RC-time constant for a third pole at 100 MHz but also delivers an additional 10 db of IF gain. This amplified signal is fed to a generously designed source follower to drive an external 50 Ω load. For on-chip demodulation, this output stage if of course redundant and great area and power consumption improvements are possible. IV. CIRCUIT DESIGN All circuits in this design operate from a single 3.3V power supply. All devices have a drawn/effective channel length of 250nm, unless otherwise mentioned. The circuit design was performed on SUN Ultra 5 workstations, using Cadence IC Tools, mainly Composer, Analog Artist and SpectreRF. Initial simulations were also performed using Cadence SpectreS and Avanti HSpice. A. Receiver Architecture The top level receiver schematic is given in Figure 2. All external components are clearly visible: The RF input source, a differential LO signal, the midband voltage for the IF amplifier, a 20kΩ resistor for the bias circuitry, and finally the 50 Ω output load. The source follower M0 is not necessary for on-chip demodulation. It is included here for reference to show a complete single-chip RF receiver. The inputs to both the LNA and mixer only are ac-coupled, while level shifting is employed for the IF path. All schematic blocks contain solely transistors, resistors, inductors and capacitors, all of which deem appropriate for CMOS integration.

4 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 4 Figure 2: 900 MHz Receiver Toplevel Schematic B. Low Noise Amplifier (LNA) The project uses an inductively degenerated common source amplifier with tuned load and cascode transistor [1]. Based on noise and power consumption constraints, the optimum width for the commonsource transistor is solely based on technology parameters [1]: 1 W = 3 ω L C ox R s With the desired input impedance of 50Ω and a target RF frequency of 900MHz, W of M0 is required to be 480µ in this technology. To account for the miller effect due to the big gate-drain capacitance of this device, a cascode transistor M1 is added. However, it can be shown that excessive drain-gate capacitance from M0 can offset the miller compensation and further decrease RF performance. To mitigate this, M1 and M0 are chosen to be of equal size, such that the source and drain contacts can overlap in layout [1]. To provide a matched 50 Ω input impedance, an ohmic resistor could be used. However, in order to avoid the added thermal noise, inductive source degeneration is used, which ensures that the input impedance at resonance resembles a 50Ω resistor. In a simple small-signal model, the input impedance of a MOS transistor with source degeneration and its gate-source capacitance is found to be [1]: 1 gm 2 Z = s Lg + + LS, Cgs = Cox W L s Cgs Cgs 3 Now Ls is chosen such that the real part of Z is exactly 50Ω. The imaginary part vanishes at resonance. However, since C gs is already fixed, an additional degree of freedom is necessary. Therefore, a gate inductance L g is added, such that the sum of L g and L s resonates with C gs. These part values are therefore found like this: RSCgs 1 L S =, Lg = Ls gm ω 2 Cgs For this design, L s is found to be 2nH, which requires L g to be 18nH. In the given schematic, L s is printed as L1 and L g as L2 respectively. For this narrow-band application it is helpful to incorporate a tuned load.

5 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 5 L0 was chosen experimentally to resonate with the load capacitance, which in this design is the input capacitance of the mixer. The mixer input device was chosen rather big, to allow for a big input capacitance which in turn allows for a somewhat smaller L0, even though the required 26.7nH is still a large value. The bias current in M0 was chosen to be 1.1mA, which is established by the current mirror formed with M2. A central bias current of 25µA is received from the bias generation circuit. The actual RF signal is ac-coupled by means of C3. The theoretical minimum noise figure of this constellation is readily obtained as shown in [1]: ω Fmin = ωt Following are the numbers, that follow directly from the simple first order model presented so far. C gs is obtained as 1.3pF and g m comes out to be 39mS. Therefore ω t is about 21GHz, which results in a minimum possible noise figure of 1.6dB with the chosen bias current of 1.1mA. However, once the DC operating point for M0 from SpectreRF using bsim3v3 models was available, it became clear that the values above needed to be severely corrected. Mainly, C gs at 1.1mA is really only 189fF, almost one order of magnitude less than the estimated zero order value. However, due to short channel effects, the available transconductance at 1.1mA is only about 24mS, again a great deviation from the simple model. Now using these values for minimum noise estimation, Fmin drops to 0.5dB, a more than excellent value. This is no surprise though, since ω t now rises to 120 GHz and it is well known that noise performance increases with the distance of RF frequency from ω t. On the down-side however, such a greatly decreased C gs also requires a great increase in gate inductance to retain resonance at 900MHz. Unfortunately, Lg now has to be as big 150nH, clearly value beyond the scope of implementation. Therefore once again a trade off is necessary between optimum noise performance and optimized impedance match. The values chosen for this design provide a good compromise, allowing for excellent noise performance and sufficient power transfer. Figure 3: LNA Schematic C. Active Double-balanced Mixer For this design, the RF frequency was chosen to be 900MHz and the required IF is 100Mhz. Therefore, after amplification the signal is multiplied with a local oscillator (LO) frequency of 1GHz. In order to minimize LO-feed through a double-balanced mixer is used. To simplify the amplifier design, only a

6 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 6 single-ended LNA is used. Therefore at the mixer the amplified RF is referenced to a DC bias value in order to obtain a differential signal. The RF is ac-coupled with C0 and added to a DC bias through R0. The bias is derived from a reference current of 25µA from the bias generator. Since the overall receiver is designed for single-ended operation, a current mirror is added to convert the differential mixer output into a single-ended output signal. While this conversion is able to provide additional gain, overall mixer gain was kept small to improve the linearity of the down-converted signal. In a similar manner, the LO amplitude was kept as small as possible to minimize current spikes from gate feed-through at the on-off switching points. The amplitude was chosen to be 1.2V, which provides just enough overdrive for M0, M5, M1 and M2 for full switching action. The input transconductance devices M4 and M6 are chosen long and wide for two reasons. First, since the tuned LNA load has to resonate with the input capacitance of M4, a high value is desirable to allow for a smaller load inductance on the LNA side. And second, a long-channel device is formed to improve linearity and to mitigate short-channel effects. The mirror structure provides a gain of about 12dB. The desired intermediate frequency (IF) output is 100Mhz. Further ac-coupling is avoided, due to the large coupling capacitors required. Therefore, level shifting is employed to achieve an output DC value of about 1.65V. To avoid added noise and attenuation from a possible source-follower stage, R1 is inserted into the tail current path of the mixer differential pair, delivering a sufficiently constant voltage drop to shift down the mixer output signal. Figure 4: Mixer Schematic Figure 5: Passive RC Filter

7 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 7 D. Active Low-pass filter IF filtering is obtained with a cascade of three RC low pass filters, two of which are passive filters, as can be seen from Fig.5. The third low-pass is implemented in the feedback path of an operational amplifier structure which also provides the final IF amplification. The opamp is formed by the differential pair M0/M1 and the active load devices M13/M14. The gain of this combination is found to be [3]: µ n Wn A = µ p Wp which is about 6.3 for the devices used here. Additional gain is provided by the current mirror structure that forms the single ended output. In simulation the open-loop gain was measured to be about 250. Even though this is not big enough to allow for the infinite-gain approximation of typical opamps, no more gain was added to keep the power consumption to a minimum. The pole formed by C0 and R2 provides the necessary cut-off frequency of 100MHz, while the ratio of R2 and R3 determines the closed loop gain of the amplifier. The mid-band voltage is not derived on-chip since it was found to be too expensive in terms of both area and power consumption. The tail bias current is derived through the mirror device M6 which receives 25µA from the bias generation circuit. Even though the active load devices M13/M14 consume considerable head-room, this was not found to be a limitation since the necessary swing is far less than the available output swing. In addition, active loads consume much less area than resistors, which would have to be of the order of 10kΩ or more. Figure 6: Operational Amplifier Schematic E. Bias Generation Circuit A central bias circuit provides all modules of the receiver with bias currents. To enhance power-supply variation rejection, a self-biased bootstrap structure was chosen [2]. An external reference resistor of 20kΩ can be made arbitrarily precise to deliver a very constant gate-source voltage at M2. The current mirror, formed by M4/M5 accepts the current from M2 and feeds it back into M1. This is clearly a structure with positive feedback, however stability is given since the loop-gain is less than unity. The circuit actually exhibits two stable points, requiring some kind of start-up circuitry in actual implementations. Since this was not the objective in this project, only the basic loop was implemented. Small devices were chosen to keep the loop current to a small 25uA. Hand calculation does not lead to useful results, due to the great approximations involved. The devices were therefore sized using DC operating point simulation in

8 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 8 SpectreRF. The loop current is about 30uA, slightly more than the desired 25uA. The current consumption is therefore a rather negligible 60uA for the bias generator. The external resistor is connected to a pin, as shown in Fig 7, which has the complete bias generator schematic. A value of 20kΩ is necessary for ideal operation. Figure 7: On-Chip Bias Generation Circuit V. SIMULATION RESULTS A. Low-Noise Amplifier The minimum possible noise figure in the hand calculations, driven by simulated operating conditions was found to be 0.5dB, which is clearly an idealized lower bound. However, as the SpectreRF simulation in Fig 8 demonstrates, the achieved noise performance with a noise figure of 1.5dB at 900MHz is still an excellent result and is far less than the initial specification of 3dB. It is remarkable that this value is achieved without great sacrifices in power consumption, as only 1.1mA of bias current are necessary. Figure 8: LNA Noise Figure Simulation Waveform

9 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 9 On the other hand it is also visible that the absolute minimum in noise figure is not achieved since it occurs around 1.5 GHz. This is clearly the consequence of the imperfect input impedance match. However, due to the great ratio of ω t to ω the noise performance is nonetheless excellent and perfectly acceptable for this design. Figure 9: LNA Gain Simulation Waveform Next consider the LNA gain, as obtained through AC simulation in SpectreRF. The maximum is clearly at 900 MHz, the desired resonance that was achieved by matching the load capacitance with the drain inductance in the LNA. The Q of this LC tank was not available in the hand calculations, however in order to avoid oscillation and excessive ringing it necessarily has to be far lower than the infinite large theoretical value. Initial simulation on the stand-alone LNA displayed excessive, non-decaying ringing which could be traced back to the exclusively ideal reactances used. A small resistor in series with the inductance resolved these issues immediately. As can be seen from Figure 9, the 3dB bandwidth of the LC-tank is 66 MHz. Using the well known approximations ω0 1 Q =, C = BW 2, ω L Q is found to be about 13, while the load capacitance C is of the order of 1.3pF, which is expected from a wide device with a channel length of 0.8nm. It is also clearly visible that the image frequency at 1.1GHz is amplified by 24dB, which represents a gain of 13dB with respect to the peak gain at 900 MHz. Combined with additional attenuation from an external antenna filter, this value deemed sufficient for this project. The usual measure of linearity for RF circuits is almost exclusively the third-intercept point with respect to the input power (IIP3). Since measurement with SpectreRF requires considerable computational effort, the IIP3 value of this LNA was only estimated with the convenient three-point-method [3]. By finding the incremental gain at three points, IIP3 is readily estimated with the following relation: 2 4V g(0) IIP3 = R g( V ) + g( V ) 2 g(0) s

10 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 10 where V is an amplitude level, relative to the DC value of 0. Using V=200uV, this measurement was performed using transient simulation of the presented LNA. The following table summarizes the measured gain values: IIP3 Gain Measurement for LNA g(0) g(v) g(-v) Plugging these numbers into the IIP3 approximation relation, yields a value of IIP3 = -34dBm. This is clearly a disappointing result and far below usual values for IIP3. It remained unclear at the end of the project as to the origin of this poor result. One explanation would be the fact that an ideal source inductance was used, while it is known that IIP3 improves with lower Q s. However, providing non-ideal inductors in SpectreRF did not improve the result. It is also know that increased gate overdrive at the common-source transistor improves IIP3. However, to achieve significant increase in V gs would require great increases in bias current, which is not tolerable. Lastly it remains unclear as to whether the threepoint method is valid for deep-submicron devices, as they are used for the LNA. In addition, the rather high supply voltage of 3.3V probably favors non-linear short-channel effects. The design was progressed too much at this point to allow for a reduction in supply voltage but it remains the opinion of the authors that additional work could improve the third-intercept value of the LNA. Figure 10: Complete 900 MHz Receiver Transient Simulation Waveform B. Overall 900MHz Receiver Chip Since the mixer is tightly coupled with the LNA through a tuned LC-tank, it was found difficult to perform isolated SpectreRF measurements that could correspond to results found from full-chip simulations. Further insight into receiver performance is therefore obtained exclusively from full-chip simulation in SpectreRF. A typical transient simulation waveform is given in Fig. 10. A rather large input RF amplitude of 1.5mV was used to obtain clearly amplified and easily visible signals. Mainly, the LNA output, symmetrical to the VDD-rail voltage of 3.3V and the mixer output, with the obvious superposition of high and low frequency components. The mixer gain is also recognizable. The smooth line centered

11 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 11 around 1V is the final output as delivered to the 50 Ω output load. Third order filtering with a cut-off at the IF of 100MHz, combined with an additional amplification of 10dB provides a very smooth and attractive output signal. Figure 11: Complete 900 MHz Receiver Output Spectrum (1024 pt. DFT) Figure 12: Complete 900 MHz Receiver Noise Figure Simulation Result

12 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 12 To further underline the statements of the last paragraph, now consider the output spectrum of the receiver, as seen by the output load. All amplitudes are referenced to the IF output amplitude. The IF component of 0dB is clearly visible and greatly exceeds the noise floor of non-linear signals. RF feed through is minimized, with an attenuation of 41dB with respect to IF. LO feed through is even further reduced, with an LO attenuation of 47 db, again with respect to IF. The third harmonic to IF at 300 MHz hardly exceeds 40dB, indicating sufficient linearity to some extent. Of almost equal interest is overall noise performance. Fig. 11 shows SpectreRF results for a full-chip noise analysis, as performed with a sweep from 1kHz to 2GHz with 801 points. A tick-mark is printed for every point and the dense spacing shows the great simulation resolution achieved, in conjunction with the accurate setting for the simulator. The noise figure assumes a global minimum at exactly the IF of 100 MHz, exactly as predicted by theory, since mixer gain is 12dB then and according to Frii s formula, the gain of the second stage is still quite important for cascaded noise performance. The great increase in noise figure for larger frequencies can be traced to up-converted flicker noise [3]. VI. SUMMARY Table 2 summarizes again the current consumption required to achieve the measured noise performance, as well as the required receiver gain. Due to the low RF frequency as compared to the intrinsic device switching frequency, a low 1.12mA bias current is necessary for sub 2dB noise figure performance. Mixer current consumption is the second largest, mainly due to the bias current required for the two big tail transconductance devices. The output source follower would consume an additional 32mA to drive the output load. This amount is as usual not included in the power budget. However, the gain improvement due to their large capacitance is reason enough to justify this slight increase in current consumption. LNA Mixer Feedback Amplifier Bias Generator Overall Current Consumption Table 2: Bias Current Distribution 1.12 ma 0.84 ma 0.48 ma 0.06 ma 2.50 ma For the feedback amplifier, open loop gain was kept to a small 250, in order to minimize the required bias current for the single-ended mirror structure. This is justified since only a small and constant closed loop gain of 10dB is necessary for this application. Table 3: Receiver Path Gain Distribution LNA Mixer Dual pole passive IF-Filter Single pole active IF-Filter Output Driver Overall Receiver Gain 37 db 12 db -6 db 10dB -2 db 51 db Table 3 summarizes again the receiver gain contributions from the individual building blocks. LNA gain is by far the largest, which is due to the high transconductance for optimized noise performance. Since the overall noise performance is greatly dependent on large LNA gain, the initial requirement with respect to noise figure can be easily exceeded. The passive RC filters attenuate by 3dB each, since the cut-off was chosen at IF frequency. Therefore the closed loop gain compensates for this loss, as well as for the slight

13 ECE 524, Yeu Kwak and Johannes Grad: A 900 MHz CMOS Receiver 13 loss in the output common source stage, as expected due the loss of one threshold voltage, augmented by body effect. As stated above, the initial specifications for this receiver have been significantly improved in terms of gain, noise figure and current consumption. No initial specification for LNA IIP3 and the image attenuation was given. However the achieved values are found to be acceptable for this first project design. Table 4: Initial 900 MHz Receiver Specifications vs. Performance Specification Achieved Performance LNA Noise Figure 3 db 1.5 db Overall Noise Figure 4 db 1.7 db Gain 40 db 51 db Current Consumption 5 ma 2.5 ma LNA IIP3 N/a -34 dbm Image Attenuation N/a -13 db Table 4 summarizes the total amount of passive devices required for this RF receiver. Inductance and capacitance are especially critical since high quality high value elements are hardly available in standard digital CMOS processes. It can be seen that the total amount of inductance is below 50nH. If a fraction of this value is contributed from input bond wires, a full integration of this value is readily imaginable. Overall required resistance and capacitance is less critical and does not hinder full integration of this project in standard foundry processes, even if no special resistive layers are available. Table 5: Amount of required passive elements Resistance [Ω] Capacitance [F] Inductance [H] LNA 2k 10p 49.5n Mixer 2.6k 15p RC Filter 1 3.2k 0.5p RC Filter 2 3.2k 0.5p Opamp 10k 0.2p Total 21k 26.2p 49.5n VII. CONCLUSION A fully integrated CMOS RF receiver at 900 MHz has been implemented and simulated. The initial specifications, together with common implementation issues are discussed and illustrated with the implementation approach for this project. After a detailed description of all individual circuits, simulation results as obtained with SpectreRF are given. LNA linearity is found to be poor, due to a low value of IIP3, however several options for possible improvement are given. The noise figure greatly exceeds initial expectations and is found to be 1.7dB. In addition 11dB more gain than required is available, together with only half the current required as originally budgeted. REFERENCES [1] Thomas H. Lee, The design of CMOS Radio-frequency Integrated Circuits.Cambridge University Press, Cambridge, [2] Paul Gray, Analysis and Design of Analog Integrated Circuits, John Wiley&Sons, New York, 2001 [3] Behzad Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, Boston, 2001