7. Low-Noise Amplifier Design

Transcription

1 7. Low-Noise Amplifier Design 1

2 Outline Low noise amplifier overview Tuned LNA design methodology Tuned LNA frequency scaling and porting Broadband low noise amplifier design methodology 2

3 7.1 LNA overview 3

4 Tuned LNA topologies CB/CG (no feedback) Cascode (L or xfmr feedback) CS/CE (L or xfmr feedback) 4

5 Design goal Minimize the noise of the amplifier for a given signal source impedance to approach transistor minimum noise figure/factor NFMIN/FMIN Rn 2 F=FMIN Ys Ysopt Gs Input and output matching to source and load. Maximize gain (G) and linearity (IIP3) Reduce DC power PDC => conflict with F and IIP3 G IIP3 f FoMLNA = F 1 PDC 5

6 Design philosophy Take advantage of what silicon does best: transistors. Use Si passives only sparingly: Q is fairly low and undermines overall noise figure Inductors are (significantly) larger than transistors, hence expensive. Make transistor sizing part of the noise matching step. Use only reactive (loss-less) feedback or minimize the noise contribution of resistive feedback components. Avoid active loads if at all possible. 6

7 LNA design fundamentals Device noise fundamentals: Re{Zsopt} <> Re{ZIN} and Im{Zsopt} approx. Im {ZIN} (within 15%) Re{Zsopt} = k ft/(fgm) FMIN is invariant to number of gate fingers Nf, and number of transistors m connected in parallel, but depends on Wf. Reactive (lossless) feedback does not affect FMIN and Re{Zsopt} Power is dictated by noise impedance matching (VDD JOPT ft/ g'm) Saving power comes with the price of compromising noise and linearity! 7

8 Tuned and broadband LNA design philosophy Active device for noise impedance Find optimal W f for given frequency Bias for minimum NFMIN and sizing (Nf) for Re{Zsopt} = 50 F MIN W f =0 W f F 50 N f =0 N f (lossless) feedback for input impedance matching ZIN and Im{Zsopt} All lossless feedback configurations work: Series-series, shunt-series, series-shunt, shunt-shunt Transimpedance feedback works best for broadband LNAs 8

9 Biasing LNA topology for minimum noise MOSFET, cascode JOPT = 0.15 ma/µm irrespective of Wf, node, and frequency Lowest current for optimally biased MOS-LNA is 150 A for single 1 m finger In HBTs JOPT varies with frequency, topology, and technology node 9

10 Sizing the MOSFET/HBT (cascode) for RSOPT RSOPT FET/HBT (casc) biased at Jopt NFMIN Z0 1/NfOPTor 1/lEOPT Noise parameters scale with (le)nf for fixed Wf. 1/Nf (1/lE) ℜ[Z sop t Nf, f ]=Z 0 coincides with ℜ[Z sop t l E, f ]=Z 0 coincides with F5 0 N f N f F5 0 le l E =0 =0 10

11 Sizing the FET (cascode) for RSOPT Rn = R N, FET Nf N Gu =G N, FET 2 N f N B cor =B FET N f N Gcor =G C, FET N f N 2 Y sopt = G cor Zsopt FET Gu jbcor =N N f W f Rn f Teff N Nf W f f g 'meff N N f= [ 2 GC, FET GFET j B FET R FET ] g 'm R 's W f g 'm R 'g W f j = Z0 j Xsopt k1 f Teff Z 0 W f f g ' meff g ' m R ' s W f g ' m R ' g W f k1 11

12 Sizing the HBT (cascode) for RSOPT Rn = R HBT N le Gu =G HBT 2 N l E B cor =B HBT N l E Gcor =G C, HBT N l E 2 Y sopt = G cor Zsopt HBT N le= Gu jb cor =N l E Rn f Teff ' f N le g meff f Teff Z0 f g'meff [ 2 G C, HBT ' G HBT j B HBT RHBT ] gm ' ' r E R b j = Z0 j X sopt 2 g'm ' r E R'b 2 12

13 RF CMOS/HBT LNA design equations F5 0 N f l E ℜ[Z sopt N f l E, f ]=Z 0 coincides with =0 N f l E L S= Z 0 Rs Rg T cascode L S= V Z 0 Rb r E R T cascode [ ft Z IN = T L S Rg Rs j L S L G f gm [ ft Z IN = T L S Rb r E j L S L G f gm ] P ] V L V LG= 2 2 f gm L S C Z =Z in DD G IN o Z =Z 2 f 1 T RP G 4 f 2 Z0 L V SOPT ft DD o L S 13 OUT

14 Refinements for mm-waves: S. Nicolson (CSICS-06) (i) Source Impedance With bondwire Rs= RS=n Z 0 ; M1 Z ZSOPT (M1)= R1 +j/ωc1 LBW 2 PAD 1 L BW CPAD Z C VIN ZO 2 X s =j 2 0 PAD PAD [L BW 1 L BW CPAD Z C ] Cpad CS RS 1 2 L BW CPAD 2 Z C Without bondwire Z0 RS= k Z0 CPAD Z 20 Z S= j k k k =1 2 C2PAD Z VIN

15 Refinements for mm-wave CMOS LNAs: (ii) ft of topology with LM after extraction VDD M2 Csb2 +Cgs2 LM1 M1 Cdb1 +Cgd1 gm1 f T cascode = 2 Cgs1 2 Cgd1 LM1 forms artificial t-line with parasitics of M1 and M2 An optimal LM1 exists that maximized ft. LM1 ~ W 1-1 Both the gain and the noise figure are improved 15

16 (mm-wave) CMOS/HBT LNA design methodology Calculate effective source imp. ZS = R + jxs Find optimal Wf (le) and bias at JOPT VDD CD Find LM1 which maximizes ft of JOPT C1 VOUT VBIAS M C2 CD Find Nf such that JOPT Find LS = R/ T such that R = Re{ZIN} LD LM VIN Find LG such Xs = Imag{ZIN} = Imag{ZSOPT} M LG CPAD LS Design output matching network: LD, CD for maximum gain 16 CPAD

17 Examples: SiGe HBT vs. 90-nm CMOS Cascode LNAs VCC=3.3 V LC= 120 ph 3.58*2 /0.2um LB = 90 ph RFIN LE= 60 ph RFOUT-DIFF RC2 =1 k C C= 23 ff 4.52*2 /0.2um LPRI/SEC= 160 ph 3.58*2 /0.2um 3.58*2 /0.2um LE2 = 60 ph JC1= 4.2 ma JC2= 6.7 ma 370 μm 480 μm 17

18 Single-Transistor Stack Topologies VT VDS Ac-coupled cascode, 1V operation in GP CMOS, insensitive to VT, yet: 2x the DC current 2nd resonant tank reduces bandwidth, extra lossy inductor and MIM cap => higher loss, larger area 18

19 140-GHz 65-nm CMOS LNA 6-stage AC-coupled cascode amplifier 63 mw at 1.2V 20% stage scaling 300 m x 500 m inc. pads [S. Nicolson RFIC-08]

20 Measured S-params and linearity

21 LNA bias network Reference current may come from bandgap circuit Base resistance should not allow for >2mV drop Transistors must be in close proximity in layout. VCE(Q2) should be large for large IIP3 21

22 Bias circuits (ii) VD D VD D LD 1 LD 1 VO U T - LD 1 VO U T + VO U T VD D Q3,4 V+IN LG 1 VD D BIAS L G 1 V_ IN VIN Q1,2 Q3 LG 1 Q1 LS 1 LS 1 LSS2 BIAS 22

23 Bias circuits (iii) 23

24 Differential noise matching Design differential half-circuit to be matched to Z sopt (50Ω) ZsoptdIff = 2Zsopt(Q1) + 2jω(LE + LB) ZINdIff = 2ωΤLE 24

25 Tuned LNA design notes MOSFET LNA design usually compromises noise figure for power dissipation (low-noise current is too high!) In this approach linearity increases with ZO. Pad capacitance and parasitic capacitance of L B reduce input impedance Tail current source in diff-pair adds noise and commonmode instability. Not recommended! 25

26 Tuned LNA topologies summary CS/CE (L or xfmr feedback) low-voltage, low-noise, good linearity, poor isolation => difficult to separately design input/output network CB/CG (no feedback) moderate noise, good isolation (HBT-only) poor linearity, difficult to simultaneously match noise and source impedance Cascode (L or xfmr feedback) best isolation, low-to-moderate noise, easy to match, good linearity higher supply voltage (but available due to mixer) 26

27 Frequency scaling of CMOS LNAs Goal: Scale the LNA centre frequency f 0' = α f 0 Step 1: Biasing for Minimum Noise JOPT 0.15mA/µm Step 2: Device Sizing W F unchanged 130nm 90nm N F' = N F / α W ' = W /α 27

28 Frequency scaling of CMOS LNAs (ii) Step 3: Input Impedance Matching LS: unchanged LG: L'G = LG / α L S= LG = 1 C IN 2 ℜ Z 0 R g R s 2 f T L S Step 4: Output matching L'D = LD / α C1' = C1 / α C2' = C2 / α 28

29 Experimental results LNA Nf Wf um IDS ma VDD [V] 14 GHz, 90-nm GHz, 90-nm GHz, 90-nm LS LG [ph] [ph] LD ph LM ph C1 C2 CPAD [ff] [ff] [ff] 12 GHz, 130-nm GHz, 130-nm

30 Frequency scaling of 90-nm CMOS LNAs Scaling error less than 8% Typical process variation: ~20%! 30

31 Design porting of CMOS LNAs Goal: Keep center frequency unchanged, port LNA to another technology node 130nm Step 1: Biasing for Minimum Noise Unchanged: JOPT is invariant between technology nodes Step 2: Device Sizing 90nm Unchanged: ZO P T is Wf W 'f= S invariant between N ' f = N f S technology nodes W' =W 31

32 Design porting of CMOS LNAs (ii) Step 3: Input Matching LS roughly scaled by 1/fT: L S= Z 0 Rg Rs 2 ft RG + RS remains approximately constant if if W f=> W f/s and W=ct. LS + LG unchanged because transistor size unchanged 32

33 Benefits of scaling for RF/mm-wave Gain and NF improve with scaling 33

34 Power-constrained LNA design VDD RP CD Problem: GHz-range, noise-matched CMOS LNAs consume significant power LD VOUT VDD VIN Solutions Current re-use with CMOS inverter (doubles VDD but still saves power Don't noise match, just bias at Jopt LG Use external capacitor between gate and source: degrades both gain and NF C1 LS ft ft C1 1 Cgs 2 Cg d C1 L S L S 1 Cgs 2 Cg d 34

35 Lossless series-series feedback noise matching scheme LG VIN M1 ZO CPAD VIN LG + LS CIN iin ZO ZS ZIN Z*SOPT CPAD LS ZS VIN ZIN LG + LS RIN = Rg+Rs + ωteff LS CIN iin ZO CPAD ZS Z*SOPT RSOPT = Rg+Rs + k2 f Teff f gmeff Pad capacitance causes second, parallel resonance Series and parallel resonance reduce input impedance matching bandwidth Rsopt/Gsopt is frequency dependent, so noise matching is NOT broadband 35

36 (Lossy) Shunt-series feedback reduces optimal noise impedance VIN GO CPAD VIN Q1 YIN np> ns Y*SOPT YS T1 LP iin GO LS CPAD+ CIN YS YIN GIN gmeff LP M LP VIN iin GO CPAD+ CIN YS Y*SOPT GSOPT Single resonance increases input impedance matching BW Reduces the transistor size & current for noise matching The noise matching is still narrow band because G SOPT is frequency-dependent 36 gmeff f k2 f Teff

37 Ex.: W-Band LNA with xfmr feedback 70pH 64pH 50pH 50pH 80pH 20um 20um 140pH 140pH 20um.. 70pH 30um 20um 105fF 128fF 30um 40um 40pH 60pH 60pH 30um 30um 40um 128fF 63fF 35pH 37

38 Other low-noise amplifier concepts Noise cancellation idea by Bruccoleri et al. ISSCC-02 CG for impedance matching and TIA/ CS for noise matching They don't cancel noise, they achieve noise matching over broader bandwidth LD LD vin VDD VDD VDD M1 RD vout vout RB vout M1 M1 vin -A -A LS ii n M2 M3 VG 38

39 Tuned, narrow-band LNA summary Cascode with inductive degeneration is the most common topology for LNAs Algorithmic design methodology for MOS and HBT LNAs up to 90 GHz In MOSFETs JOPT & ZOPT invariant between nodes CMOS LNA design scalable in frequency and portable between nodes without redesign Frequency scaling error <8% 39

40 Back-up slides 40

41 7.2 Tuned LNA design methodology using a simulator 41

42 Cascode topology with series inductive feedback Good isolation allows for separate input/output matching network design. Bias current is shared resulting in low power. Limited to about 1.8V supply (HBT) or 1.2V supply (LVT MOSFETs) Noise slightly degraded (compared to CE/CS) by common base (gate) device. If common base/gate device is sized for max. speed, NFmin is degraded by a few tenths of db. 42

43 Tuned LNA design steps Set VCE/VDS on transistor to maximize linearity (avoid output clipping as in PA design) Bias minimum NF current density; Size transistor for optimal noise resistance - active device matching; Add passive (inductive) components for optimal noise impedance, input/output impedance and gain - passive device (classical) matching; Add base/gate bias circuitry without impact on noise; If linearity goal is not met (typically because of transfer characteristics) use gain control schemes or increase size or current density (may change input matching) 43

44 Step 1: find the Jopt for the HBT cascode At low-noise bias read ft; use average initial size le=5 µm and 2 emitter, 3base, 2col. HBT ft Jopt 44

45 Step1b: HBT cascode low-noise bias (read J opt) Jopt 45

46 Step-2: cascode sizing for Re(Zsopt)=ZO 46

47 Step 3a: add LE such that Re(ZIN) = ZO LE= ZO Rb RE 2 f T cascode 47

48 Step 3b: add LB such that Im(ZIN, Zsopt) = 0 Z in Z O j L B L E L B 1 j C in 1 L E 2 C in ZSOPT=ZO ZIN=ZO 48

49 Step 3c: add LC for maximum gain LC should be as large as possible for gain CC helps lower impedance May use 3-terminal inductor or transformer for impedance transform to ZO Linearity is maximized by setting: RCTankx Icopt = VCE(Q2) VCESAT RCTank is the equiv. parallel ac resistance at the output node 49

50 Step 3d: matching the output Use the Smith chart with the series-shunt or shuntseries technique Make sure not to short-ckt. the output to ground (use shunt inductor to VCC not to GND. Use 2pF... 5pF (depending on LNA freq) to de-couple cascode bias and VCC to AC ground. 2 f 1 T RP G 2 4 f Z in 50