THE rapid evolution of wireless communications has resulted

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1 368 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004 Brief Papers A 24-GHz CMOS Front-End Xiang Guan, Student Member, IEEE, and Ali Hajimiri, Member, IEEE Abstract This paper reports the first 24-GHz CMOS front-end in a m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 db and an overall noise figure of 7.7 db with an input return loss, S 11 of 21 db consuming 20 ma from a 1.5-V supply. The LNA achieves a power gain of 15 db and a noise figure of 6 db on 16 ma of dc current. The LNA s input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy. Index Terms CMOS analog integrated circuits, integrated circuits noise, receiver front-ends, RF amplifiers, wireless communications. I. INTRODUCTION THE rapid evolution of wireless communications has resulted in a strong drive toward building high-performance RF circuits in silicon, particularly CMOS, for its low cost and high level of integration. Meanwhile, the growing demand for larger bandwidth motivates integrated circuits to move toward higher frequencies. Recent works have shown CMOS as a promising medium for building RF circuits in the low-gigahertz range [1] [4]. However, a high-performance CMOS front-end for applications above 20 GHz has not been reported to date. These high frequencies provide higher available bandwidth and make it possible to use small-sized phased array antennas [5] for beam forming [6], [7] and space-time coding [8]. The purpose of this work is to develop a CMOS receiver front-end (LNA mixer) operating at frequencies above 20 GHz (i.e., 24-GHz industrial, scientific, and medical (ISM) band). A simplified block diagram of a typical receiver is shown in Fig. 1. In this architecture, the RF amplification and downconversion stages are the most critical to the system noise performance and the most challenging to implement in CMOS. This work reports the design and implementation of a 24-GHz CMOS front-end. Section II presents a novel low-noise amplifier (LNA) topology, common-gate with resistive feedthrough. Section III describes the circuit design and implementation of the front-end in detail. The experimental results are shown and discussed in Section IV. Manuscript received April 4, 2003; revised September 26, The authors are with the California Institute of Technology, Pasadena, CA USA ( xiangg@caltech.edu). Digital Object Identifier /JSSC Fig GHz receiver. II. LNA ANALYSIS Lower intrinsic gain of transistors makes it more difficult to achieve low noise figure (NF) at very high frequencies. Additional noise sources, such as gate-induced noise, become more prominent with increasing frequency. Therefore, it is necessary to re-evaluate the topologies used for such LNAs. A. Common-Source and Common-Gate LNAs The common-source stage with inductive degeneration has been commonly used in CMOS LNA implementations [1] [3], [10] [15]. Extended analysis of this topology has been given in many previous publications [13], [14]. It can be shown that for an input-matched common-source LNA, the minimum achievable noise factor,, and the effective transconductance,, are linearly related to the working frequency, and, respectively [13]. Therefore, although this common-source topology is well suited for applications at low-gigahertz range, its performance degrades substantially at higher frequencies when becomes comparable to [9], [15]. In contrast, in the common-gate (CG) LNA, the gate-source and gate-drain parasitic capacitances of the transistor are absorbed into the LC tank and resonated out at operation frequency. Therefore, to the first order, the noise and gain performance of the common-gate stage are independent of the operation frequency, which is a desirable feature for high-frequency design. However, due to the constraints of input matching, it can be shown that the noise factor of the CG LNA has a lower bound of for perfect input match, where is the channel thermal noise coefficient. In the following subsection, a resistive feedthrough technique is proposed to bring the noise factor of common-gate LNA to a significantly lower level. B. Common-Gate With Resistive Feedthrough LNA Most analysis on CG LNA assumes the transistor output resistance is infinite. It was first noted in [16] that a finite of the input transistor increases input resistance and can be used /04$ IEEE

2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY effect of these terms later. The feedthrough resistor, which is formed by in parallel with, creates a positive feedback loop around the amplifier to enhance the input impedance. Analysis of the circuit in Fig. 2(b) shows that at resonance frequency, the input impedance seen looking into the source of can be expressed as where is the transistor transconductance, is the ratio of the transistor backgate transconductance to, and. If input is matched, the effective transconductance of CGRF stage is given by (1) (2) (a) which indicates that to the first order at input matching condition the gain of CGRF stage is independent of and. Assuming a matched input and, it can be shown that the output noise power generated by the thermal noise of and is negligible compared to that generated by the transistor channel thermal noise, and the noise factor can thus be approximately expressed as (3) (b) Fig. 2. Common-gate with resistive feedthrough LNA. (a) Schematic. (b) Small-signal equivalent circuits. to build CG LNA with noise factor lower than the bound of. The transistor output resistance depends on the channel length and bias current, so the designer cannot control its value freely. We can add an external resistor,, to the traditional CG LNA in parallel with the input transistor to improve its noise performance, as Fig. 2(a) shows. We call this topology common-gate with resistive feedthrough (CGRF) LNA. A detailed analysis of this stage is given next. In Fig. 2(a), is the signal source impedance, is a large capacitor for isolating dc level, and is the resistive load at the drain of owing to the finite quality factor of the resonant load. Inductors and resonate at operation frequency with capacitive load at drain and source of, respectively. The small-signal equivalent circuit of the CGRF LNA at operation frequency is shown in Fig. 2(b), including the major noise sources, where is the transistor transconductance, is the backgate transconductance, is the real part of the gate admittance [17], is the transistor channel thermal noise source, and is the induced gate noise source [17]. The analysis starts with the study of the circuits at low frequency, where and can be neglected. We will include the where is the ratio of to the channel conductance at zero drain-to-source voltage. Based on the simplifying assumptions that ignore gate noise and, it may appear that the noise of CGRF amplifier can approach 0 db by increasing, providing a direct way to trade between power and noise while keeping the input matched [9]. However, at high frequencies, we should include the effect that the coupling between channel and gate is due to a distributed RC network, reflected in the real part of the gate admittance,. In the pinch-off region, is related to operation frequency, gate-source capacitor, and through [13], [17] This conductance has a thermal noise associated with it, which is called induced gate noise. The power spectral density of is given by [17] where is the gate noise coefficient. and are partially correlated with a complex correlation coefficient given by Taking into account, the input impedance of CGRF stage is revised as where is defined as the ratio between and, i.e., (4) (5) (6) (7) (8)

3 370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004 If input is perfectly matched to, the effective transconductance of the CGRF stage is given by (9) which indicates that a large or high frequency can degrade the gain. This is because an increase of or frequency results in a larger, making more signal loss through the gate. Assuming a matched input and yields the following expression for : Fig. 3. Reducing substrate coupling by using parallel inductor. (10) where the second term represents the contribution of channel thermal noise and the third term represents the contribution of induced gate noise. At low frequencies,, (10) reduces to (3). It can be shown that an optimum exists for minimum noise figure, i.e., The corresponding minimum (11) is approximately given by (a) (12) C. Stability Since in the CGRF stage, results in positive feedback, the stability issue needs to be carefully addressed. Considering the input transistor with feedthrough resistor in Fig. 2(a) as a two-port network, and are the load impedance at the two ports, source and drain, respectively. It is a sufficient condition to prevent oscillation that the real part of both impedance seen looking into the ports and are positive. It is easy to shown that and can be expressed as where and is guaranteed. (13) (14), and (13) and (14) indicate that as long as are positive, the stability of the CGRF stage III. CIRCUIT DESIGN AND LAYOUT ISSUES A. 24-GHz LNA The analysis in the previous section ignores all the substrate effects. However, at 24 GHz, capacitive coupling and resistive loss through substrate have considerable influence on the circuit performance. A simplified substrate network model for MOS transistor is shown in Fig. 3 [18]. Simulation results show the Fig. 4. (b) Building blocks. (a) Three-stage LNA. (b) Downconversion mixer. capacitive coupling between drain and source through this network harms stability and noise figure. A shunt inductor in series with a large bypass capacitor can be added, as shown in Fig. 3, to resonate the equivalent capacitance between drain and source so that the substrate effects are reduced. The series resistance of can be converted to an equivalent parallel resistance, which affects the performance of the LNA as a feedthrough resistor. In this case, the feedthrough resistance can be expressed as (15) where is the quality factor of. Fig. 4(a) shows the 24-GHz CMOS LNA. It consists of three stages. The first stage employs CGRF topology, where shunt inductor resonates the capacitive coupling while introduces a feedthrough resistance given by (15) between drain and source

4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY of. A 1-pF MIM capacitor isolates the dc level of source and drain. The second and third stages are both common-source with inductive degeneration amplifiers which are used to enhance the overall gain. The peak of the m CMOS device used at 1.5 V bias is about 60 GHz. To achieve the minimum noise figure at 24 GHz, the optimum is estimated to be about 80 ms by using (11). To reduce the power consumption, we choose to be 40 ms in this design. We also lower by a factor of two from its value for peak, which is a more power-efficient way reducing current consumption by more than 50%, while reducing by only about 10%. Finally, is biased at 8 ma with 54-GHz. The second and third stages consume 4 ma each. Since the feedthrough resistor is replaced by an inductor in the first stage in Fig. 4(a), the stability of the amplifier needs to be reexamined. Simulation shows that the first stage is unconditionally stable up to 43 GHz. Above 43 GHz, the stability factor of the stage is less than one. However, the input impedance of the second stage is located in the stable region with sufficient margin. Stable operation in all frequency ranges is observed in both simulation and measurement. Fig. 5. Die micrograph. TABLE I PERFORMANCE SUMMARY OF THE 24-GHz FRONT-END B. 24-GHz to 5-GHz Mixer The core of the mixer shown in Fig. 4(b) is a conventional single-balanced Gilbert-type mixer. The RF input applies at the gate of which is used as a transconductance amplifier. The linearity of this transconductance amplifier is improved by using source degeneration inductor, which also adjusts the input impedance seen looking into the gate of in order to improve the impedance matching at the LNA-mixer interface. The is biased at 4-mA dc current. The chopping function is accomplished by the mixing cell, and 1.6-V peak-to-peak differential local oscillator (LO) signal is applied. Cascode amplifiers following the differential mixing cell are used to drive the 50- loads. The outputmatch is accomplished by the LC impedance transforming network. C. Layout Issues The circuit has been designed and fabricated using m CMOS transistors. The process offers six metal layers with two top layers of 1- m-thick copper. and in the LNA and in the mixer are slab inductors, and all the other inductors are spirals. Shielded pads [19] are employed at both RF and IF ports. Grounded metal1 underneath the pads prevents loss of the signal power and noise generation associated with the substrate resistance. Ground rings are placed around each transistor at minimum distance to reduce the substrate loss. Separated pads are assigned to the LNA, mixer, and bias circuits. Large on-chip bypass capacitors are placed between each and ground. The die micrograph is shown in Fig. 5. The size of the chip is mm including a large area occupied by the wide ground rings and pads. The size of the core cell is only mm. IV. EXPERIMENTAL RESULTS The front-end is tested by probing the input, output, and LO ports. The power and ground pads are wirebonded to the testing board. The reflection coefficients at the RF and IF ports are measured using an HP 8722D network analyzer. Conversion gain and noise figure are measured using an HP 8970B noise figure meter with an HP 8971 noise figure test set as a second downconverter. Table I summarizes the measured results of the front-end and the de-embedded performance of the LNA and the mixer. Fig. 6(a) shows the measured input and output reflection coefficients, and. The RF input and the IF output are well matched at their respective frequencies. Fig. 6(b) shows the measured power gain and extracted voltage gain with a 16.9-GHz LO frequency. The measurement shows that a 27.5 db maximum power gain appears for an RF of 21.8 GHz and an IF of 4.9 GHz. The frequency offset from the 24 GHz is likely due to inaccurate modeling of MOS transistor and planar inductor at high frequencies. The LNA achieves a 15-dB power gain. The mixer followed further enhances the signal power by 13 db. Because of the imperfect conjugate matching at the LNA mixer interface, the overall power gain

5 372 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 2, FEBRUARY 2004 (a) (b) (c) (d) Fig. 6. Front-end measurement results. (a) Reflection coefficients. (b) Power gain and voltage gain (LO = 16:9 GHz). (c) Large-signal nonlinearity. (d) Total noise figure of three-stage LNA + mixer (LO = 16:9 GHz). TABLE II COMPARISON of the front-end is slightly lower than the sum of the individual power gain of the two blocks. Fig. 6(c) and (d) reports the measured large-signal nonlinearity and noise figure, respectively. The input-referred 1-dB compression point of the front-end appears at 23 dbm. A minimum noise figure of 7.7 db is achieved for the combined LNA and mixer at GHz. The individual noise figures of the LNA and the mixer are 6 db and 17.5 db, respectively. The noise figure of the first CGRF stage is extracted to be 4.8 db. Equation (3) predicts the only noise figure of the first stage to be 3.3 db. Equation (10) revises the prediction of the noise figure to be 4.1 db by taking and into account; the remaining 0.7 db is due to the thermal noise of the parasitic resistance and substrate noise. The image rejection of the front-end is 31 db. This performance is achieved via the large IF and the multistage nature of the LNA. The overall current consumption of the front-end is 43 ma, of which the output buffers consume 23 ma. The LNA and the mixer draw 16 and 4 ma, respectively, from a 1.5-V supply voltage. A comparison of the LNA in this work and the one in [15] and [20] is given in Table II. V. CONCLUSION The design issues and experimental results of a 24-GHz CMOS front-end are presented. A novel LNA topology, common-gate with resistive feedthrough, is studied and demonstrated with good performance at very high frequencies. The theoretical analysis of the LNA topology explains the experimental results. This work shows that CMOS technology is a viable candidate for building fully integrated receivers at frequencies higher than 20 GHz. ACKNOWLEDGMENT The authors would like to thank Jazz Semiconductor Inc. for fabrication of the front-end. They are grateful for the support of Lee Center, NSF-ERC, and NSF. They are especially grateful for the help and advice of M. Racanelli, S. Stetson, A. Karroy,

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