Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits

Transcription

1 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 1/27 Class-AB Single-Stage OpAmp for Low-Power Switched-Capacitor Circuits S. Sutula 1, M. Dei 1, L. Terés 1,2 and F. Serra-Graells 1,2 1 Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) 2 Dept. of Microelectronics and Electronic Systems (DEMISE) Universitat Autònoma de Barcelona (UAB) Lisbon, May 2015

2 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 2/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

3 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 3/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

4 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 4/27 Low-Power Switched-Capacitor Design Low-Voltage Approach Low-Current Approach Bulk-driven OpAmps Internal supply multipliers Inverter-based OpAmps Switched OpAmps Telescopic diff. pairs with LCMFB Dynamic biasing by RC bias tees Hybrid-Class-A/AB Adaptive biasing Nominal-voltage downscaling Moderate power savings Higher power savings Parameter-variation sensitivity

5 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 5/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

6 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 6/27 Single-Stage Class-AB OpAmp Two complementary diff. pairs Dynamic current mirrors Separate Class-AB control Partial positive feedback CMFB control through the NMOS-pair tail Gain improvement by the output cascode transistors No need for the Miller compensation capacitors High-peak Class-AB currents only in the output transistors

7 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 7/27 Single-Stage Class-AB OpAmp Supposing all boxed devices operating in strong inversion: I onp D D =. AB A + B = I inp A + nβ 2 Vcp Desired Class-AB behavior: I outp 0 V cp V xp I onp I inp I outp 0 V cp V xp { Ionp I inp I onp I inp

8 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 8/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

9 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 9/27 Type I I inp =B ( 2 Ionn D +C( 2Itail D ( Ionp D Ionp Iinp D + A Ionp D Ionn D Ionn D Iinp A + Iinn A )( Ionp ) Iinp D A ) Iinp + A + Iinn A ) Cross-coupled pair for the Class-AB operation Crossing transistor as a Class-AB limiter Independence from the technology parameters Need for an extra bias reference

10 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 10/27 Type I with Class-AB Smoother Low-level common-mode current injection Instability prevention under a high Class-AB modulation Need for extra current sources

11 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 11/27 Type II [ ( I inp = 2 B ) Ionn Ionp D +C D (B+C)( Ionp Iinp D A )]( Ionp ) Iinp D A D =. A(B+C) I A+B+C max 1+ A C I 1+ B+C A tail > I tail Independence from the technology parameters Auto-biased Class-AB limiter Self-latch prevention Simple sizing procedure

12 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 12/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

13 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 13/27 Type-II OpAmp Using a 0.18-µm CMOS Technology Circuit design based on the inversion-coefficient Reduced set of transistor matching groups Minimum-channel-length devices can be used Bias for cascode transistors optimized for maximum output full scale 1.8-V nominal voltage supply of the CMOS technology

14 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 14/27 Simulation Results DC transfer curve 10 Analytical Numerical Analytical versus numerical behavior 8 6 Class-AB achieves about 4 bias current [ma] 4 I onn I onp I inp I inn [ma]

15 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 15/27 Simulation Results Frequency response 200-pF load capacitance Differential Gain [db] db 50 Phase Gain Phase [ ] Frequency [Hz]

16 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 16/27 Simulation Results Step response for several load conditions Differential Output Voltage [V] µf at 1 Hz, 650 nf at 1 khz 650 pf at 1 MHz Time Input Frequency [-] Stability robustness

17 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 17/27 Integration Standard 0.18-µm 1P6M CMOS technology 0.07-mm 2 area Additional CMFB averaging capacitors for SC applications

18 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 18/27 Integration Standard 0.18-µm 1P6M CMOS technology 0.07-mm 2 area Additional CMFB averaging capacitors for SC applications

19 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 19/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

20 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 20/27 Step Response Current [ma] Diff. Output Voltage [V] Simulated Measured I opp I supply I opn Time [ms]

21 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 21/27 Full-Scale Evaluation Differential Output Voltage [V] Time [ms] Ideal Simulated Measured 3.3-V pp differential full scale at 1.8-V voltage supply

22 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 22/27 Figure-of-Merit Comparison Parameter [1] [2] [3] [4] [5] This work Units Technology µm Supply V DC gain db C load pf GBW MHz Phase margin 89.5 N/A Slew rate, SR V/µs Static power, P mw Area N/A mm 2 V pf FOM µs µw FOM = SR C load P [ ] V pf µs µw

23 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 23/27 1 Introduction 2 Class-AB Architecture 3 Process-Independent Circuits 4 Practical Design 5 Experimental Results 6 Conclusions

24 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 24/27 Conclusions New family of Class-AB OpAmps Single-stage topology No need for an internal frequency compensation Class-AB current peaks in the output transistors only Low sensitivity to the technology parameter variations Simple analytical design flow Successfully used in a 16-bit 100-kS/s ΔΣ ADC Thank you!

25 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 25/27 References [1] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency, IEEE Journal of Solid-State Circuits, vol. 40, pp , [2] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan, and A. Lopez-Martin, A Free But Efficient Low-Voltage Class-AB Two-Stage Operational Amplifier, IEEE Transactions on Circuits and Systems II: Expressed Briefs, vol. 53, pp , [3] M. Yavary and O. Shoaei, Very Low-Voltage, Low-Power and Fast-Settling OTA for Switched-Capacitor Applications, in Proceedings of the International Conference on Microelectronics, 2002, pp [4] M. Figueiredo, R. Santos-Tavares, E. Santin, J. Ferreira, G. Evans, and J. Goes, A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, pp , [5] M. R. Valero, S. Celma, N. Medrano, B. Calvo, and C. Azcona, An Ultra Low-Power Low-Voltage Class AB CMOS Fully Differential OpAmp, in Proceedings of the IEEE International Symposium on Circuits and Systems, 2012, pp

26 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 26/27 Normalized Current Transfer Curve for Different B/C Ratios

27 IEEE ISCAS 2015 Intro Architecture Circuits Design Results Conclusions 27/27 Normalized Current Transfer Curve Under Corners for B/C=3 4 3 typical at 20 C fast at -40 C slow at 80 C 2 2 Ionn I tail 2 Ionp I tail (I inp I inn ) /I tail