# LOW-VOLTAGE operation and optimized power-to-performance

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3 1070 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 so an increase of is achieved compared to the OTA of Fig. 1(a) with. The phase margin as a function of is given by for V is negative, and the large positive swing at node yields a large current in, given by (2) (6) whereas current in is lower than and negligible. In this case. Thus, a general expression for the output current when Vis This formula allows estimation of the maximum value for that can be employed for a given phase margin and load capacitance.if is too large the OTA of Fig. 1(b) behaves like a two-stage topology and Miller compensation is required. Fortunately, it is not necessary to use large values of to achieve very high slew rates in our proposed OTAs, as will be illustrated in Section II-B, thus enforcing enough phase margin. B. Large-Signal Analysis When no differential input is present in the OTA of Fig. 1(b), currents and generated by the input differential pair are identical and equal to the very small quiescent current provided by the adaptive bias circuit, and no current flows through and. Assuming operation in strong inversion and saturation, voltages at nodes,, and are given in this case by where and are the threshold voltage and transconductance factor, respectively, of transistors and. However, upon application of a differential input signal, a differential current is created, which neglecting channel-length modulation in and leads to a current in the resistors. Current through and will be the common-mode current. Therefore, nodal voltages will be Hence, a large positive voltage swing takes place at node for V. Assuming operation in strong inversion and saturation for, it leads to a current in (5) whereas the large negative swing at node strongly decreases current through transistor below quiescent current. Thus, the output current is. In a similar manner, (3) (4) where when and when. Current efficiency is approximately given by, where is given by (7). Since under dynamic conditions, current efficiency approaches the ideal value of 1, whereas in the conventional OTA of Fig. 1(a) and in previous class AB OTAs with it is 0.5 or less [7]. This is because using LCMFB the large dynamic currents are generated directly in the output branches, without internal replication. A drawback of LCMFB is that independence of current multiplication with absolute process variations, typical of current mirrors, is lost as the expressions above reflect. This is not critical since the exact maximum output current obtained is not very important provided it is high enough to achieve a given settling time. However, process tolerances must be considered at the design stage in order to reach specifications within reasonable safety margins. LCMFB has been employed in the past combined with conventional class A differential pairs to achieve class AB amplifiers [8]. In this case the maximum differential current of the input pair is twice the quiescent current, i.e., where the tail current is chosen very small to achieve low static power dissipation. From (7), this implies that large feedback resistors should be utilized to achieve enough current boosting, which is incompatible with large phase margin. Thus limited current boosting is provided as low enough values for must be chosen to enforce stability. This limitation explains why the reported slew rate increase factor in [8] versus the conventional OTA is just 3. Potentials of the LCMFB technique for design of class AB amplifiers can only be fully exploited using a class AB differential input stage, as we propose here and show in Fig. 1(b). In this case, current boosting at the input stage may lead to a differential current in (7) much larger than the quiescent current, and therefore a very large current boosting can be achieved in the output current for low values of, simultaneously preserving phase margin and static power dissipation. Dynamic current boosting takes place not only in the differential pair, but also in its active load due to the LCMFB technique. For typical class AB CMOS input stages, the differential current generated is proportional to and so is the output current [4], [7]. From (7), including LCMFB the output current will be proportional to and therefore to, clearly outperforming previously reported CMOS (7)

4 LÓPEZ-MARTÍN et al.: LOW-VOLTAGE SUPER CLASS AB CMOS OTA CELLS WITH VERY HIGH SLEW RATE AND POWER EFFICIENCY 1071 Followers (FVFs) [12]. They have a very low output resistance (typically in the range ), and fulfill the aforementioned requirements. Quiescent current in and is the well-controlled bias current of the FVFs assuming that transistors,, and are matched. In this case, for large currents and are (8) Fig. 2. Adaptive biasing topologies. Using two level shifters: (a) diagram; (b) circuit. Using CMS: (c) diagram; (d) circuit. Using WTA: (e) diagram; (f) circuit. class AB OTA topologies. Hence, the resulting circuits can be coined as super class AB OTAs [10]. III. SUPER CLASS AB OTAS Different super class AB OTA topologies can be obtained using different adaptive biasing techniques for the input differential pair in the general diagram of Fig. 1(b). Fig. 2 shows three alternatives to implement these input stages, suited to lowvoltage operation. The resulting OTAs are shown in Fig. 3. A. Super Class AB OTA With Cross-Coupled Floating Batteries The scheme of Fig. 2(a) [10], [11] consists of two matched transistors and cross-coupled by two dc level shifters. Under quiescent conditions, so transistors and carry equal quiescent currents controlled by.if is slightly larger than, very low standby currents can be achieved. However, for instance when decreases voltage at the source of decreases by the same amount whereas the source voltage of stays constant. Therefore, current through increases whereas current through decreases. The maximum value of these currents can be much larger than the quiescent current. Very low output impedance dc level shifters are required in order to drive the low-impedance source terminals of transistors and. The dc level shifters must also be able to source large currents when the circuit is charging or discharging a large load capacitance. Moreover, they should be simple due to noise, speed, and supply restrictions. A very good choice is shown in Fig. 2(b) [10], [11]. Each level shifter is built using two transistors (, and, ) and a current source. We name these level shifters Flipped Voltage Although when both and operate in strong inversion and saturation (i.e., for low values), due to the small value of chosen the input transistor with the lowest is soon driven, and dependence of becomes quadratic. In this case the differential current and common-mode current out of strong inversion for not very large on are and for large positive whereas and for large negative. From (8), currents and are not bounded by, showing the class AB operation of the circuit. The common-mode output current is signal-dependent, another characteristic of class AB topologies. The ac small-signal differential current of the input stage is (9) Since the ac input signal is applied to both the gate and the source terminals of and, the transconductance of this input stage is twice that of a conventional differential pair. Fig. 3(a) shows the super class AB OTA obtained using the adaptive bias circuit of Fig. 2(b) in the scheme of Fig. 1(b). For large and positive, from (8) and. For large negative,, and. Using (7), the output current in Fig. 3(a) is given by (10) where the sign of corresponds to the polarity of.itis clear that for a large the output current increases with, enhancing quadratically the current boosting provided by the class AB input stage. The GBW of the OTA is given by (1) with. An increase factor appears in the dc gain compared to the conventional OTA of Fig. 1(a), which translates to the same increase in GBW. The factor is due to the LCMFB technique, and the additional factor 2 is due to the doubled transconductance of the input stage. The minimum supply voltage of the circuit is where is the minimum for operation in saturation. For V and V it yields 1.3 V. The common-mode input voltage is similar to that of the conventional class A OTA of Fig. 1(a). Therefore the circuit is suitable for low-voltage operation. Other approaches based on

5 1072 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 source-coupled nmos and pmos transistors [4] require a minimum supply voltage of. Note, however, that the FVF cell is suited to low supply voltages only, as the drain voltage of is, which can make enter triode region if is large enough. For high supply voltages, a source follower can be included in the FVF loop acting as a dc level shifter to solve this issue [12]. Transistors and in the FVF cells provide shunt feedback, and the FVF cell forms a two-pole negative feedback loop. Stability of the FVF cell can be readily enforced by proper sizing of transistors to ensure the condition, where and are the parasitic capacitances at the source and drain, respectively, of. FVF load capacitance is included in. For large FVF capacitive loads the inclusion of a grounded compensation capacitor at the drains of and could be necessary to increase. B. Super Class AB OTA With Pseudodifferential Pair An alternative class AB input stage is shown in Fig. 2(c)[13], [14]. Voltage at the common-source node of the input differential pair is set to the input common-mode voltage shifted by. Under quiescent conditions, and voltage controls the quiescent currents like in Fig. 2(a). When a differential input is applied, an unbalance in the drain current is produced that is not limited by the quiescent current. A very efficient implementation of the dc level shifter is again the FVF, and the resulting circuit is shown in Fig. 2(d). In this case and the FVF bias current is the quiescent current of the input differential pair, assuming matched transistors,, and. Currents and are given by (11) As in Fig. 2(b), output currents increase quadratically with and are not limited by. A circuit, labeled CMS in Fig. 2(c), is required to sense the common-mode input voltage and to apply it to the gate of transistor, in order to make quiescent currents independent of the input common-mode voltage, and thus to obtain a high common-mode rejection ratio (CMRR). Fig. 3(c) and (d) shows two implementations of Fig. 1(b) using the circuit of Fig. 2(d) with different common-mode sensing techniques. In both cases the common-mode voltage is sensed by applying the input voltage to a resistive divider through two FVF buffers, thus exploiting the benefits already mentioned of the FVF cell. Voltage at node A is. In Fig. 3(c), a down-shifting is applied to obtain at the gate of. Noting that and lead to complementary dc level shifts, an alternative approach is shown in Fig. 3(d) where these transistors are removed, and a simple buffer is employed. The amplifier used in Fig. 3(d) is a simple nmos differential pair with active load. An alternative and very compact approach not discussed here for sensing of input common-mode level is based on the use of floating-gate transistors [15]. Both in Fig. 3(c) and (d), differential and common-mode currents flowing out of the input pair are and for large positive, and and for large negative. Therefore, using (11) and (7) the output current is (12) where the sign of corresponds to the polarity of. Like for the OTA of Fig. 3(a), the output current increases with, enhancing quadratically the current boosting provided by the class AB input stage. However, comparing (12) and (10) a lower current boosting is predicted for the topologies of Fig. 3(c) and (d) compared to Fig. 3(a) for identical transistor dimensions and quiescent currents, due to the factor 2 that divides in (11). The small-signal transconductance of the input stage is also half that of Fig. 3(a), i.e., like the conventional class A OTA, since the ac input signal is only applied to the gate of the input transistors and their source is an ac virtual ground. Thus for fully differential inputs the ac small-signal of the input transistors is half the differential ac input swing. Therefore, the GBW of the OTA is given by (1) with. Only the increase factor in the dc gain due to the use of LCMFB appears compared to the conventional OTA of Fig. 1(a), which translates to the same increase in. Supply voltage requirements and common-mode input range are the same as for Fig. 3(a), allowing low-voltage operation. C. Super Class AB OTA With WTA Input Stage Fig. 2(e) shows a modification proposed here of the idea in Fig. 2(c), where a Winner-Take-All (WTA) circuit replaces the common-mode sensing circuit. The output of the WTA circuit is the maximum (the winner ) of the input voltages. Therefore, voltage at the common-source node of the differential pair is the maximum input voltage shifted by the constant voltage. Under quiescent conditions, input voltages are equal, and their maximum value corresponds to the common-mode input voltage. Thus, and quiescent currents are well controlled and determined by like in the circuits of Fig. 2(a) and (c). The difference arises under dynamic conditions. If for instance the input voltage decreases so that it is lower that, the common-source node tracks the maximum input voltage, i.e.,, and not the common-mode voltage of the inputs. Therefore, the resulting is larger than that obtained for the same input in Fig. 2(c), and a larger dynamic current boosting is achieved. A related strategy which uses a Minimum circuit was reported in [7]. However, two additional amplifiers in negative feedback configuration are required, complicating the design. Here only four transistors are utilized to achieve the Maximum operator. Fig. 2(f) shows a very efficient implementation of the WTA circuit. The basic cell employed is once more a FVF cell thus benefiting from its large sourcing capability, low output impedance and low-voltage operation. It will be assumed that transistors,, and are matched. In this case,

6 LÓPEZ-MARTÍN et al.: LOW-VOLTAGE SUPER CLASS AB CMOS OTA CELLS WITH VERY HIGH SLEW RATE AND POWER EFFICIENCY 1073 Fig. 3. Super class AB OTAs. (a) Based on Fig. 2(b). (b) Based on Fig. 2(f). (c), (d) Based on Fig. 2(d). under quiescent conditions, and voltage at node is, yielding again a quiescent current. If for instance decreases, increases so the drain voltage of increases, driving into triode region. In this situation voltage at node is set by, the dimensions of, and current, i.e.,. Accordingly, when decreases below, enters triode region and. Hence, for V,, and currents and are In a similar way, when V,,, and currents and are (13a) (13b) Therefore, the same maximum currents as in (8) are generated. Again and may be significantly larger than. The ac small-signal differential current of the input stage is, like for the OTAs of Figs. 1(a) and 3(c) and (d). This is because, although under large-signal conditions the largest of the input transistors is due the WTA circuit, for a fully balanced ac small-signal input the node is an ac virtual ground and. Fig. 3(b) shows the super class AB OTAs obtained employing the adaptive bias circuit of Fig. 2(f) in the scheme of Fig. 1(b). The maximum output current is the same as for the OTA of Fig. 3(a), given by (10). Since, the predicted dc gain is like for the OTAs of Section III-B, and also GBW is given by (1) with. The requirements in terms of supply voltage and the input common-mode range are identical than for the OTA of Fig. 3(a) and the conventional class A OTA of Fig. 1(a). D. Comparison of the Super Class AB OTAS The differences among the OTAs of Fig. 3 are due to the different class AB input stages employed. All the OTAs achieve a current boosting proportional to, clearly outperforming previous approaches. However, the topologies of Fig. 3(a) and (b) achieve the maximum output current for a certain, given by (10) and identical in both cases. The OTAs of Fig. 3(c) and (d) yield a lower output current for the same, as can be de-

9 1076 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 TABLE I MEASURED PERFORMANCE PARAMETERS OF THE OTAS V. CONCLUSION A novel family of CMOS class AB OTAs, based on the combined use of adaptive biasing and local common-mode feedback, has been fabricated and tested. The technique employed leads to a significant increase in slew rate and fast settling, improving current efficiency and maintaining low noise and very low static power consumption. The principle proposed is completely general and can be extended to virtually any class AB input stage by properly including LCMFB. Various topologies have been presented and implemented in a 0.5- m CMOS technology, achieving near-optimal current efficiency, increasing slew rate by more than two orders of magnitude, and increasing GBW up to a factor 3.6 compared to the conventional OTA with the same dimensions and quiescent currents. Among them, as theoretically predicted in Section III-D and experimentally verified from Table I, the circuit of Fig. 3(a) shows the best overall performance, in terms of slew rate, GBW, and settling time. The circuits proposed can find application in low-voltage low-power switched-capacitor circuits and in buffers for testing mixed-signal circuits. [7] R. Harjani, R. Heineke, and F. Wang, An integrated low-voltage class AB CMOS OTA, IEEE J. Solid-State Circuits, vol. 34, no. 2, pp , Feb [8] J. Ramirez-Angulo and M. Holmes, Simple technique using local CMFB to enhance slew rate and bandwidth of one-stage CMOS op-amps, Electron. Lett., vol. 38, pp , Nov [9] B. Razhavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001, pp [10] S. Baswa, A. J. Lopez-Martin, J. Ramirez-Angulo, and R. G. Carvajal, Low-voltage micropower super class AB CMOS OTA, Electron. Lett., vol. 40, pp , Feb [11] V. Peluso, P. Vancorenland, M. Steyaert, and W. Sansen, 900 mv differential class AB OTA for switched opamp applications, Electron. Lett., vol. 33, pp , Aug [12] J. Ramirez-Angulo, R. G. Carvajal, A. Torralba, J. Galan, A. P. Vega- Leal, and J. Tombs, The flipped voltage follower: A useful cell for low-voltage low-power circuit design, in Proc. Int. Symp. Circuits and Systems, 2002, pp. II 615 II 618. [13] S. Baswa, A. J. Lopez-Martin, R. G. Carvajal, and J. Ramirez-Angulo, Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers, Electron. Lett., vol. 40, pp , Feb [14] J. Ramirez-Angulo, R. Gonzalez-Carvajal, A. Torralba, and C. Nieva, A new class AB differential input stage for implementation of low voltage high slew rate op-amps and linear transconductors, in Proc. Int. Symp. Circuits and Systems, 2001, pp. I 671 I 674. [15] J. Ramírez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, Lowvoltage CMOS op-amp with rail-to-rail input and output for continuous-time signal processing using multiple-input floating-gate transistors, IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp , Jan REFERENCES [1] K. de Langen and J. H. Huijsing, Compact low-voltage power-efficient operational amplifier cells for VLSI, IEEE J. Solid-State Circuits, vol. 33, no. 10, pp , Oct [2] M. Degrauwe, J. Rijmenants, E. A. Vittoz, and D. Man, Adaptive biasing CMOS amplifier, IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp , Jun [3] L. Callewaert and W. Sansen, Class AB CMOS amplifiers with high efficiency, IEEE J. Solid-State Circuits, vol. 25, no. 6, pp , Jun [4] R. Castello and P. R. Gray, A high-performance micropower switchedcapacitor filter, IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp , Dec [5] S. L. Wong and C. A. T. Salama, An efficient CMOS buffer for driving large capacitive loads, IEEE J. Solid-State Circuits, vol. SC-21, no. 3, pp , Jun [6] R. Kline, B. J. Hosticka, and H. J. Pfleiderer, A very-high-slew-rate CMOS operational amplifier, IEEE J. Solid-State Circuits, vol. 24, no. 3, pp , Jun Antonio J. López-Martín (M 04) was born in Pamplona, Spain, in He received the M.S. and Ph.D. degrees (with honors) in electrical engineering from the Public University of Navarra, Pamplona, Spain, in 1995 and 1999, respectively. He has been with the New Mexico State University, Las Cruces, and with the Swiss Federal Institute of Technology, Zurich, Switzerland, as a Visiting Professor and Invited Researcher, respectively. Currently, he is an Associate Professor with the Public University of Navarra, and Adjunct Professor with the New Mexico State University. He has authored or co-authored a book, various book chapters, over 50 journal papers and 70 conference presentations. He also holds two international patents, and leads research projects funded by public institutions and local companies. His research interests include low-voltage analog and mixed-mode integrated circuits, integrated sensor interfaces, analog and digital signal processing, and communication systems.

10 LÓPEZ-MARTÍN et al.: LOW-VOLTAGE SUPER CLASS AB CMOS OTA CELLS WITH VERY HIGH SLEW RATE AND POWER EFFICIENCY 1077 Sushmita Baswa received the B.Eng. degree from Bangalore University, Karnataka, India, in 1999, and the M.S.E.E. degree from the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, in Her research interests include the design of lowvoltage mixed-signal ICs. She has industrial experience in the design of high-performance image sensors for applications including broadcasting, security, video conferencing, medical, and consumer applications. Jaime Ramirez-Angulo (M 76 SM 92 F 00) received a degree in communications and electronic engineering (Professional degree), the M.S.E.E. degree from the National Polytechnic Institute, Mexico City, Mexico, and the Dr.-Ing. degree from the University of Stuttgart, Stuttgart, Germany, in 1974, 1976, and 1982, respectively. He is currently Klipsch Distinguished Professor and Director of the Mixed-Signal VLSI lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces. He was Professor at the National Institute for Astrophysics Optics and Electronics (INAOE) and at Texas A&M University. His research is related to various aspects of design and test of analog and mixed-signal very large scale integrated circuits. Dr. Ramirez-Angulo received the URC University Research Council Award for exceptional achievements in creative scholarly activities and the Westhafer Award for Excellence in Research and Creativity, in March and May 2002, respectively. Ramón González Carvajal (M 99 SM 04) was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1996), and Professor (2002). He is also Adjunct Professor at New Mexico State University, Las Cruces. He has published more than 100 papers in international journals and conferences. His research interests are related to low-voltage low-power analog circuit design, low-power A/D and D/A conversion, and analog and mixed-signal processing.

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