Low-output-impedance BiCMOS voltage buffer

Transcription

1 Low-output-impedance BiCMOS voltage buffer Johan Bauwelinck, a) Wei Chen, Dieter Verhulst, Yves Martens, Peter Ossieur, Xing-Zhi Qiu, and Jan Vandewege Ghent University, INTEC/IMEC, Gent, 9000, Belgium a) Abstract: A low power, 3.3 V BiCMOS voltage buffer is presented showing gigahertz operation, low output impedance and low input current. The buffer is designed to make the voltage at an unused negative output of a current switching DAC equal to the voltage of the positive current output, thus increasing the switching speed of the DAC. By consequence the buffer has to sink a fast switching current. A super emitter follower is used for achieving the low output impedance whereas base current compensation is used to reduce the input current. Simulation results in a 0.35 µm SiGe BiCMOS process are included demonstrating a low output impedance, a small input current, a high 3 db bandwidth and a good transient response at 330 µw static dissipation. Keywords: Voltage buffer, output impedance, BiCMOS. Classification: Integrated circuits References [1] A. Tabatabaei, A. Fotowat, M. Delurio, and S. Navid, A high slew-rate unity-gain low-voltage buffer with large Active/Quiescent current ratio, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp , [2] H. W. Cha and K. Watanabe, Wideband CMOS current conveyor, Electron. Lett., vol. 32, no. 14, pp , [3] P.R.Gray,P.J.Hurst,S.H.Lewis,andR.G.Meyer,Analysis and Design of Analog Integrated Circuits, John Wiley and Sons, New-York, Introduction Voltage buffers play an essential role in most analogue electronic systems. An opamp connected as a unity gain buffer is often used. The overall feedback loop can provide gain accuracy, a low-offset, and a low dynamic output resistance when the loop gain is sufficiently large. But large loop gain requires more severe compensation, which degrades the response time, and accumulated phase shift and delay within the loop becomes problematic at higher frequencies [1]. For high-speed operation a more simple structure is desirable. Suitable topologies are based on open loop or local feedback approaches, and can be optimised for any specific application. The proposed voltage buffer is part of a current switching DAC in which 34

2 Fig. 1. Application (a) and proposed voltage buffer (b) it is used to make the voltage at the unused negative current output equal to the voltage at the positive current output, thus increasing the switching speed (see Fig. 1 (a)). The DAC output voltage at the positive current output is not fixed because this current is fed into a current mirror, the input voltage of which changes over the complete current range. Without the buffer the voltage difference between the positive and the negative output of the DAC would result in lower switching speeds, as parasitic capacitances have to be charged/discharged. By consequence, the proposed voltage buffer only has to sink current, but this current shows fast transitions between 0 and 900 µa when the digital code of the DAC changes. Since the buffer only has to sink current a pmos or pnp follower output stage is a good choice as its bias current does not limit the current drive capability. An nmos or npn follower placed in front of this output stage makes a very simple buffer. In CMOS technology, such a simple buffer has been used in [2]. The buffer we designed is part of a BiCMOS chip. We extended this simple structure to take advantage of the high-speed bipolar transistors and to reach a much faster response and a much lower output impedance. The base current of the input bipolar transistor was compensated in our design, resulting in a significantly reduced input current. 2 Circuit description A circuit diagram of the proposed voltage buffer is shown in Fig. 1 (b). The input voltage Vin is transmitted to Vout by the cascade of an npn and a pnp emitter follower. Simple nmos and pmos current mirrors have been used to build the 25 µa and the 50 µa current sources. The output resistance of an emitter follower is approximately 1/g m. This output resistance is too high when a low impedance load is to be driven. Increasing the collector current of the pnp follower would reduce the output impedance of the buffer but at the cost of a significantly higher power consumption. To minimize the output resistance, a super emitter follower is 35

3 used [3]. This circuit uses local negative feedback through the npn transistor to reduce the output resistance by a factor of about g m npn r o pnp. We added a capacitor (100 ff) to increase the phase margin of this small feedback loop. The current through the pnp transistor is constant (25 µa neglecting the npn base current) and by consequence also the current through the npn follower (25 µa neglecting the pnp base current) so that the offset voltage between input and output is constant (at a certain temperature). Neglecting the base currents, the output voltage Vout is: V out = V in V be npn + V be pnp = V in + V T ln (I S NPN /I S PNP ) (1) in which I S NPN (I S PNP ) is the saturation current of an npn (pnp) transistor and V T the thermal voltage. Since the current through the npn transistor is approximately constant, the base current of the npn can be easily compensated via the slow pmos cascode mirror. This pmos mirror mirrors the base current of an identical (matched) npn follower so that the input current equals the difference between both base currents which is very small. For large output currents, the base current of the npn transistor in the super emitter follower can not be neglected. This will result in an increased offset between input and output. The base current of this npn transistor however is not limited to 50 µa because the output current can provide a part of this base current via the pnp transistor. The buffer s ability to sink current is not limited by any current source. By consequence the power consumption (P) is relatively low: P =4 25 µa 3.3 V + V out I out = 330 µw + V out I out (2) 3 Simulation results The simulated voltage offset is typical equal to 1mV to 9mV for the output current range of 0 to 900 µa. Taking into account corner, temperature ( 40 C to 110 C) and supply variations (3.3 V±5%) gives an offset of 40.6mV to 26.6mV. The maximum input current over 300 monte carlo simulations taking into account temperature ( 40 C to 110 C) and supply variations (3.3 V±5%) is 82.5 na. Without this compensation the worst-case input current would be 673 na, which is about 8 times larger. The voltage gain of the buffer varies typically from to when the output current is swept from 0 to 900 µa (curve b in Fig. 2). A typical output resistance of 11.4 Ω at DC was calculated. Taking into account corner, temperature (( 40 C to 110 C) and supply variations (3.3 V±5%) a worstcase output resistance of 28 Ω is obtained. Curve a shows the voltage gain in case a simple pnp follower would have been used. Curve a varies from to and a typical output resistance of 161 Ω was calculated, which is about 15 times higher. Because of its simple architecture, and despite the low power consumption, this design is inherently fast. The typical 3 db bandwidth ranges from 36

4 Fig. 2. Output voltage variation as a function of the output current Fig. 3. Transient response MHz for Iout = 0 to GHz for Iout = 900 µa. Taking into account corner, temperature ( 40 C to 110 C) and supply variations (3.3 V±5%) gives a 3 db bandwidth of 577 MHz to GHz for Iout = 0 and GHz to GHz for Iout = 900 µa. The minimum speed can be increased by increasing the bias current sources of the super emitter follower. When the bias current sources of the super emitter follower are doubled the 3 db bandwidth (for Iout = 0) rises from MHz to GHz. Fig. 3 shows the transient response of the voltage gain (Vout/Vin) as a result of a step (rise/fall time 100 ps) of the input voltage (1.3 V to 1.7 V) 37

5 and a step (rise/fall time 100 ps) of the output current (0 to 900 µa). 4 Conclusion It is shown that the proposed circuit performs very well as a voltage buffer. The transient response is very good which makes it a useful building block in our application. It typically achieves a 11.4 Ω output impedance, an MHz to GHz 3 db bandwidth and an input current smaller than 100 na while having a small static power consumption (330 µw). The proposed design is robust with respect to corner, temperature and supply variations. Acknowledgments The work described in this publication is partly supported by the Flemish Government under the research contract IWT Sympathi and partly by the European Commission under the research contract IST GIANT. The authors would like to thank also Alcatel and STMicroelectronics for their financial and technical support and the other partners of the GIANT project for their cooperation. 38