Fast CMOS Transimpedance Amplifier and Comparator circuit for readout of silicon strip detectors at LHC experiments

Transcription

1 Fast CMOS Transimpedance Amplifier and Comparator circuit for readout of silicon strip detectors at LHC experiments Jan Kaplon - CERN Wladek Dabrowski - FPN/UMM Cracow Pepe Bernabeu IFIC Valencia Carlos Lacasta IFIC Valencia Robert Szczygiel - INP Cracow

2 Motivations Check the feasibility of the designing of the fast amplifier/comparator FE optimised for long strip SSD in CMOS.25µm technology Design follows the specifications for readout chip for ATLAS SCT Detector capacitance in the range of 2pF (3pF max) ENC in the range of 15e- for 2pF input capacitance 2ns peaking time time walk for 1.2 1fC signal <16ns (1fC threshold) matching of the comparator better than 5% of 1fC signal (sigma spread)

3 Architecture of the Front-End channel Inp Preamplifier Threshold Shaper Comparator One channel comprises three AC coupled blocks: fast, transimpedance preamplifier (12ns peaking time) shaper (peaking time 2ns) differential discriminator Out Why AC? limiting the matching problem to the differential discriminator improving robustness of the design against low frequency drifts (1/f noise, low frequency interferences) Improving the PSRR of the circuit in low frequency range relatively easy layout (42µm pitch)

4 Architecture of the Preamplifier Vcc Ib1 M3 M5 Ib2 M4 M6 VC1 M2 Cf1 C1 Inp Ifeed M1 Mf1 Mf2 GND1 ZVT1 Out Ib3 M7 R1 Gain [db] = 4 µa I input = 6µA I input frequency [Hz] Bandwidth ~6MHz Open Loop Gain ~83dB Cascode amplifier with active feedback Input transistor M1 3µm/.5µm Bias 4-7µA (equivalent to 9-16mS) Feedback current 7nA 1.6µA (Rfeed 15 75kOhm)

5 AC characteristic of the Preamplifier Z in [Ω] 1 2 I input = 4µA I input = 5µA I input = 6µA Phase [ ] C input = 2pF 95 input I = 6µA I input = 4µA I input = 5µA frequency [Hz] frequency [Hz] Input resistance 1 15 Ohm at 1MHz Phase [ ] 1 9 = 5µA = 2pF, I input C input = 75nA I feed 8 = 1.25µA I feed = 1µA I feed Phase margin better than 8 adjustable with Ifeed frequency [Hz]

6 Preamplifier responses to 1fC Preamplifier Output [mv] C input C input = 3pF = 2pF Preamplifier Output [mv] I feed = 1.25µA I feed = 1µA I feed = 75nA 721 C input = 1pF Time [ns] Responses for various Cdetector. Feedback current 1µA Input current 55µA Time [ns] Responses for various feedback currents. Input capacitance 2pF Input current 55µA Peaking time 12 14ns Gain ~4mV/fC

7 Architecture of the Shaper stage VT2 VT1 Vcc VB1 R2 ZVT3 ZVT4 R2 C2 Inp M8 C3 R3 M9 ZVT2 C4 R9 R11 M12 R12 M13 R1 ZVT6 ZVT5 Out1 Amplitude [V] fc signal R4 Ib4 M1 M11 Ib5 M14 M15 Out2 M fc threshold R5 R6 R7 R13 C5 R14 R Time [ns] GND2 VB2 Schematic diagram of the shaper stage. Pulse gain ~15 V/V (6mV/fC with preamp) Peaking time 2ns R8 Response to 3.5fC charge seen at the differential output. The signals are DC separated by the threshold voltage VT2-VT1).

8 Vcc Inp1 Inp2 R17 M17 M19 R16 Architecture of the Discriminator SL R18 M18 Ib6 Vdd M24 M25 M22 R19 M2 M21 M23 Ib7 M26 Out M27 Amplitude [V] Amplitude [V] Amplitude [V] Input fc threshold 3.5 fc signal Time [ns] Diff pair output Time [ns] Output GND2 GND3 DC gain ~9dB Min overdrive for 2ns pulse ~3mV (< 1σ noise) Calculated offset spread (RMS) 4.5mV Time [ns]

9 Time walk simulation Amplitude [mv] fC response 1.2fC response 1fC threshold Time [ns] Amplitude [V] Time Walk 12.2ns Time [ns] Comparator input Comparator output Time walk defined as the difference of comparator response delays for input charges of 1.2fC and 1fC with threshold set to 1fC.

10 Layout and testability full channels including preamplifier, shaper and comparator readout via serial output register 2. 8 analogue test channels including preamplifier, shaper and comparator input stage readout directly via output buffers 3. Biases and threshold voltage - external 4. Four calibration lines distributing input signals every fourth channel 5. Chip area 4 x 4mm 2, dimensions of the channel 42µm x 2mm

11 Response of the analogue chain Amplitude [mv] Input charge: -4 to 16fC Amplitude [mv] V Power Supply (nominal) 2V Power Supply Time [ns] Charge [fc] Peaking time 2ns, semigaussian Gain ~55mV/fC Dynamic range 12fC Linearity better than 5% inside the dynamic range and limited power supply and extreme corners of technology Amplitude [mv] Nominal Parameters Corner: -3σ Corner: +3σ Charge [fc]

12 Single analogue channel - ENC C = C = 25pF input input ] - ENC [e ] - ENC [e I feed I d I feed I d ENC of the analogue channel as a function of feedback and input bias current.

13 Single analogue channel Peaking Time C input = C input = 25pF Peaking Time [ns] I feed I d Peaking Time [ns] Ifeed I d Peaking time as a function of feedback and input bias current.

14 Single channel Peaking Time vs. input capacitance Peaking time [ns] Input Current = 55uA Peaking time [ns] Feed Back Current = 1uA Feed Back Current =.4uA. Slope =.7 ns/pf Feed Back Current = 1.uA. Slope =.7 ns/pf Feed Back Current = 1.6uA. Slope =.5 ns/pf 5 Input Current = 45uA. Slope =.9 ns/pf Input Current = 55uA. Slope =.7 ns/pf Input Current = 65uA. Slope =.5 ns/pf Input Capacitance [pf] Input Capacitance [pf] Peaking time as a function of input capacitance for different feedback and input bias currents.

15 Single analogue channel FWHM C input = C input = 25pF FWHM [ns] 4 35 FWHM [ns] I feed I d I feed I d FWHM as a function of feedback and input bias current. FWHM for ideal CR-RC µ Peaking Time

16 Single channel - Noise slope ENC [e-] Input Current = 55uA ENC [e-] Feed Back Current = 1uA Feed Back Current =.4uA. Slope = e/pf Feed Back Current = 1.uA. Slope = 44.1 e/pf Feed Back Current = 1.6uA. Slope = e/pf 4 2 Input Current = 45uA. Slope = 47. e/pf Input Current = 55uA. Slope = 44.1 e/pf Input Current = 65uA. Slope = e/pf Input Capacitance [pf] Input Capacitance [pf] ENC as a function of input capacitance for different feedback and input bias currents.

17 Estimation of the noise performance Components: Channel thermal noise GIC noise Correlation term GIC thermal noise Flicker noise Assumptions: Γ excess noise factor 1.3 n slope factor 1.45 Type of the filter CR-RC3 EKV modelling of gm, γ and intrinsic capacitances of the transistors vs. the inversion order ENC [e-] GIC Correlation Channel Thermal Noise Feedback Noise [pf] C detector Comparison for Iinput 55µA and Ifeed1µA: Markers measurement Lines calculation Good agreement except for the parallel noise contribution: predicted value 4e- vs. 5e- measured 1/f

18 Noise performance of the active feedback Components: Channel thermal noise Flicker noise (not filtered in ideal CR-RC filter - but thanks to AC coupling between stages) Observation: ENC related to the active feedback almost twice higher comparing to classical passive feedback built with resistor of equivalent value still not a problem for capacitance detector above 1pF Advantage of the active feedback: Small feedback devices higher bandwidth and preamplifier gain Possibility of adjusting a phase margin and the Peaking Time ENC [e-] ENC [e-] R F total ENC of active feedback ENC thermal noise: NMOS PMOS ENC flicker noise: NMOS PMOS Ifeedback = 1/g m ENC active feedback ENC passive resistor feedback Ifeedback R F =1/g m [kω]

19 Full chain measurements Efficiency Charges from 1 to 16fC Threshold [mv] Threshold [mv] Charge [fc] Threshold scans and response curve in one channel of the chip measured for Ipreamp=55µA and Ifeedback=1µA.

20 Full chain measurements Gain and ENC Gain [mv/fc] Mean: 6.8mV/fC RMS:.48mV/fC ] - ENC [e Mean: 68e - RMS: 21e Channel Number Channel Number Distribution of channel gains and ENC in one chip (56 channels) measured for Ipreamp=55µA and Ifeedback=1µA. Good agreement with analogue measuerements.

21 Full chain measurements Offset and Time Walk Offset [mv] Mean: 2.2mV RMS: 2.9mV Timewalk (ns) Mean: 12.4ns RMS:.7ns Channel Number Channel Number Distribution of comparator offsets (~3mV) and time walks (~12.5ns) in one chip (56 channels) measured for Ipreamp=55µA and Ifeedback=1µA.

22 Summary of results 1. Functionality in wide range of biases (currents and power supply) and technology corner parameters (±3σ) 2. Gain ~55mV/fC ±5mV/fC (function of bias), good linearity up to 12fC signal (for all possible corner parameters and limited power supply) 3. Peaking time 2ns ±2ns (adjustable with feedback current) 4. ENC for Cinput 25pF 14 16e- (function of bias) 5. Input resistance in the range of 1 Ohm at 1MHz 6. Very high uniformity of gain (.8% RMS) 7. Small variation of offsets 3mV RMS (5% of 1fC) no channels outside distribution 8. Small variation of ENC 3% RMS 9. Time walk of premp/shaper/comparator ~12.5ns (measured at 1fC threshold between 1.2 and 1fC signals) 1. Analogue power consumption at nominal biases (55µA input) 2.4mW/channel (.95µA) 11. 1Mrad of X-Ray no visible effects

23 Addendum: Transconductance of BJT and NMOS transistors - remainder ] 2 gm/i [1/v BJT 1µm x 1.2µm (DMILL) 35 3 NMOS 2mm/.5µm (CMOS.25) NMOS 2.5mm/1.5µm (DMILL) I Gm/I for MOS in weak inversion n-times lower than for BJT n slope factor ~1.45 for IBM

24 Addendum: Single analogue channel - Gain C input = C input = 25pF Gain [mv/fc] Gain [mv/fc] I feed I d I feed I d Gain of the analogue channel as a function of feedback and input bias current.

25 Addendum: Response to overdrive 1fC and 1fC signal separated by 8ns distance seen at the input of the comparator.

26 Addendum: Components contributing to final spread of the comparator offset Offset spread of the NMOS input pair amplified by the gain of stage (~2.5V/V) Offset spread of the transistors used in the threshold circuit, buffers and comparator stage Voltage mismatch due to resistor matching (RMS from foundry data.5%) For 1 mv sigma offset of Vt for all transistor pairs and for nominal bias of 2 3 µa in the input stage: σ Vt = (1 2.5) + (1.4.5e 14.7e 3e 1e ) = mV

27 Addendum: Time Walk measurement Efficiency Delay scans for 1.2 & 1fC charge at 1fC threshold 1fC charge 1.2fC charge Timewalk (ns) Walk Mean: 12.4ns RMS:.7ns Delay [ns] Time walk defined as the difference of comparator response delays for input charges of 1.2fC and 1fC at 1fC threshold Channel Number Distribution of time walks (~12.5ns) in one chip (56 channels) measured for Ipreamp=55µA and Ifeedback=1µA.

28 Addendum:Current and power consumption Current at nominal bias condition: (Iinput + 4uA) x 128 For Iinput = 55uA (1mS transconductance):.95ma/channel (2.4mW/channel) For one 128 channel chip: 31mW (121mA) For 12 chip module: 3.7W (1.45A)