RX64DTH - A Fully Integrated 64-channel ASIC for Digital X-ray Imaging System with Energy Window Selection

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1 RX64DTH - A Fully Integrated 64-channel ASIC for Digital X-ray Imaging System with Energy Window Selection P. Grybos, A. E. Cabal Rodriguez, W. Dabrowski, M. Idzik, J. Lopez Gaitan, F. Prino, L. Ramello, K. Swientek, P. Wiacek Abstract--We report on the multichannel IC (RX64DTH) designed for position sensitive X-ray measurements with silicon strip detectors and dedicated to medical imaging applications. This integrated circuit has a binary readout architecture and possibility of selecting energy window for measured signals. The design has been realized in 0.8 µm CMOS process. The core of the RX64DTH chip consists of 64 readout channels. The single channel is built of four basic blocks: charge sensitive preamplifier, shaper, two independent discriminators and two independent 0-bit counters. Each readout channel counts pulses, which are above low discriminator threshold and independently pulses above high discriminator threshold. The energy resolution in such architecture is limited by noise of a single channel and by channel to channel threshold spread. We present noise and matching performance of a single chip and the performance of 384-channel system built of silicon strip detector and six RX64DTH chips. In the 384-channel system an equivalent noise charge of about 00 el. rms has been achieved for shaper peaking time of 0.8 µs and the strip capacitance of 3 pf. The deviation of discriminator thresholds for the whole system is only 87 el. rms. The obtained results show clearly that the energy resolution and uniformity of analog parameters (noise, gain, offsets) are sufficient for medical diagnostic applications such as dual energy mammography and angiography. I. INTRODUCTION IGITAL X-ray imaging systems consisting of Dmultielement sensor and multichannel readout ASICs are very promising alternatives to traditional medical imaging systems due to their high count rate capabilities, large dynamic range and very good spatial resolution. If additionally such digital imaging systems are able to extract energy information about X-ray radiation, the image contrast can be improved dramatically together with reduction of the radiation dose delivered to a patient [1, ]. Profiting of our experience in design of ASICs for digital readout of silicon strip detectors [3,4] and utilizing first very promising results of their possible applications in clinical diagnostics [5] we have made a step forward in developing a position sensitive X-ray system dedicated to dual energy mammography and angiography. The core part of the system is 64-channel IC called RX64DTH with a binary readout architecture and with the possibility of an energy window selection of input signals for each readout channel. The full system is built of six RX64DTH chips connected to 384 strips of silicon detector. The architecture and the results of test measurements for a single RX64DTH IC as well as the noise and matching performance for the whole 384-channel system are presented below. (a) II. RX64DTH ARCHITECTURE The block diagram of RX64DTH IC is shown in Fig.1(a). Manuscript received October 15, 004. This work was supported in part by the Polish State Committee for Scientific Research under Grant No. 3T11B0147 and European Union ALFA Programme under Contract No. AML/B7-311/97/0666/II-004. P. Grybos, W. Dabrowski, M. Idzik, K. Swientek, M. Wiacek are with the Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, Al. Mickiewicza 30, Cracow, Poland (telephone: , A. E. Cabal Rodriguez is with CEADEN, Havana, Cuba. J. Lopez Gaitan is with Universitad de los Andes, Bogota, Columbia. F. Prino is with Sez. di Torino, INFN, Torino, Italy. L. Ramello is with Dip. Scienze e Tecnologie Avanzate, Universita del Piemonte Orientale and INFN, Alessandria, Italy. (b) Fig. 1. (a) Block diagram of RX64DTH chip, (b) block diagram of the single channel.

2 Fig.. Schematic diagram of a charge preamplifier and shaper. The chip comprises of six basic blocks: 64 analog front-end channels, 64 counters, an input-output block, command decoder, digital to analog converters and calibration circuit. The block diagram of a single analog channel is shown in Fig. 1(b). Each channel is built of charge sensitive preamplifier, shaper, two independent discriminators and two independent 0-bit counters. The charge preamplifier integrates the current input signal from a silicon strip detector and gives the output voltage signal. The shaper circuit provides noise filtering and semi-gaussian pulse shaping with the possibility of peaking time control in the range µs. Each front-end channel is equipped with two discriminators, which are set for low and high threshold respectively. Pulses above the low and above the high threshold are counted independently by the pair of counters placed in every channel. The counters are based on pseudo-random shift register, which results in very compact layout. A. Noise Optimization of the Preamplifier The charge preamplifier is based on folded cascode configuration (transistors M1-M4, see Fig. ) with feedback loop built of capacitor C 1 of 00 ff and transistor M5 working in a linear region. The source follower M6-M7 is added to provide capability for driving the following shaper stage. In response to a δ-like current pulse carrying charge Q, a voltage step of amplitude Q/C 1 is produced at the charge preamplifier output. This voltage step is applied to a band-pass filter CR- (RC) with the following (nearly equal) time constants C ( C + C ) os 3 τ d (1) gm 13C3 i 1 r ds 17C3 i RC4 τ () τ (3) where C os is a total capacitance to ground seen from the drain of transistor M15, g m13 is the transconductance of M13 and r ds17 is the drain-source resistance of M17. A simplified noise scheme of the preamplifier is shown in Fig. 3. The Equivalent Noise Charge (ENC) for a case with relatively short peaking time, when 1/f noise is negligible, can be expressed as [6] ENC F v C v n in + Fi i ntp (4) Tp where C in is the total input capacitance including gate of input transistor M1, sensor capacitance C d and any stray capacitance introduced by connection between the sensor and the IC, v n is the spectral density of equivalent input voltage noise, i n is the spectral density of equivalent input current noise dominated by feedback resistance r ds5 of transistor M5, T p is the peaking time (T p τ i1 ), F v and F i are constants dependent on a filter type. From formula (4) one can see that contribution of the input voltage white noise to the ENC is inversely proportional to the square root of T p, while contribution of the input current noise is proportional to the square root of T p. Fig.3. Equivalent noise scheme of preamplifier. The input voltage noise v n is usually dominated by a thermal noise of the input transistor M1 (W 1 /L 1 = 500µm/1µm). Other components which can contribute to voltage noise are the thermal noise of current source M4 (W 4 /L 4 = 100µm/10µm) and the thermal noise of parasitic resistance r of connection between the sensor and transistor M1. The input current noise i n is determined by small source-drain resistance r ds5 of

3 transistor M5 (W 5 /L 5 = µm/10µm), which works in linear region. Taking into account these four components the total ENC can be expressed as ENC ENCw 1 + ENCw4 + ENCw5 + ENC (5) The contributions of these components to total ENC depend on the peaking time T p of the following shaper stage. Summary of noise simulation for significant noise components are shown in Fig. 4. r VTH for the high threshold. Both these stages are biased from common voltage divider built of transistors M3-M34. The following stages M35-M43 and M50-M58 are comparators with hysteresis. The hysteresis is controlled by an external current IDIG. In order to reduce the effect of comparator switching on preamplifier and shaper performance, the positive power supply rails are cut after the differential pair, and the comparators have separate Vddd power rails (see also Fig. 6). Fig.4. Contributions of different components in the preamplifier to total ENC as a function of a peaking time. The noise calculation is made for drain current of the input transistor M1 I d = 500 µa, input capacitance C in = 4 pf, parasitic resistance r = 40 Ω and drain-source resistance r ds5 equal to 0 MΩ. Figure 4 shows also 1/f components ENC f1 and ENC f4 of transistors M1 and M4, but they are really negligible (for detail methodology of noise calculation see [7]). Since in our case the peaking time is about 0.8 µs, so the main contribution to the total ENC = 160 el. rms comes from the ENC w5 component, which is equal to 19 el. rms, while ENC w1 is only 73 el. rms. We have implemented a possibility to control the drain-source resistance r ds5 by an internal DAC so it can be set to a value up to 100 MΩ and then its contribution to noise is ENC w5 = 58 el. rms. There are however some practical limitations for setting high r ds5 value, since transistor M5 should provide a certain DC current to the detector. It is obvious in case of DC coupled detector and it may be necessary in case of AC coupled detector with oxide pin-holes (broken coupling capacitors resulting in a DC path between the silicon and the preamplifier input) [8]. B. Pair of Low Offset Discriminators To reduce the channel-to-channel offset variation in a large multichannel IC, the discriminators are AC coupled to the shaper and are designed in fully differential mode (see Fig. 5). In each channel the two discriminators work independently. The input differential stages M7-M31 and M45-M49 have gain about 0 db and are used for providing differential threshold voltages, VTL1-VTL for the low and VTH1- Fig.5. Schematic diagram of a pair of discriminators. Taking into account process matching parameters we have sized transistor dimensions to obtain offset spread less than 1.7 mv at one sigma level. This has been verified by Monte Carlo simulation [9]. III. LAYOUT DESIGN The RX64DTH IC is designed in 0.8 µm AMS CMOS process. The layout of the chip with the major blocks is shown in Fig. 6. The total die area is 3700 µm 6500 µm. As the chip contains both analog and digital circuits placed on a common epi-type substrate, particular attention has been paid to floor plan, guard rings and distribution of power supply voltages. Full custom layout techniques are used for all blocks, except for command decoder. After layout extraction the HSPICE simulations of analog blocks have been repeated using the extracted netlist including parasitic capacitances and some extra parasitic resistances, especially for power supply lines (added manually).

4 connection is about 35 Ω. Since the detector thickness is only 300 µm of silicon, to obtain good detection efficiency, the module is dedicated to work in edge on configuration (the strips are parallel to the incoming X-ray beam) [5]. Fig.6. Layout of the RX64DTH: 1 - input pads, - charge preamplifiers & shapers, 3 - discriminators, 4 - counters, 5 - command decoder, 6 -calibration, 7 - DACs, 8 - analog power supply (Vdd), 9 - analog ground, 10 - power supply for discriminators (Vddd), 11 - power supply for digital blocks, 1 - data output pads, 13 - control pads, 14 - digital ground. V. MEASUREMENT RESULTS The board was tested using a Cu-anode X-ray tube, with different targets (Ge, Zr, Nb, Mo, Ag, Sn). In this set-up six different energies of X-rays are available. Performing discriminator threshold scans of the RX64DTH for a given energy of X-ray radiation, one can extract gain, offset and noise in all 384 channels of readout electronics [3]. To evaluate the performance of the whole system in a real environment the measurements were done simultaneously for all channels. A fixed width of energy window was set during the measurements (both thresholds were scanned simultaneously). The results of the measurements are shown in Fig. 8 for gain, in Fig. 9 for noise and in Fig. 10 for offset in low threshold discriminator (results for high threshold discriminator are nearly the same). It is clearly visible that spreads of analog parameters are smaller inside the chip, than between the chips. At the design stage of RX64DTH we foresaw, that the spread of analog parameters from chip to chip can be higher than inside the chip. For that reason we implemented a local 3-bit address IV. TESTING BOARD As mentioned before the RX64DTH IC has been developed for medical diagnostic application. Six RX64DTH chips have been glued on a small Printed Circuits Board (PCB), together with a 384-strip silicon detector (see Fig. 7). Fig.8. Spread of gain. Fig.7. Testing board. The sensor and integrated circuits are connected using pitch adapter printed on glass and wire bonding techniques. The basic detector parameters are: p+ strip on n-type substrate, strip pitch 100 µm, strip length 1 cm. The detector is of AC coupled type and has FOXFET bias structures. The detector leakage current is typically below 100 pa/strip and the total strip capacitance is about 3 pf. The resistance of the fanout Fig.9. Spread of noise - data for Ag peak.

5 independently, we have calculated the energy threshold spread of our 384-channel system for above mentioned application. The histogram of threshold spread of 6-chip module (expressed in energy) is shown in Fig. 11. The spread of threshold is equal to 0.3 kev, i.e. 87 el. rms assuming 3.67 ev for generation of an electron-hole pair in silicon detector. This spread is much smaller compared to the measured noise ENC 00 el. rms, so it does not limit the performance of the system. We conclude that the energy resolution of our multichannel system is enough good to foreseen application, like dual energy digital imaging. Fig.10. Spread of discriminator offsets. in command decoder, which is set during chip bonding on the PCB. So the values of low and high discriminator threshold can be loaded different for each chip on the board. This protocol guarantees cancellation of unwanted threshold spread from chip to chip with precision equal to 1 LSB of threshold DAC. Let us consider the module performance in possible future tests in clinical diagnostics with dual energy of X-ray beams. In coronary angiography medical examinations are aimed at visualisation of coronary arteries with contrast agent injected. The typical contrast medium with iodine has a K-edge absorption at kev. The idea is to take images of test object at two different X-ray energies (31 kev and 35 kev) which are below and above the iodine K-edge, and then perform (logarithmic) subtraction to extract the iodine signal [, 5, 10]. For the electronic readout system this means, that the low threshold discriminators should count the photons of both energies (31 kev and 35 kev) at the same time, while the high threshold discriminator should count only higher energy photons (35 kev). Fig.11. Spread of the low and high thresholds in 384-channel module dedicated to digital imaging with X-ray beam of dual energy 31 kev and 35 kev. VI. SUMMARY We have presented the RX64DTH chip, which is fully integrated digital readout for silicon strip detector and additionally provides some energy information about X-ray radiation. The detailed analysis and measurements show that the RX64DTH ICs can be used to build medical imaging system for dual energy mammography and angiography. Examples of using described above multichannel system for taking the images of mammographic phantoms are presented in [10]. VII. REFERENCES [1] Besch H. J.: "Radiation detectors in medical and biological applications." Nucl. Instr. and Meth., vol. 419, 1998, pp [] Alvarez R. E., Macovski A.: "Energy selective Reconstructions in X-ray Computerized Tomography." Phys. Med. Biol., vol. 1, 1979, pp [3] Dabrowski W., Grybos P., Hottowy P., Swientek K., Wiacek P.: "Integrated readout of silicon strip detectors for position sensitive measurements of X-rays." Nucl. Instr. and Meth., vol. 51, 003, pp [4] Grybos P., "Low Noise Multichannel Integrated Circuits in CMOS Technology for Physics and Biology Applications." Monography 117, AGH Uczelniane Wydawnictwa Naukowo-Dydaktyczne, Cracow, Poland, 00, available at: [5] Baldazzi G., et al.: "A silicon strip detector coupled to RX64 ASIC for X-ray diagnostic imaging." Nucl. Instr. and Meth., vol. 51, 003, pp [6] Chang Z.Y. and Sansen W.: "Effect of 1/f noise on resolution of CMOS analog readout systems for microstrip and pixel detectors." Nucl. Instr. and Meth., vol. A305, 1991, pp [7] Grybos P.: "Design for a low noise of multichannel integrated circuits on example of RX64 chip." Electronics and Telecommunication Quarterly, Polish Academy of Science, Warsaw, Poland, No. 3, 004, pp [8] Bolla G.: "Testing and quality insurance during the construction of the SVXII silicon detector." Nucl. Instr. and Meth., vol. A473, 001, pp [9] Dabrowski W., Grybos P., Swientek K., Wiacek P.: "Corner and matching analysis for multichannel analogue ASICs." Proceedings of 10 th International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 003, pp [10] Ramello L, et al..: "A Silicon Microstrip System Equipped with the RX64DTH ASIC for Dual Energy Mammography" IEEE NSS-MIC 004 Conference Record. Taking into account the spreads of analog parameters and the possibility of setting the thresholds in each chip