Low noise Amplifier, simulated and measured.

Transcription

1 Low noise Amplifier, simulated and measured. Introduction: As a study project a low noise amplifier shaper for capacitive detectors in AMS 0.6 µm technology is designed and realised. The goal was to design an amplifier shaper with a noise contribution of 250 electrons and 12 electrons contribution per pf input capacitor. Also the amplifier should have a relative high gain and bandwidth. The amplifier will be situated as close to the detector as possible. The advantage is very short connections between the detector and the amplifier. The disadvantage is an optional higher radiation level. The design of the amplifier should be radiation tolerant. After making a basic design with only rectangular FET s, a radiation Figure 1: Rectangular versus Gate around FET. tolerant version was developed with for the N-type gate around FET s (see figure 1). From these two basic designs two layouts are made, and simulated. With these layouts a test chip is realised with of both versions 4 channels. 1

2 The schematic diagram: The schematic diagram of the amplifier (rectangular version) is drawn in figure 2. Basically is this circuit a one FET (M0) amplifier. Due to noise demands more component have been added. Figure 2: The schematic diagram of the rectangular version. The mayor part of the noise on the output of the amplifier has its origin in the input FET (M0) of the amplifier. Optimising the circuit for noise demands makes the width of this FET 1500 µm. The disadvantage of a FET this size is a large Miller capacitor, which reduces the bandwidth of the amplifier. To reduce the influence of the Miller capacitor, a cascode FET (M16) is added to the circuit. Due to the limited power supplies (-2 V and +2 V) the variation called folded cascode is used. The FET M1 is a current source. The only way of reducing the influence of the Miller capacitor is keeping the drain voltage constant, which is what a cascode FET does. The DC current through the drains flows into the current source (M1). The AC current flows into M16 and gives on the drains of M16 the output signal. The fact that the current source M1 is not ideal gives some signal lost of the AC current in M1. The output FET M16 can be a lot smaller as M0. This makes his Miller capacitor a lot smaller, which gives a larger bandwidth to the circuit. The FET M13 is again a current source. The output impedance of this source is the drain resistor for the amplifier. The amplifier is a charge amplifier, so the main feedback path is a capacitor. To make the amplifier work a DC feedback path, the feedback resistor M2, is needed. The 2

3 value of the feedback resistor is adjustable because a FET is used as a resistor. Due to this the discharge time of the feedback capacitor is adjustable. The FET s M28 and M30 are needed to correct the DC setting of the amplifier to 0 Volt on the output. Without this the circuit would stabilise at 1 V. Based on this design a radiation hard version has been developed. In figure 3 the schematic diagram of this version is drawn. Figure 3: The schematic diagram of the 'gate around' version. There are made 3 changes in the circuit compared to the rectangular version: Change 1 The feedback resistor M2 is now a P-type FET. 2 The source of M0 is connected to VDD 3 The level shifter is now adding 1 V to the output. Reason To make a circuit radiation tolerant, only the layout of the N-type FET s needs to be changed to gate around form. It s impossible in the gate around form to make a FET longer as its width, so making a high impedance resistor is impossible. When connected to ground the working area of the control voltage of the resistor M2 is below 2 V. The gate of M0 stabilises now on +1 V. 3

4 The simulations and tests. In the test set-up a support circuit is build around the test chip. The schematic diagram of this circuit is copied to the simulator, to make both situations as equal as possible. In the simulation a 5-pF load capacitor is placed on the output of the circuit to simulate the electrical connection of a probe. The amplifier is designed to amplify the signal from a capacitive detector. The Minimal Ionising Particle (MIP) of such a detector is electrons. The electrical charge of 1MIP = = C Input 1p5F D.U.T Output 56 Cdet 5pF Figure 4: The schematic diagram of the test set-up. In figure 4 the schematic diagram of the in- and out-put circuit in the test set-up is drawn. The capacitor on the output is placed only in the simulator to represent the capacitance of the output pad and the test probe. At the input of the Amplifier (D.U.T.) a charge of 1 MIP is made by discharging a voltage step over a capacitor. The value of this step is: 15 Q U = = = 1. 28mV 12 C The test is done with 6 values of detector capacitance to investigate its influence. 4

5 The gain. The simulator makes for every setting a calculation. The answer is a picture like figure 5 and 6. These pictures deliver the numbers in table 1. Figure 5: The output with a C det = 0 pf. Figure 6: The output with a Cdet = 27 pf. For the measurements it s a little different. Now signal and noise are mixed together. By taking the average of 64 of these signals a clear picture appears to measure the gain, see figure 7 and 8. Figure 7: Measured output signal with C det = 0 pf. 5

6 Figure 8: Measured output signal with C det =27 pf. In the table 1 the test and simulation results are given for the gain of the amplifier. Table 1: Output signal versus 1 MIP input signal. Capacitor Gate around Rectangular Simulated Measured Simulated Measured (pf) (mv) (mv) (mv) (mv) The numbers from the table are graphically reproduced in figure 9. In both cases the measured gain is higher as simulated. The simulations are done with the extracted form of the layout. This extraction is an ideal representation of the circuit made in layout. Added to the circuit are all parasitic capacitors in the layout, so the simulation gets closer to reality. Not included here are fabric tolerances. The amplifier is a charge amplifier with a capacitor as the main feedback. When the size of this capacitor is smaller as expected, the gain gets higher. The choice for small feedback capacitors makes the influence of this error worst. 6

7 Output (mv) Gain. Gate around simulated Gate around measered Rectangular simulated Rectangular measured Cdet (pf) Figure 9: The gain versus C det for both versions. 7

8 The noise. In the same test set-up as above the output noise of the amplifier shaper is measured with an AC-RMS voltmeter. The bandwidth of this meter goes up to 30 MHz. These values are calculated back to the input with the formula: U noise = U u 1MIP Input _ noise( electrons) In table 2 the results from the simulation and the measurements are given. This is also plotted in figure 10. Table 2: The noise figures. Capacitor Gate around Rectangular Simulated Measured Simulated Measured Noise S/N Noise S/N Noise S/N Noise S/N (pf) (electron) (electron) (electron) (electron) noise (electrons) 4000 Gate around simulated gate around measured 3500 Rectangular simulated Rectangular measured 3000 Noise Cdet Figure 10: The noise calculated back to the input. 8

9 The difference between the simulation and the test chip is for noise about 2. It was expected to have a higher noise output from the test chip as simulated. There is no noise contribution from the test equipment and no signals from the environment coupling into the circuit in the simulation, so the noise should be larger. In figure 11 the signal to noise ratio is plotted. S/N Gate around simulated Gate around measured Rectangular simulated Rectangular measured Cdet Figure 11: Signal to Noise ratio. In table 3 the noise is split up into its sources. The first line gives the number of electrons noise from the amplifier itself. The second line the number of electrons added to this when a detector with a C det is connected to the amplifier. Table 3: The noise contributions. Gate around Rectangular Simulated Measured Simulated Measured Amplifier noise Noise / pf Cdet

10 The dynamic range: The dynamic range is simulated and tested in the range from 10 to 10 MIP input signal. The results are split into positive and negative going pulses, to keep the graphics readable Rectangular version: Figure 12: Positive output signal, rectangular version, simulated MIPS input signal Time (nsec) Figure 13: Positive output, rectangular version, measured. The first thing that strikes the attention in these two pictures is the rising edge of the pulse. The rising edges of all pulses follow a strait line with the same angle. The output buffer causes this. The capacitors on the output are charged with the bias current of the buffer, which gives the linear rising of the voltage. The output signal is linear up to 5 MIP input signal in the simulation as well the measurement. 10

11 Figure 14: Negative output signal, rectangular version, simulated. Dynamic range Rectangular negative. Output (V) Number of MIPS 8 Input signal Time (nsec) Figure 15: Negative output, rectangular version, measured. The timing of the falling edge of the pulse increases somewhat with the number of MIPs input signal. The speed is now mainly controlled by the signal size and not by buffer limitations. The dynamic range is up to 8 MIP in simulation and 6 in measurement linear. The difference is caused by the gain of the circuit. A second observation is the fact that the gain for negative signals is larges as for positive going signals. The output buffer causes this. The output signal is plotted 5 times in figure 16 with the same input signal (10 MIP). The difference is the bias current for the output buffer. The positive gain of the circuit is getting close to the negative gain. 11

12 Figure 16: The output signal for 5 buffer bias currents. 12

13 Gate Around version: The test and simulation are also done for the gate around version. In figure 17 and 18 the output is plotted for the positive going pulses. Figure 17: Positive output signal, gate around version, simulated Number Of MIPS input signal Figure 18: Positive output signal, gate around version, measured. Time (nsec) As with the rectangular version the rise the bias current of the output buffer limits time of the output. The gain of the amplifier is linear for the range of 10 MIP in figure 17, simulated. In the measured plot (figure 18) the gain is linear up to 7 MIP. The non-linearity is now caused by the power supply limit. 13

14 Figure 19: Negative output signal, gate around version, simulated. Signal (V) time (sec) Figure 20: Negative output signal, gate around version, measured Number Of MIPS input signal The linear region for gain is with negative pulses more than 10 MIP simulated, measured its 8 MIP. The limit is again the power supply. The output is now limited a little earlier due to the long tail pair in the control part of the amplifier. The bias current now has no influence on the gain. The maximum current downwards is not controlled by the bias current, but by the size of the FET. 14