ECEN 607 (ESS) Texas A&M University. Edgar Sánchez-Sinencio TI J. Kilby Chair Professor

Transcription

1 1 ECEN 607 (ESS) Texas A&M University Edgar Sánchez-Sinencio TI J. Kilby Chair Professor

2 Next we review the conventional Op Amp Design frequency response compensation techniques and also we introduced a simple LV Current- Mode based Op Amp using resistors as transconductors. Difference Differential Amplifiers are also introduced. 2

3 UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER V DD V in V bs M3 M1 M5 M2 M4 1 V in C p1 High Impedance M6 2 M7 v o1 C p2 3 M8 M9 Node C L 3 v o is a low impedance M1=M2; M3=M4 V ~ 1 SS A V3 Ignoring zeros we can model this topology as: V in V in + Input Stage - i i o1 o 2 1 Second 2 3 Output Stage Stage R C p R o1 1 o 2 C R o 3 p2 C L v o A A V V 1 T 0 s g o1 g m1 g o3 A A V 0 0 A 0 A 0 V1 V 2 V 3 m p s p s p s p CL 1 ; 2 2 gm6 g g o6 o7 ; ; p 1 g g g C o2 8 p 1 04 ; p 2 go6 g C p 2 o7 3 3

4 UNCOMPENSATED CMOS OPERATIONAL AMPLIFIER STABILITY ISSUES The low frequency voltage gain is high enough for a number of applications. The open loop poles are far from the origin, this can cause stability problems for closed loop applications. Closed loop poles might end very close to the jw axis and some in the RHP. How to tackle this stability problem will be discussed next. 4

5 Two-Stage Uncompensated Amplifier V DD M 3 M 4 M 6 v in I o I o 2 2 M 1 M 2 v in V out I 6 I g I o I 7 M 5 M 7 V SS Uncompensated Operational Amplifier g g A A A m2 m6 V V1 V2 Large voltage gain g02 g04 g06 g07 Poles are close to the j axis causing stability problems 5 5

6 Employing a simple capacitor will split correctly the poles but will generate a Zero in the RHP. Using an RC compensation can eliminate the zero and split poles. The resistor can be implemented with transistor in the ohmic region. V DD v in M 3 M 1 M 4 A M 8 M 6 M 1 M 2 V 0 out C M 11 C B M 9 v bias M 5 M 7 V SS Analog and Mixed Signal Center, TAMU (ESS) Improved internally compensated CMOS operational amplifier. Better bias for the output stage (M8 and M9) 6 6

7 A variation at the output stage with class AB is shown below. V DD v in M 3 M 4 v DS 4 M9 + I o I o 2 2 M 1 M 2 v in v GS 9 I o I 10 M 8 v GS 6 C C - + I 6 M 6 I L C L + M 7 V bias M 5 M 10 v GS 7 - V SS CMOS op-amp with class-ab output stage and RC pole splitting. 7 7

8 Pole Splitting can be carried out with a compensation capacitor feedback and a voltage buffer as shown below M3 M4 M8 I bias v in M1 M2 v in C C M10 M12 Out M5 M6 M9 M11 M7 Two-Stage amplifier with source follower compensation scheme Without M12 and M11 a zero in the PRH With buffer (voltage follower), zero is eliminated and pole splitting (due to C C ) is kept. 8 8

9 An Improved Frequency Compensation Technique for CMOS Operational Amplifiers using Current Buffers ECEN 607 (ESS) Courtesy of Hatem Osman

10 Background.- Two-Stage Op-amp with Miller compensation The first stage is a differential-input/single-ended output stage, and the second stage is a class A or class AB inverting output stage. C c DC Gain V IN,p V IN,n g m1 g m2 V OUT r o1 C p r o2 C L Transfer Function Pole/zero locations RHP zero Dominant Pole Non-dominant Pole

11 Two-Stage Op-amp with Miller compensation Pole Splitting C c Pole/zero locations V IN,p V IN,n g m1 g m2 V OUT r o1 C p r o2 C L Pole-zero position diagram Increasing C c achieves sufficient pole-splitting thus improving the PM. However, the larger C c shifts the RHP zero to lower frequencies thus ruining the PM.

12 Miller Op-amp with Nulling Resistance Introducing a small series resistance in series with C c may cancel the RHP zero or shift it to the LHP. R c C c Pole/zero locations V IN,p V IN,n g m1 g m2 V OUT r o1 C p r o2 C L No zero LHP zero Can be used to cancel the first non-dominant pole. Disadvantages: To achieve a sufficient phase margin, second pole cross-over of the unity gain frequency should be avoided. Thus, the Op-amp stability is severely degraded for capacitive loads of the same order as compensation capacitor.

13 Improved compensation technique The RHP zero is a result of the feed-forward path through C c. C c V IN,p V 1 g m1 V IN,n g m2 V OUT r o1 C p r o2 C L The RHP zero can be eliminated if we cut the feed-forward path and make the compensation capacitor unidirectional. Virtual Ground C c V IN,p V 1 g m1 V IN,n g m2 V OUT r o1 C p r o2 C L

14 Improved compensation technique Virtual Ground C c DC Gain V IN,p V 1 g m1 V IN,n g m2 V OUT r o1 C p r o2 C L Dominant Pole Non-dominant Pole

15 Improved compensation technique Miller compensation with nulling resistance Dominant pole Improved compensation technique Dominant pole Non-dominant pole Non-dominant pole Gain-bandwidth product Gain-bandwidth product Phase margin Phase margin

16 Circuit Implementation Miller compensation with nulling resistance. V DD V B,p M p,0 V B,p M p,2 V IN,n M p,1 M p,1 V IN,p R c C c V OUT C L M n,1 M n,1 M n,2 Improved compensation technique. V DD V SS V B,p M p,0 V B,p M p,3 V B,p M p,2 V IN,n M p,1 M p,1 V IN,p M p,4 C c V OUT V B,n M n,1 M n,1 M n,2 M n,3 C L V SS

17 Other performance parameters- PSR Miller compensation with nulling resistance. V DD V B,p M p,0 V B,p M p,2 V IN,n M p,1 M p,1 V IN,p R c C c V OUT VSS PSR M n,1 M n,1 M n,2 C L f p1-20log(a v,0) freq Improved compensation technique. V DD V SS V B,p M p,0 V B,p M p,3 V B,p M p,2 V IN,n M p,1 M p,1 V IN,p M p,4 C c V OUT VSS PSR -20log(A v,0) M n,1 M n,1 M n,2 V SS V B,n M n,3 C L f p1 1/r o1c p GBW Better PSR at high frequencies. freq

18 Design Example Miller Compensation Design an OTA with GBW > 5MHz, C L =10pF, PM>70, and SR> 2 V/µs. V DD Choose C c =C L /2= 5 pf. GBW > 5MHz V B,p M p,0 V B,p M p,2 SR > 2 V/µS V IN,n M p,1 M p,1 V IN,p R c C c V OUT PM > 70 M n,1 M n,1 M n,2 C L Let V SS Then Choose R c > 1/g m2

19 Design Example Miller Compensation Simulation results OL Transfer function Negative supply rejection Positive supply rejection Transient step response

20 Design Example Miller Compensation Capacitive load driving capability PM > 70 for C L < 15 pf.

21 Design Example Improved Compensation Design an OTA with GBW > 5MHz, C L =10pF, PM>70, and SR> 2 V/µs. V DD Choose C c =C L /2= 5 pf. GBW > 5MHz V B,p M p,0 V B,p M p,3 V B,p M p,2 SR > 2 V/µS V IN,n M p,1 M p,1 V IN,p M p,4 C c V OUT In order to make the current transformer biased during slewing interval V B,n M n,1 M n,1 M n,2 M n,3 C L PM > 70 V SS Let Then Let s use g m2 =6gm1 like the miller Opamp to make a comparison between the capacitive driving capability. For the same capacitive load driving capability, the second stage will consume less current making it suitable for low power applications

22 Design Example Improved Compensation Simulation results OL Transfer function Negative supply rejection Positive supply rejection Transient step response

23 Design Example Improved Compensation Capacitive load driving capability PM > 70 for C L < 100 pf.

24 Design Example Improved Compensation Summary of Simulation results Parameter Spec Miller Compensation Improved Compensation GBW > 5MHz 5.5 MHz 6 MHz PM > SR + > 2 V/µs 2.75 V/µs 3 V/µs SR - > 2 V/µs 3 V/µs 3.15 V/µs PSR db At (0-3.1 khz) PSR db At (0-44 khz) db At ( khz) db At ( khz) DC gain db 51.3 db Current consumption Capacitive load driving capability - 80 µa 110 µa - PM > 70 for C L < 15 pf PM > 70 for C L < 100 pf

25 Using another current buffer Op Amp topology. M3 M4 M7 M8 I bias v in M1 M2 v in M11 M12 V out C C M5 M6 M9 M10 Two-Stage amplifier with Current Buffer compensation scheme. Improve SR at the expense of power consumption

26 Differential Output Two Stage Amp with a capacitor compensation with a current Buffer ( Common Gate) 26

27 27

28 Note that this and previous structure are fully differential but this approach could be used for single output topologies. Compensation using a current buffer ( current gain) Note that the current-mirror introduces an extra inversion which must be taken into consideration for the single ended version. P.J. Hurst, Lewis, S.H. ; Keane, J.P. ; Aram, F. ; Dyer, K.C. Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers IEEE Transactions on Circuits and Systems I, Volume: 51, Issue: 2, Feb

29 Besides the above zero the amp has three poles Elements of Current-Mirror Cc compensated Note that the common-gate and current mirror topologies under ideal case are almost identical, however in practice the one using current-mirrors is more power hungry and has a larger parasitic capacitance CB 29

30 Summary for Two Stage Op Amp Architecture Designs Roots close to the j axis for uncompensated Q 6 V in V bias I ss Q 5 V in I bias Q 7 C L s p1 s p 2 Potentially unstable for some values of C L I bias = C L S R *2.5 Q 6 V in V bias I ss Q 5 V in I bias Q 9 Q 10 Q 7 V o Improved output stage optimal bias of Q 6 and Q 7 No significant change of pole locations. A v (0) -> + A v () -> - Q 9 Q 6 V o Pole splitting => one dominant pole V in V bias I ss Q 5 V in I bias C C Q 10 Q 7 s p1 s p 2 z 1 z 1 Phase deteriorates phase margin The good and the bad news Analog and Mixed Signal Center, TAMU (ESS) 30

31 Two possible solutions to cancel z 1 and keeping s p2 > t =GBW and s p1 small V o V o Vin V in C C C L C Q10 C I ss V bias I ss V bias Q 11 Internally Compensated with R C C C Internally Compensated with unity gain buffer (Q 10, Q 11 ) Operational Amplifier (conventional) Architectures. Reader.- See the internally Op Amp compensated with current gain buffer in previous pages Analog and Mixed Signal Center, TAMU (ESS) 31

32 Compared to two-stage Op Amp, folded cascode Op Amp has: Improved input common-mode range (ICMR) Improved power supply rejection (PSR) Push-pull output stage Self compensation Folded-cascode Op Amp broken into stages [Allen] 32

33 Folded Cascode OpAmp The extended ICMR is achieved The bias currents I4 and I5 should be designed such that I6 and I7 never goes to zero (i.e. I 4,5 = 1.2I 3 1.5I 3 ) Poor noise performance: In addition to the input transistors, transistors M 4,5 and M 10,11 generate significant current noise 33

34 Small Signal Analysis R A and R B are the resistances looking into the sources of M 6 and M 7 R A = r ds6+ 1 g m10 1 and R 1+g m6 r ds6 g B = r ds7+r II m6 1+g m7 r ds7 The currents i 7 and i 10 is expressed as i 7 = g m2(r ds2 r ds5 ) R B +(r ds2 r ds5 ) v in = g m2 v in 2 k+1 2 i 10 = g m1(r ds1 r ds4 ) R A +(r ds1 r ds4 ) Thus, the transfer function can be found as follows v out = g m1 v in 2 + g m2 R 2 k + 1 out = R II g m7 r ds7 where R II = g m9 r ds9 r ds11 where k = R B r ds2 r ds5 v in g v in 2 m k 2 + 2k g m1r out Where R out = g m9 r ds9 r ds11 g m7 r ds7 r ds2 r ds5 Where k is the low-frequency unbalance factor 34

35 35 Frequency Response The frequency response is dominated primarily by the output pole due to the high output impedance P out = 1 R out C out In order to have sufficient phase margin, all other pole should be located will above the GBW Pole at source of M 6 (Folding node) Pole at source of M 7 (Folding node) P A = P B = Pole at drain of M 6 P 6 = g m10 2C gs +2C bd 1 R A C gs +2C bd g m6 C gs +2C bd 1 R B C gs +2C bd g m7 C gs +2C bd Pole at source of M 8 P 8 = g m8r ds8 g m10 C gs +C bd Pole at source of M 9 P 9 = g m9 C gs +C bd Remarks: We assumed R B 1 g m7 because at high frequency, where this pole has influence, C out shunts the drain of M 7 to ground.

36 Power Supply Rejection The following model is used to calculate the negative PSR The gate, source and drain of M 11 varies with V SS The gate, source of M 9 varies with V ss The transfer function V out V out V ss = sc gd9r out sc out R out +1 V ss can be found as PSRR can be calculated PSRR = A v V out V ss [Allen] Output stage of folded cascode OpAmp 36

37 Power Supply Rejection [Allen] At low frequency, we assume that other source of V ss injection becomes significant Low frequency PSRR - is at least as large as the magnitude of the differential voltage gain A v PSRR + can be derived similarly: the primary source of injection is through 37

38 38 Slew Rate SR + = SR = I 3 C L The bias currents I 4,5 should be designed such that I 6,7 never goes to zero I 4,5 = 1.2I 3 1.5I 5

39 39 Maximum Available Output Swing V out max = V DD V SD5 V SD7 V out min = V ss + V DS9 + V DS11 The output common mode level V ocm is often dictated by the circuit that interface with the amplifier (e.g. V ocm = V DD 2)

40 Noise Analysis The noise current of M 1, M 4 and M 10 goes directly to the output At low and medium frequencies, noise contribution of the cascode transistors (M 6 and M 8 ) can be neglected Total output noise current becomes 2 i out = 8KTγ g m1 + g m4 + g m10 Input referred noise density 2 v n,in = 8KTγ g m1 1 + g m4 g m1 + g m10 g m1 Half circuit model 40

41 Folded Cascode Op Amp Design Procedure Design approach for the folded cascode Op Amp using long-channel model [Allen] 41

42 42 Design Example Design a folded cascode Op Amp to comply with the following specifications using 0.18μm CMOS technology Parameter Spec Slew rate > 10 V μs Load Capacitor 10pF Power Supply ±1 V Max/Min Output Voltage ±0.5 V GBW > 10 MHz Min Input CM Voltage 0.3 V Max Input CM Voltage 1 V Differential Voltage Gain > 60 db Power Dissipation < 2 mw

43 43 Design Example (Cont.) Solution: From the value of the slew rate we can get I 3 I 3 = SR C L > I 3 100μA Select I 3 = 120μA I 4,5 will be designed such that I 6,7 never goes to zero I 4 = I 5 = 1.2I 3 to 1.5I 3 Select I 4 = I 5 = 1.25I 3 = 150μA Knowing I 4 and I 3, we can get the quiescent, min, and max values of I 6,7 I 6,Q = I 7,Q = I 4 0.5I 3 = 90μA I 6 min = I 7 min = I 4 I 3 = 20μA I 6 max = I 7 max = I 4 = 150μA From the min and maximum output voltages we can get overdrive voltage of transistors M 4 11 V SDsat 4 7 max = 0.5 V DD V out max = 0.25 V V DSsat 8 11 max = 0.5 V out min V SS = 0.25 V

44 44 Design Example (Cont.) The value of GB gives g m1,2 g m1,2 = GB C L μa V Thus, choose g m1,2 = 700 μa V From g m1,2 and I 1,2, we can obtain V DSsat(1,2) V DSsat 1,2 = 2I 1 g m1 = I 3 g m1 = 0.17 V The minimum input common mode voltage defines V DSsat3 V icm min = V SS + V DSsat(3) + V Tn + V DSsat 1 Thus, V DSsat 3 = 0.13μA for V Tn = 0.4 V We need to check that the maximum input common mode voltage is satisfied V icm max = V DD V SDsat 4 + V Tn = 1.15 V Meets the spec

45 45 Design Example (Cont.) Now, we have the bias currents I D and overdrive voltage V DSsat of all the transistors. Thus, we can obtain W L of all the transistors from the ACM model or square-law model if long-channel transistors are used. The channel length of the transistors should be chosen to satisfy the specified voltage gain. The current flowing in transistors M 6 11 can have any value from 20 μa to 150 μa depending on the amplitude and polarity of the differential input voltage. Therefore, they should be sized such that the worst case V DSsat of each transistor meets the specified limits on the output voltages. Bias voltages of the cascode transistors V PB2 and V NB2 are chosen such that V PB2

46 DC operating point Simulation Results Transistor M 1,2 M 3 M 4,5 M 6,7 M 8,9 M 10,11 W L I D μa V DSsat

47 47 Simulation Results Input common-mode range ICMR testbench Minimum input common mode voltage is 0.28 V

48 48 Simulation Results Output Swing Output Swing Testbench The gain is perfectly linear for 0.5 V out 0.5

49 49 Simulation Results Open loop response Open loop response testbench A v > 60 db GB > 10 MHz

50 50 Simulation Results Slew Rate Slew-rate testbench SR +, SR > 10 V μs

51 51 Simulation Results PSRR PSRR + testbench PSRR - testbench

52 52 Summary of Results The following simulation results for C L = 10pF, V DD = 1 V and V SS = 1V Parameter Spec Simulation SR + > 10 V μs 11.3 V μs SR - > 10 V μs V μs Max/Min Output Voltage ±0.5 V V GBW > 10 MHz 10.7 MHz Min Input CM Voltage 0.3 V 0.28 V Max Input CM Voltage 1 V 1 V Differential Voltage Gain > 60 db 62dB PSRR db PSRR db Power Dissipation < 2 mw 840 μw

53 Techniques for Wideband Amplifiers Focus the improvement in the load of the differential pair Current Mirror at the output load R Frequency Dependent Current Mirror (FDCM) C F >> Cgs Conventional Wideband Alternative C F 0.1K < R < 1K I b C F Low Frequency Behavior High Frequency Behavior T. Itakura and T. Iida, A Feedforward Technique with Frequency-Dependent Current Mirrors for a Low-Voltage Wideband Amplifier, IEEE J. Solid-State Circuits, Vol. 31, No.6, pp , June

54 An example of its use: V DD M P 3 R 3 I b M P 4 v in M P 2 C F 1 M P1 v in C L v o C F 2 M P 3 R 1 M n1 M n 2 R 2 M n 4 V SS Wideband Amplifier with Feedforward Technique What is the optimal value of R1 as a function og GmP3? C F1 by passes two current mirrors. C F2 is fed forward to the input of another FDCM and signal is amplified. 54

55 Next, we discuss different families of wideband reported in the literature. M n 3 v in A R L v o M n1 B v o M n 2 B RL A v in M n 4 An alternative is to connect C F instead to nodes B to nodes A CF R SS CF F. Centurelli et al, A Bootstrap Technique for Wideband Amplifiers, IEEE Trans. on Circuits And Systesm I, Vol. 49, No. 10, pp , October

56 FOLDED-CASCODE WIDEBAND AMPLIFIER ( See page 11 for cascode) M P4 V b 4 M P3 V b 4 M P2 v in V b 1 V b 1 v in M P1 C L V OUT R F1 V b 1 C F1 v in v in C F 2 V b 1 Vb2 V out CL I tail V b2 M n5 I tail M n3 M n4 M n3 M n4 Conventional Folded-Cascode (FC) FC with Capacitive Feedforward V DD I bias V b 1 V o C L R F1 V b 1 V b2 C F1 V o V in C F 2 R F 2 V b 1 V b2 C L V o Differential Wideband Amplifier F. Opt Eynde, W. Sansen, A CMOS Wideband Amplifier with 800MHz Bandwidth, IEEE Custom Integrated Circuits Conf., pp , 1991 V SS 56

57 V DD i o+ M 12 M 5 M 6 M 14 O P V bias v + Figure 1 X i o- I B I B I B I B O N B M 1 i b M 3 M 8 V- X Figure 1 O P O N v in ix X R i R A O N i o - i o+ O P - Fig 2 Pseudo Differential Op Amp M 13 M 2 M 4 M 9 M 10 M 11 V SS ir = Vin/R Fig. 1 Transconductance Amp Basic Structure based on current-mode ix = - ir IB > ir E.K.F. Lee, Low-Voltage Opamp Design and Differential Difference Amplifier Design Using Linear Transconductor with Resistor Input, IEEE Trans. Circuits and Systems II,vol. 47, pp , Aug

58 Transimpedance amplifier V DD V bias C C i o+ v o v + Figure 2 v - i o- R 1 R 1 V SS Fig 3 VCVS Amplifier: Op Amp i o1+ v 1+ Figure 2 v 1- i o1- Transimpedance amplifier v o i o2+ v 2+ Figure 2 v 2- i o2- DDA 58

59 References SS Rajput, SS Jamuar, Low voltage analog circuit design techniques, IEEE Circuits and Systems Magazine, pp , 2002 S. Yan and E. Sánchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial, IEICE Trans. Fundamentals, Vol. E83-A, No. 2, pp , February 2000 E. Sánchez-Sinencio and Andreas G. Andreou, Eds. Low-Voltage/Low-Power Integrated Circuits and Systems, IEEE Press, Piscataway, NJ 1999 X. Xie, M.C. Schneider, E. Sanchez-Sinencio and S.H.K. Embabi, Sound Design of Low Power Nested Transconductance-Capacitance Compensation Amplifiers, IEE Electronics Letters, Vol. 35, pp , June A. Rodriguez-Vazquez and E. Sánchez-Sinencio, Eds., Special Issue on Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems, IEEE Trans. on Circuits and Systems I, vol. 42, No. 11, November 1995 J. Crols, J.; Steyaert, M.; Switched-opamp: an approach to realize full CMOS switched capacitor circuits at very low power supply voltages IEEE Journal of Solid-State Circuits,, Volume: 29, Issue: 8, Aug Pages: Analog & Mixed-Signal Center (AMSC)

60 References Very low-voltage analog signal processing based quasi-floating gate transistors,j Ramirez-Angulo, AJ Lopez-Martin, RG Carvajal, et all, IEEE J. Solid-State Circuits, pp , March 2004 Low threshold CMOS circuits with low standby current Stan, M.R. Low Power Electronics and Design, Proceedings International Symposium on, Aug Pages:97-99 A dynamic threshold voltage MOSFET (DTMOS) for ultra low voltage operation Assaderaghi, F.; Sinitsky, D.; Parke, S.; Bokor, J.; Ko, P.K.; Chenming Hu; Electron Devices Meeting, Technical Digest., International, Dec Pages: Resizing rules for MOS analog-design reuse Galup-Montoro, C.; Schneider, M.C.; Coitinho, R.M.; Design & Test of Computers, IEEE,Volume: 19, Issue: 2, March-April 2002 Pages:50-58 An MOS transistor model for analog circuit design.cunha, A.I.A.; Schneider, M.C.; Galup- Montoro, C.; Solid-State Circuits, IEEE Journal of,volume: 33, Issue: 10, Oct Pages: Series-parallel association of FET's for high gain and high frequency applications Galup-Montoro, C.; Schneider, M.C.; Loss, I.J.B.; Solid-State Circuits, IEEE Journal of,volume: 29, Issue: 9, Sept Pages: Analog & Mixed-Signal Center (AMSC) 60

61 References S. M. Mallya abd J. H. Nevin, Design Procedures for a Fully Differential Folded Cascode CMOS Operational Amplifier, IEEE J. of Solid-State Circuits, Vol 24, No. 6, pp , December D. B. Ribner, M. A. Copeland. and M. Milkovic, 8OMHz low offsetfully-differential and singleended opamps, in Proc. IEEE Custom Integruted Circuits Con/., 1983, pp This reference discusses three different Op Amp topologies: S. Rabii and B. A. Wooley, A 1.8V-V Digital Audio Sigma-Delta Modulator in 0.8-um CMOS, IEEE J. of Solid-State Circuits, Vol. 32, N0. 6, pp , June 1997 CMOS Analog Circuit Design, P.E. Allen, D.R. Holberg, Oxford University Press, 3 rd Edition, Analog & Mixed-Signal Center (AMSC)