Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

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1 Analog Integrated Circuits and Signal Processing, 36, 69 77, 2003 c 2003 Kluwer Academic Publishers. Manufactured in The Netherlands. Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing A. TORRALBA, 1 R. G. CARVAJAL, 1, J. RAMÍREZ-ANGULO, 2 J. TOMBS, 1 F. MUÑOZ 1 AND J. A. GALAN 1 1 Dpto. de Ing. Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain 2 Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM carvajal@gte.esi.us.es Received March 30, 2002; Revised August 15, 2002; Accepted October 11, 2002 Abstract. Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 µm CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 µa of quiescent current and a 10 pf load, using a 1.5 V single voltage supply. Key Words: low-voltage, low-power, operational amplifiers, dynamic biasing 1. Introduction The market of portable electronic equipment has pushed industry to produce circuit designs with very low supply voltage. Although two oxides are presently available in some analogue technologies, digital compatibility forces analogue circuits to operate with supply voltages close to a transistor threshold voltage. The first class-ab output stages followed the Monticelli s scheme [1], where quiescent currrent control (Fig. 1(a)) uses two complementary head-to-tail connected transistors and two matched current sources to implement a floating voltage source (Fig. 1(b)). This scheme achieves an accurate quiescent current control by means of a translinear loop at the expense of a high supply voltage (larger than two V GS ). Several lowvoltage (V DD < 1.5 V) class-ab op-amp schemes have been recently reported [2] [6]. In [2] the (negative) floating voltage source of figure 1b was implemented with one current source and one transistor (Fig. 1(c)), although a complex control loop was required for quiescent current control. In [3], diode connected transistors Author to whom correspondence should be addressed. Tel.: , Fax: acting as loads of simple common source amplifiers were used to bias the output transistors (Fig. 1(d)). Although the proposed stage is very simple, no a good class AB behavior was achieved and dependence on process variations was not fully eliminated. In [4] a folded version of the Monticellis output stage was proposed to achieve operation with low supply voltage (Fig. 1(e)). An additional feedback loop is required for minimum current control. The output stage in [5] (Fig. 1(f)) implements another version of the floating battery of Fig. 1(b), using switched capacitor circuits. This stage, used in sample-data applications, requires a voltage doubler to be operated under low-voltage conditions. The output stage in [6] (Fig. 1(g)) uses two source followers to achieve large driving capability, but at the cost of a complex inner-loop for common mode control in nodes driving the output stage. Other output stages using a feedback loop for quiescent current control can also be found in the literature, but they have a slower speed and may have stability problems because of the feedback loop. The rest of this paper has been organized as follows. In Section 2, the new class AB output stages for CMOS opamps with rail-to-rail output swing and quiescent current control are presented. In Section 3,

2 70 Torralba et al. Fig. 1. Low-voltage class-ab output stages: (a) [1], (b) basic circuit, (c) [2], (d) [3], (e) [4], (f) [5], (g) [6]. experimental results of both output stages are shown and compared. Finally conclusions are drawn in Section Proposed Class AB Output Stages and Quiescent Current Control In this paper two new CMOS class AB output stages for continuous-time operation are presented with simple and accurate quiescent current control (Figs. 2(a) and 3) First Output Stage (Fig. 2(a)) Figure 2(a) shows the first proposed output stage and Fig. 2(b) its biasing circuit for quiescent current control. The proposed stage uses resistor R and current sources I r to implement the floating voltage source V AB of Fig. 1(b). The input and output terminal voltages are V X and V out. Cross connecting terminals X and to the gates of transistors M outp and M outn, respectively, allows the supply voltage to be close to a transistor threshold voltage. For larger supply

3 Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control 71 I 2 = I 1 I r - M outp M 2 V 2 I ' r V AB R V out - X + M 1 V 1 DA + - R' + V AB I r M outn I ' r I 1 (a) (b) I 2 = I 1 M outp M 2 - M 1 V Q 1 = V X I c R' V AB + X R M outn V out I 1 I c2 (c) Fig. 2. First proposed class-ab output stage: (a) basic idea, (b) dynamic biasing circuitry, (c) practical implementation. voltages a straight connection of these terminal should be done. In Fig. 2(b), transistor M 1 and current source I 1 determine V 1 = V Q X (upper index Q means quiescent value), while transistor M 2 and current source I 2 = I 1 determine V 2 = V Q. The resistor R and the differential amplifier DA driving two matched current sources I r constitute a voltage-to-current converter [8], so that I r = V AB/R = (V Q V Q X )/R. This floating voltage source V AB is replicated in Fig. 2a, by means of matched resistor R and current sources I r. In a real implementation, to reduce power consumption, M 1 (M 2 ) and I 1 = I 2 would be a scaled version of M outp (M outn ) and I Q Moutp = I Q Moutn, respectively. Fig. 2(c) shows a practical implementation of the whole output stage, where the amplifier DA of Fig. 2(b) has been implemented by means of a simple pmos differential amplifier. Bottom current sources I r and I r have been implemented by means of a low voltage current mirror, allowing operation with less than 1 V supply voltage. Note that the circuit in Fig. 2(c) maintains its operation independent on the supply voltage, as long as V AB remains negative (which approximately means V DD < 2 V in our technology). For larger supply voltages, the polarity of the floating voltage sources can be reversed by changing the role of nodes X Second Output Stage (Fig. 3) The second proposed output stage is shown in Fig. 3. In this figure, the bias current I o in the low voltage differential pairs M 1p M 3p and M 1n M 3n [7] accurately determines the quiescent output current

4 72 Torralba et al. X V AB + - M 3p M 1p M 1n M 3n M 2p M 2n 1 I o I o : α W + V - AB Z M outp I Moutp I M outn M outn V out where VX MAX is the maximum expected variation for the input node voltage V X. As a result, an appropriate value for V AB is V Q X V Q = V DD V Q GSM1n V Q SGM1p 2V DSsat VX MAX. If the input node V X in Fig. 3 is the first stage output of an op-amp, negative feedback reduces VX MAX to only a few mv so that, for a 0.8 µm CMOS technology with 0.8 V of transistor threshold voltages, V DD V AB is in the order of 1.8 to 3 V depending on transistor sizes and biasing currents. According to this reasoning, this stage can be operated with less than 1 V supply voltage if V AB = 0.8 V. Note that this stage can be also operated with a high supply voltage if V AB is positive. The same dynamic biasing scheme of Fig. 2(b) can be used to generate the floating voltage sources V AB between nodes X and W Z by means of two matched (and, normally scaled) 1 : α Fig. 3. Second proposed class-ab output stage. I Q out = I Q Moutn = I Q Moutp = 2αI o. Furthermore, the minimum current in the output transistors is given by Iout MIN = IMoutn MIN = I Moutp MIN = αi o. Note that I Q out and Iout MIN do not depend on the value of the floating voltage sources V AB, which is selected to allow an accurate copy of currents I M3p and I M3n to transistors M outp and M outn, respectively. Under quiescent conditions, if V AB was too large, transistors M 3p and M 3n would not be in saturation. On the other hand, if V AB was too small, transistors M 1p M 2p and M 1n M 2n would operate in linear region. Appropriate values for V Q X and V Q are: V Q X = V DD V Q SGM1p V DSsat VX MAX /2, and V Q = V Q GSM1n + V DSsat + VX MAX /2 respectively, I Moutp V X (a) I Moutn Table 1. Output stages and op-amp design parameters. Output Stage Output Stage Units of Fig. 2(c) of Fig. 3 I Moutp I Moutn M outp W/L 500/1 500/1 M outn W/L 165/1 165/1 R, R k M 1 W/L 50/1 20/1 M 2 W/L 16.5/1 6/1 I 1 = I 2 µa 7.5/1 7.5/1 M in1, M in2 W/L 500/1 500/1 I dp µa M 1p, M 2p W/L 25/1 M 3p W/L 50/1 M 1n, M 2n W/L 8/1 M 3n W/L 16.5/1 I o µa 3.75 V X (b) Fig. 4. Simulated class-ab behaviour of the output stages: (a) class AB behaviour of the first proposed output stage (Fig. 3), (b) class AB behaviour of the second proposed output stage (Fig. 2a).

5 Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control 73 replicas of current sources I r and resistor R. A special property of the output stage in Fig. 3 occurs when transistors M 3n and M 3p are biased near the linear region. In this case the output current can increase several times compared to the output current when transistors M 3n and M 3p are biased in the saturation region. This mode of operation can be used to obtain additional class AB behaviour as was demonstrated in [3], but it is not suitable for very low-voltage operation as the voltages at the gates of transistors M 3n and M 3p can experience big variations from its quiescent value, thus affecting the current source I b Simulation Results CMOS technology whose transistor threshold voltages are in the order of 0.85 V. Design parameters for the first output stage (Fig. 2) are resumed in Table 1. Fig. 4(a) presents the transistor currents I Moutp, and I Moutn for V X in the range [0.45 V, 0.9 V], with V DD = 1.5 V showing a typical class AB behavior. The quiescent output current I Q out of 74 µa is in good agreement with the expected value (75 µa). The same simulations were repeated for the second proposed output stage (Fig. 3). Fig. 4(b) shows the transistor currents I Moutp and I Moutn for V X in the range [0.1 V, 0.7 V], with V DD = 1.5 V. In this case, not only I Q out (76 µa) but also Iout MIN (38 µa) are accurately controlled by the biasing circuitry. The proposed output stages have been simulated with SpectreS and the parameters of a standard 0.8 µm I dp V- R c Cc V+ M in1 M in2 V out X Output Stage (figure 2a or 3) Fig. 7. Microphotograph of the op-amp with the first proposed output stage. Fig. 5. Simple op-amp fabricated for the testing of the output stages performances. V CM-ADJ R 2 V o R 1 V o C L C L V in V in a) b) Fig. 6. Configuration used in the measurements of the op-amps: (a) unity gain configuration with input-output common mode adjustment, (b) Gain R 2 /R 1 follower configuration. Fig. 8. Experimental results for the first proposed output stage in unity gain configuration.

6 74 Torralba et al. Table 2. Experimental measurements (C L = 10 pf, V DD = 1.5 V, C C = 10 pf, R C = 500, V CM ADJ = 600 mv). Output Stage Output Stage Units of Fig. 2(c) of Fig. 3 DC gain db Phase margin Unity gain frequency MHz Quiescent output current (µa) Minimum current through (µa) 0 38 output transistors Supply current (µa) PSRR db CMRR db THD (1 khz) db Input referred noise nv 2 /Hz (100 khz) Slew rate V/µs Peak output current µa Transient response, 0.3 V peak square input signal. Fig. 10. Microphotograph of the op-amp with the second proposed output stage. Fig. 9. Experimental results for the first proposed output stage in gain R 2 /R 1 = 5 configuration: (a) experimental DC sweep response, (b) experimental transient large signal behavior. 3. Experimental Results Both output stages were sent for fabrication as a part of a two-stage op-amp. For both output stages the same simple pmos differential pair with a current mirror load (Fig. 5) was used as input stage. Design parameters for both op-amps are also resumed in Table 1. These op-amps can be used for very low voltage switched op-amp applications using the scheme proposed in [9] or in sampled-data and continuous-time applications with the dc level shift in the input stage provided by the circuit proposed in [2]. Both op-amps designs were fabricated in the same standard 0.8 µm CMOS technology and, for each opamp, two feedback configurations were implemented (Fig. 6). Figure 6(a) shows the op-amp connected in unity gain configuration with a floating voltage source in the feedback loop. This voltage source provides low common mode voltage for the pmos input transistors as well as a V DD /2 common mode voltage for the output stage. (Note that in a low-voltage environment the input common mode voltage of the pmos input pair is close to ground while the desired common mode voltage for the output stage is V DD /2). The floating voltage source has been implemented by means of a switched capacitor circuit and allows measurements of the output stage with the nominal common mode voltage. Figure 6(b) shows the op-amp connected as a R 2 /R 1 amplifier. This configuration allows large output signal

7 Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control 75 Fig. 11. Experimental results for the second proposed output stage in unity gain configuration. measurements to be made. A value for R 2 /R 1 = 5 has been used with an input common mode of 150 mv, providing a 750 mv output swing, suitable for V DD = 1.5 V operation. Figures 7 9 show the experimental results obtained with the op-amp fabricated using the first output stage (Fig. 2). Figure 7 shows the op-amp microphotograph and Table 2 resumes the measured results. Figure 8 shows the experimental transient response in unity gain configuration. Note that the op-amp follows a 4 MHz square input signal. Figure 9(a) shows the experimental DC input sweep response in the gain 5 configuration of Fig. 6(b), demonstrating an almost rail-to-rail output swing. Finally Fig. 9(b) shows the experimental transient response in the gain 5 configuration for a large output swing. The same measurements were made for the opamp with the second output stage (Figs , and Table 2). Note that PSRR performance for both circuits is near 40 db and the THD for the second output stage is slightly improved. This is produced by the fact that the minimum output current is controlled in the second output stage. In both opamps the Slew-Rate obtained was10v/µs. This is fixed by the biasing current of the input differential pair (100 µa) and the compensating capacitance (10 pf), that is, it was not limited by the output stages. Finally, in both cases, the achieved unity gain frequency was 15 MHz with a phase margin of about 75. This places the desing amongst the best published to date for low voltage appliactions. Fig. 12. Experimental results for the second proposed output stage in gain R 2 /R 1 = 5 configuration: (a) experimental DC sweep response, (b) experimental transient large signal behavior. 4. Conclusions Two new low voltage output stages have been proposed for class-ab CMOS opamps. A new dynamic biasing technique allows an accurate quiescent current control and provides good PSRR. The second proposed stage also allows to set the minimum current through output transistors, which is a very convenient property for class-ab output stages. Experimental results confirm the high performance of these output stages operating in a low voltage environment and are in good agreement with the expected values.

8 76 Torralba et al. Acknowledgments This work has been financed the Spanish Comisión Interministerial de Ciencia y Tecnología (CICT) and the European Union (FEDER) under grant TIC C02. The authors would also like to thank Marta Rodriguez Pizarro for her help in the test of the chips. References 1. D. M. Monticelli, A quad CMOS single-supply op amp with railto-rail output swing. IEEE J. of Solid-State Circuits SC-21(6), pp , J. Ramírez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, A simple technique for opamp continuous-time 1 V supply operation. Electron. Lett. 35(4), pp , F. ou, S. H. K. Embabi, and E. Sánchez-Sinencio, Low-voltage class AB buffers with quiescent current control. IEEE J. of Solid- State Circuits 33(6), pp , De Langen and H. J. Huising, Compact low-voltage powerefficient operational amplifier cells for VLSI. IEEE J. of Solid- State Circuits 33(10), pp , G. Giustolisi, G. Palmisano, and T. Segreto, 1.2-V CMOS opamp with a dynamically biased output stage. IEEE Journal of Solid-State Circuits 35(4), pp , G. A. Rincon-Mora and R. Stair, A low voltage, rail-to-rail, class AB CMOS amplifier with high drive and low output impedance characteristics. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48(8), pp , V. Peluso, P. Vancoreland, A. M. Marques, M. S. J. Steyaert, and W. Sansen, A 900-mV low-power A/D converter with 77 db dynamic range. IEEE J. Solid-State Circuits SC-33(12), pp , J. Ramírez-Angulo, A. Torralba, and R. G. Carvajal, Lowvoltage CMOS amplifiers with wide input-output voltage swing based on a novel scheme. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47(5), pp , A. Baschirotto, R. Castello, and G. P. Montagna, Active series switch for switched opamp circuits. IEE Electronics Letters 35(4), pp , from the University of Seville, Seville, Spain, in 1983 and 1985, respectively. Since 1983, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Assistant Professor, Associate Professor (1987), and Professor (1996). He has published 30 papers in journals and more than 80 papers in conferences. His research interests are in the design and modeling of low-voltage analog circuits, analog and mixed-signal design, analog to digital conversion, and electronic circuits and systems with application to control and communication. Ramón González Carvajal was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1996), and Professor (2002). He has published more than 100 papers in International Journals and Conferences. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing. Antonio Torralba was born in Seville, Spain. He received the electrical engineering and Ph.D. degrees Jaime Ramírez-Angulo is currently Klipsch Distinguished Professor, IEEE fellow and Director of the Mixed-Signal VLSI lab at the Klipsch School of Electrical and Computer Engineering, New Mexico State University (Las Cruces, New Mexico), USA. He received a degree in Communications and Electronic

9 Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control 77 Engineering (Professional degree), a M.S.E.E. from the National Polytechnic Institute in Mexico City and a Dr.-Ing degree form the University of Stuttgart in Stuttgart, Germany in 1974, 1976 and 1982 respectively. He was professor at the National Institute for Astrophysics Optics and Electronics (INAOE) and at Texas A&M University. His research is related to various aspects of design and test of analog and mixedsignal Very Large Scale Integrated Circuits. Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2002, respectively. Since 1997, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1999). His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing. Jonathan Noel Tombs was born in Oxford, UK. He received the Electrical Engineering and Ph.D. degrees from Oxford University, UK, in 1987 and 1991, respectively. Since 1993, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1997), and Professor (2002). He has published more than 50 papers in International Journals and Conferences. His research interests are related to Digital Design and system verification with VHDL, low-voltage low-power analog circuit design, A/D and D/A conversion and analog and mixed signal processing. Juan Antonio Gómez Galán was born in Alosno, Huelva, Spain. He received the Electronics Engineering degree from the University of Granada, Granada, Spain, in Since 1998, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he is currently studying towards his PhD. He is also with the Electronics and Automatic Systems Engineering Department at the Huelva University where he is an Assistant Professor. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing. Fernando Muñoz Chavero was born in El Saucejo, Sevilla, Spain. He received the Telecommunications