HIGH GAIN, HIGH BANDWIDTH AND LOW POWER FOLDED CASCODE OTA WITH SELF CASCODE AND DTMOS TECHNIQUE

Transcription

1 HIGH GAIN, HIGH BANDWIDTH AND LOW POWER FOLDED CASCODE OTA WITH SELF CASCODE AND DTMOS TECHNIQUE * Kirti, ** Dr Jasdeep kaur Dhanoa, *** Dilpreet Badwal Indira Gandhi Delhi Technical University For Women, Kashmere Gate, Delhi Associate Professor, ECE Department, Indira Gandhi Delhi Technical University For Women, Kashmere Gate, Delhi Assistant Professor, Department of Electronics Engineering,JSSATE NOIDA ABSTRACT: Low power has become one of the key research areas in today s electronic industry. Need of low power is very important in the field of electronics where power dissipation is equally important as area and performance. There are different low power portable electronic equipments, low voltage design techniques have been developed that drive analog designers to create techniques such as Self Cascode and DTMOS technique. In this paper we have proposed a Folded Cascode OTA using low power techniques and analyzed its different properties through the PSPICE simulations for.18 micron CMOS technology at supply voltage of 1.8V. KEYWORDS: Folded Cascode OTA, Self Cascode and DTMOS Technique. 1.INTRODUCTION Folded Cascode OTA [1] has been chosen since it allows shorting of input and output terminals with extremely negligible swing limitations. Folded cascode OTA [2] is used for high speed applications thanks to its capability to provide high gain and large bandwidth. The Low Power Consumption to the OTA structure provides significant decrease in power with increase in gain. In 24 has explained an approach which may results in very high gain and low power dissipation [3, 4] by discussing the effects on the overall composite cascade circuit performance with one device operating in the sub threshold and the other device operating in the active region. To obtain high output impedance and therefore high gains, cascoding is done, where two MOSFETs are placed one above the other [5-8]. DTMOS transistor was first proposed for silicon on insulator SOI process technology. In DTMOS technique, the idea is to connect the gate and body of a transistor to change its threshold voltage of the device. The body terminal of PMOS transistors in bulk CMOS technology can be used as the forth terminal to enhance the performance of low-voltage analog circuits such as increasing the gain and bandwidth of the circuit. 2. LOW POWER TECHNIQUES There are various low power techniques. In this paper we are going to compare two low power techniques. 2.1 Self Cascode Technique Self Cascode [9-1] is the new technique, which does not require any high voltage at output nodes. It is useful in low-voltage design because it provides high output impedance to give high output gain. Self Cascode is a 2- transistor structure is shown in the given Figure 1, and can be treated as a single composite transistor. By using the composite structure, it has much larger effective channel length and the effective output conductance is very low. The transistor M1 is equivalent to a resistor, which is input dependent. To get the optimal 24

2 operation, the W/L ratio of upper transistor M2 is kept larger than that of lower transistor M1. The operating voltage of self cascode is much lower. Figure 1. Self Cascode Structure 2.2 Dynamic Threshold MOS (DTMOS) Technique: DTMOS transistor shows high threshold characteristic when it is off to minimize the leakage and at the same, it behaves as a low threshold device for high current drivability under low voltage supplies. This feature makes it as a promising candidate for modern ultra low voltage analog circuits. A PMOS transistor s gate and body terminals are connected without requiring any additional processing steps and it can be produced in standard CMOS technology. The idea is to connect the gate and body of the device to dynamically change the threshold voltage of the transistor. Figure 2, shows the representation of DTMOS. 3. PROPOSED FOLDED CASCODE USING SELF CASCODE AND DTMOS TECHNIQUE: The Proposed Folded Cascode OTA using Self Cascode is shown in Figure 3. At input terminals Self Cascode is not used but on rest of the circuits Self Cascode is used because this whole circuit works as load. In this proposed circuit we take the value of m=2. In this circuit each transistor splits into two so that upper transistors are working in saturation region while other is in linear region to work this circuit properly. The Proposed Folded Cascode OTA using DTMOS technique is also shown in Figure 3, where the body and the gate terminal are shorted such that they work in dynamic mode of operation and the rest of the circuit is similar to the Self Cascode technique, then such type of operation is known as DTMOS. 241 Figure 3. structure Figure 2. DTMOS Structure Proposed folded cascade OTA

3 4. CHARACTERISTICS OF PROPOSED FOLDED CASCODE OTA The results have been verified using PSPICE version 9.2 at.18 µm technology using supply of 1.8 V. 4.1 Gain: Gain is a measure of the ability of an op-amp to increase the power or amplitude of a signal from the input to the output. Gain is the ratio of the output voltage and the differential input voltage. The dc gain of Proposed Folded Cascode OTA using Self Cascode and DTMOS are shown in Figure 4 and 5. A V = A V = Table 1. Simulated Results of Proposed Folded Cascode OTA Characteristics Self Cascode DTMOS Power supply 1.8 V 1.8 V Power consumption Open gain loop e- 2 W Bandwidth K e- 3 W db 55 db M A V (db) = db 4.2 Power Consumption: Power consumption (PC) is defined as the amount of quiescent power (V in = V) that must be consumed by the OTA in order to operate properly. The amount of average power consumption of Proposed Folded Cascode OTA using Self Cascode technique and DTMOS technique are given in the Table (1.m, ) DB((V(1))- V(11)/V(26)) (39.811K, ) 5. SIMULATION RESULTS Simulation has been done on PSPICE with 1.8V supply voltage. PSPICE simulation results of the circuit confirm the effectiveness of the approach. Proposed Folded Cascode OTA using DTMOS technique shows better performance in terms of gain and bandwidth as compare to Self Cascode technique m 1m 1m 1. 1 Freque ncy 1 1.K 1K Figure 4. Voltage gain using Self Cascode technique 1K 242

4 8 (8.764M,4.37) 4 1.m 1m 1m K 1K 1K 1.M 1M 1M 1.G DB((V(1)-V(11))/V(26)) Frequency Figure 5. Voltage gain and bandwidth using DTMOS technique 6. CONCLUSION In this paper, we have presented low power techniques using Self Cascode and DTMOS, which promises low voltage design with high gain and also high bandwidth. We can use these techniques where area factor is not considered. By using Self Cascode technique the gain of proposed folded cascode is increased with decrease in average power consumption. And by using DTMOS technique, the gain and bandwidth is increased with decrease in average power consumption. This folded cascode circuit have been employed in a variety of situations from increasing the gain in amplifiers with medium available bandwidth. These techniques can extensively be applied where power supply and area requirements are not the constraint and that high gain and average power dissipation is of importance. ACKNOWLEDGEMENTS We would like to thank the faculty of Indira Gandhi Delhi Technical University For Women (IGDTUW) and Head of the Department, ECE to provide the opportunity to use the resources of Institute. REFERENCES [1] P. Soni, M. Bhardwaj and B.P.Singh Design of Enhanced Performance Folded Cascode OTA Amplifier, American Institute of Physics Conference Proceedings, Volume 1324, pp , December 21, ISBN , ISSN X. [2] F. Henrici, J. Becker, and Y. Manoli, A continuous time field programmable analog array using parasitic capacitance Gm-C Filters, in Proc. ISCAS 7,

5 [3] P. Gray and R. Meyerce, analysis and design of analog integrated circuits, New York: John Wiley & sons, [4] V.I. Proddanov and M.M. Green, CMOS current mirrors with reduced input and output voltage requirements Electron. Lett., vol. 32, pp , [5] E.Sanchez-Sinencio, Low Voltage Analog Circuit Design Techniques, IEEE Dallas CAS Workshop, 2. [6] S. S. Rajput and S. S. Jamuar, Design Techniques for Low Voltage Analog Circuit Structures, NSM 21/IEEE, Malaysia, November 21. [7] S. Yan and E. Sanchez-Sinencio, Low Voltage Analog Circuit Design Techniques: A Tutorial, IEICE Transactions on Fundamentals, vol. E83 A, February 2. E. Sanchez-Sinencio and A. G. Andreou, ed., Low Voltage/Low Power Integrated Circuits and Systems. IEEE Press, [9] X. Xie, M.C. Schneider, E. Sanchez- Sinencio, and S.H.K. Embabi, Sound design of low power nested transconductance-capacitance compensation amplifiers, Electronic letters, Vol. 35, pp , June [1] Yan Shouli, Sanchez-Sinencio Edgar, Low voltage Analog Circuit Design Techniques, IEICE Transactions: Analog Integrated Circuits and Systems, vol EOO +A, no.2, pp1-3, Feburary 2. [8] 244