CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC

Transcription

1 CMOS Analog to Digital Converters : State-of-the-Art and Perspectives in Digital Communications ADC Hussein Fakhoury and Hervé Petit C²S Research Group

2 Presentation Outline Introduction Basic concepts of A/D Conversion ADC in digital radio receivers Time-Interleaved ADC Frequency synthesis for A/D Conversion

3 Introduction The practical A/D Converter has 60 years old The first commercial ADC: DATRAC 11-bit, 50-kSPS SAR ADC (vacum tube) Designed by Bernard M. Gordon at EPSCO Dimensions: 48cmx38cmx66cm Price : 8500$ Power : 500W VHS bit, 75-MSPS FLASH ADC (hybrid ICs) Designed by Computer Labs Dimensions: 48cmx43cmx17cm Price : 10000$ Power : 130W (linear power supplies included)

4 Introduction The practical A/D Converter has 60 years old The first complete monolithic ADC ADC bit, 40-kSPS SAR ADC in Bipolar Process Designed by Analog Devices (Paul Brokaw) The most power efficient DS ADC IP ~12-bit,BW=18MHz,3.9mW,0.08mm² Designed by MediaTek in 28nm CMOS

5 Basic concepts of A/D Conversion Two fundamental steps Sampling : Shannon's theorem must be followed to avoid aliasing Quantization : assumed to be an additive white noise process clock signal (f s ) Modulated Signal x(t) N Sampling (f s >2xf b ) Quantization X(f) X(f) X(f) image -f b f b f -f s -f b f b f s f -f b f b f quantization noise Due to quantization only (for a full-scale sine wave input): SNR (db) =6.02xN+1.76dB+10xlog(OSR) resolution Over-Sampling Ratio

6 Basic concepts of A/D Conversion Practical considerations: clock signal purity Due to components noise, the period of an oscillator fluctuates in time In time domain : jitter In frequency domain : phase noise Time domain Frequency domain s(t) jitter S(f) phase noise T s time f s = 1 T s f>0

7 Basic concepts of A/D Conversion Practical considerations: clock signal Effect of clock jitter : in the time domain, the sampling process can bee seen as a mixing of the input signal with the clock signal Sampling with jittered-clock sinusoid input x(t) Non-uniform sampling x(nt s +Ɛ n ) X(f) * phase noise Signal corrupted by phase noise f in f>0 f s f>0 f in f>0 Due to clock-jitter only (full-scale sine wave input) : SNR j = Clock jitter is critical in wideband application! 1 (2pf in s jitter )²

8 Basic concepts of A/D Conversion Practical considerations: components noise and distortion Noise of active and passive components : thermal and flicker noise Non-linear behavior of active components : harmonic distortion sampling quantization Modulated Signal x(t) Noise + Noise + N X(f) X(f) + thermal noise X(f) + flicker noise + phase noise + distortion quantization noise + thermal noise + flicker noise + phase noise + distortion -f b f b f -f b f b f -f b f b f Effective resolution : SNDR= Signal Power Power of (all noise sources+distortion)

9 Basic concepts of A/D Conversion How to judge if an ADC is good or not? The Figure of Merit (FoM) is mostly used as the comparison metric The FoM judges the power efficiency of an ADC ADC architectures : Power FoM= [J/conversion-step] f s_nyquist x2enob

10 ADC in digital radio receivers The ADC is the interface between the RF/Analog processing & DSP The RF carrier is filtered, amplified and down-converted by the RF stages Further baseband analog processing is done before the A/D conversion Demodulation and complex signal processing is done in the digital domain RF carrier CMOS radio IC MIXER Mixed-Signal LNA VGA ADC DIGITAL PROCESSING LO RF ANALOG DIGITAL

11 ADC in digital radio receivers Problematic of RF/Analog processing in Rx Area of Analog/RF blocks do not scale as fast as digital gates Passive components (capacitors, resistors, inductors) consumes a large area Must be redesigned for each CMOS node : increased risks & time-to-market Example : scaling of a a/b/g SoC RF/Analog ~30% chip area RF/Analog ~42% chip area RF/Analog ~31% chip area QUALCOMM ATHEROS L. Nathawad et al., ISSCC nm CMOS MEDIATEK J-W. Lay et al., ASSCC nm CMOS MARVELL SEMICONDUCTOR A. Shirvani et al., CICC nm CMOS

12 ADC in digital radio receivers Why do we need analog conditioning before the ADC: RF carrier MIXER LNA VGA ADC DIGITAL PROCESSING LO ANALOG CONDITIONING

13 ADC in digital radio receivers Why do we need analog conditioning before the ADC: the wanted signal is often received in the presence of strong interferers the received power can be much higher than the ADC Full-Scale Case 1 Strong interferers Strong signal Case 2 ADC Full-Scale Weak signal Case 3 f f weak signal ADC Full-Scale f Without filtering - Potential aliasing into signal - Saturation of the Rx chain Without VGA - Saturation of the ADC - Low SNR when the signal is weak

14 ADC in digital radio receivers Why do we need analog conditioning before the ADC: the wanted signal is often received in the presence of strong interferers the received power can be much higher than the ADC Full-Scale Case 1 Case 2 & 3 Weak signal AAF VGA ADC Full-Scale f>0 f Filter and VGA in front of the ADC Robust and High-dynamic range Rx VGA tracks the optimal SNR Area & Power consuming

15 ADC in digital radio receivers What not digitizing at antenna? LNA MIXER VGA ADC DIGITAL PROCESSING LO Ideal-ADC characteristics - Bandpass shaping - Robust to interferers - Very fast Bandpass DS + advanced CMOS process - Very high dynamic range - Low Power How much??? ADC DIGITAL PROCESSING

16 ADC in digital radio receivers What not digitizing at antenna? Design case: computation of the Dynamic Range (DR ADC ) required at the antenna for a GSM-compliant mobile handset ( MHz band) Max -15dBm DR ADC =87dB -102dBm ADC DIGITAL PROCESSING Estimation of the ADC power consumption: Power ADC =FoMxf sampling x2 ENOB f sampling =1.8GHz FOM =50fJ/conversion-step (state-of-the-art ADC [ISSCC 2012]) Power ADC =1.6W! State-of-the-art GSM Rx power~100mw [ISSCC 2011] Not realistic for portable handsets, but for a non-mobile platform

17 ADC in digital radio receivers Architectural trend in low-power low-cost mobile application LNA MIXER VGA ADC DIGITAL PROCESSING LO Baseband-ADC High dynamic range to digitize wanted signal+interferers LNA MIXER ADC DIGITAL PROCESSING LO Channel selection is done in the digital domain Increase the DR of the ADC is less expensive than increase the order of the filtering However an AAF must be used : CT DS ADC are good candidate!

18 ADC in digital radio receivers State-of-the-art A 5mW CT DS ADC with Embedded 2nd-Order Active Filter and VGA Achieving 82dB DR in 2MHz BW, R. Rajan, S. Pavan [ISSCC 2014] VGA Gain=0-18dB AAF 2 nde order ADC CORE N ADC CORE + 2 nde order AAF +VGA (0-18dB) N Chip micrograph (0.13µm CMOS) Improvements IIP3 10dB FOM 33% Area 22%

19 ADC in digital radio receivers State-of-the-art A DC-to-1GHz Tunable RF DS ADC Achieving DR = 74dB and BW = 150MHz At f 0 =450MHz Using 550mW, H. Shibata et al., Analog Devices [ISSCC 2012] LNA MIXER VGA ADC DIGITAL PROCESSING LO ADC Tunable blocker-tolerant bandpass ADC with integrated LNA and variable gain f 0 = MHz BW~100MHz DIGITAL PROCESSING

20 Area is acceptable for integration in a SoC for mobile application, but the power consumption is too high ADC in digital radio receivers State-of-the-art A DC-to-1GHz Tunable RF DS ADC Achieving DR = 74dB and BW = 150MHz At f 0 =450MHz Using 550mW, H. Shibata et al., Analog Devices [ISSCC 2012] ADC Chip micrograph (65nm CMOS) Performances Summary - f c =0-1GHz - BW =35-100MHz - DR =69-80dB - Filtering=3 rd -6 th order - Power = mW - Area =5.5mm²

21 Time-Interleaved ADC Concept : Introduced by W. C. Black and D. A. Hodges, Time-interleaved converter arrays, [JSSC 1980] M-channel are time-interleaved to increase the speed of the ADC by a factor M while the speed of each individual channel is fixed f s Mxf s F 1 X(t) F 1 F 2 F M F1 F 2 ADC 1 f s F 1 F 2 M samples F M F1 t s =1/f s time ADC 2 M U X t s =1/f s X(n) f s F M ADC M

22 Time-Interleaved ADC Power consumption : single-channel vs TI channels F 1 f s /M f s F 1 F 2 F M CLOCK GEN f s F 1 ADC F 2 F M f s ADC 1 ADC 2 ADC M M U X Specific processing overhead Single-channel ADC Time-Interleaved ADC P ower /f s Single-channel interleaved f s_critical Mxf s_critical f s

23 Time-Interleaved ADC Performance limitation Mismatch between channels due to the fabrication process Introduce spurious tones at the reconstructed output : a specific correction procedure is needed Example : representation of mismatch errors in a 2x Time-Interleaved ADC (M=2): Gain Offset Bandwidth Clock skew F 1 +DF 1 offset 1 f s Mxf s BW 1 G 1 G ADC 1 ADC 2 M U X Specific processing F 2 +DF 2 BW 2 offset 2 f s

24 Time-Interleaved ADC Example with a 2-channel Time-Interleaved ADC : M=2, channel resolution=10-bit, V REF =1V Offset value in channel 1=1mV, the second channel is free of offset Offset=1mV f s F 1 ADC 1 Mxf s F 2 + ADC 2 M U X spurious SFDR =63dBc spurious s /2 f s M tones are created at ixf s /M, with 0 < i < M 1, [1] The SFDR of the ADC is severely degraded

25 Time-Interleaved ADC Two approaches for the correction of mismatch-induced errors Mixed : digital estimation and analog correction Fully-digital : Fully-digital : digital estimation and correction INPUT TI ADC INPUT TI ADC Digital correction DAC Digital estimation Digital estimation Simple Area & power Portability Robust Compatible with CMOS scaling May be complex David Camarero et. al, [2] Han Le Duc et. al, [3]

26 Time-Interleaved ADC Which architecture is best suited to TI channels? what architecture? ADC 1 ADC 2 M U X DSP FLASH SAR PIPELINE DS A few analog components Power efficient Area efficient Robust Slow

27 Time-Interleaved ADC Which architecture is best suited to TI ADC? Single-channel CMOS ADCs presented at ISSCC/VLSI bit 11-bit

28 IP : 4-channel Time-Interleaved 12-bit 4x80-MSPS SAR ADC Time-Interleaved ADC State-of-the-art Synopsys new ADC IP generation in 28nm CMOS: 12-bit 80-MSPS PIPELINE ADC 12-bit 80-MSPS SAR ADC to 28nm CMOS Power x3 Area x6

29 Time-Interleaved ADC State-of-the-art A 1.62GS/s Time-Interleaved SAR ADC with Digital Background Mismatch Calibration Achieving Interleaving Spurs Below 70dBFS, Nicolas Le Dortz et al., ST Microelectronics & Supelec, [ISSCC 2014] Digital part - Area = 53% - Power= 40% Applications : broadband satellite, cable TVs, SDR Correction type ISSCC 13 [1] ISSCC 13 [2] ISSCC 14 THIS WORK digital CMOS node 65nm 65nm 40nm Speed [GS/s] ENOB [bit] Mismatch tones [dbfs] Power [mw] FOM [fj/conv.-step] Chip micrograph (40nm CMOS) Area [mm²]

30 Time-Interleaved ADC State-of-the-art A 90GS/s 8b 667mW 64 Interleaved SAR ADC in 32nm Digital SOI CMOS, Lukas Kull et al., IBM Research & EPFL, [ISSCC 2014] Application : optical communication Process 32nm CMOS SOI Supply 1.2V Input range 0.8V pp-diff Speed ENOB Power FOM Area 90 GS/s ~5-bit 667mW 203fJ/conv.-step 0.45mm² Chip micrograph (32nm CMOS SOI)

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