Designing CMOS Wireless System-on-a-chip
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1 Designing CMOS Wireless System-on-a-chip David Su Atheros Communications Santa Clara, California Santa Clara SSCS (c) D. Su Santa Clara SSCS September 2009 p.1 Outline Introduction CMOS Transceiver Building Blocks LNA and PA System-on-a-chip Integration issues Digital Assistance and Interference Conclusion (c) D. Su Santa Clara SSCS September 2009 p.2 1
2 SoC Trends: GSM (1995) Stetzler et al, ISSCC 95 (AT&T) Integrated Transceiver with external components (e.g. filters) (c) D. Su Santa Clara SSCS September 2009 p.3 SoC Trends: GSM (2006) Bonnaud et al, ISSCC 06 (Infineon) SoC with integrated transceiver and CPU. (c) D. Su Santa Clara SSCS September 2009 p.4 2
3 SoC Trends: WLAN (1996) Prism WLAN chipset (Harris Semi) AMD App Note ( Multi-Chip b Transceiver (c) D. Su Santa Clara SSCS September 2009 p.5 WLAN Integration Story LO I ADC LNA ADC Switch LO LO Q Synthesizer Digital Signal Processor LO I DAC PA RFVGA Su Mehta Chang et al et ISSCC al ISSCC (Atheros) (Atheros) LO Q DAC (c) D. Su Santa Clara SSCS September 2009 p.6 3
4 SoC Trends: WLAN (2008) Nathawad et al, ISSCC 08 (Atheros) 11a/b/g/n (2x2 MIMO) Radio SoC (c) D. Su Santa Clara SSCS September 2009 p.7 Advantages of SoC Integration Increased functionality Smaller Size / Form Factor Lower Power On-chip interface Lower Cost Single package Ease of manufacture Minimum RF board tuning Reduced component count Improved reliability (c) D. Su Santa Clara SSCS September 2009 p.8 4
5 Cost of WLAN Throughput Zargari, 2007 VLSI Symposium Short Course (c) D. Su Santa Clara SSCS September 2009 p.9 Evolution of WLAN PHY Rates n (2.4 and 5GHz) Max PHY Data Rate (Mb/s) a (5GHz) b (2.4GHz) g (2.4GHz) (2.4GHz) Year of Product Introduction (c) D. Su Santa Clara SSCS September 2009 p.10 5
6 Single-chip Radio Block Diagram Transceiver Digital Baseband PHY Digital MAC Digital Interface (c) D. Su Santa Clara SSCS September 2009 p.11 Transceiver Block Diagram Receiver LO I ADC LNA ADC Switch LO LO Q Synthesizer Digital Signal Processor LO I DAC PA RFVGA DAC Transmitter LO Q (c) D. Su Santa Clara SSCS September 2009 p.12 6
7 CMOS Transceiver Building Blocks Signal Amplification Frequency Translation Frequency Selectivity (c) D. Su Santa Clara SSCS September 2009 p.13 CMOS RF Design Advantages Low-cost, high-yield Multi-layer interconnect makes decent inductors High-level of integration supports sophisticated digital signal processing Challenges: Multi-GHz: narrowband design with inductors No high-q BPF: architecture + dynamic range Process/Temp Variation: DSP algorithms Reduced supply headroom: IO devices Noise coupling: careful design & layout (c) D. Su Santa Clara SSCS September 2009 p.14 7
8 Tuned CMOS RF Gain stage Gain V IN Frequency gmv IN R L C L Equivalent Model Use of Inductor Narrowband tuned circuit with higher gain (c) D. Su Santa Clara SSCS September 2009 p.15 LNA Design Goal Low Noise Figure Sufficient gain Able to accommodate large blockers Large Dynamic Range Large Common-mode Rejection High Linearity (c) D. Su Santa Clara SSCS September 2009 p.16 8
9 LNA with Cascoded Diff Pair IN IN BIAS Input match Noise Figure (c) D. Su Santa Clara SSCS September 2009 p.17 LNA with Switchable Gain gain gain gain M1 M2 M3 M4 IN IN BIAS CMRR at RF Switchable gain for high DR Zargari et al, JSSC Dec 2004 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.18 9
10 Linear PA for High Data Rate Modern digital modulation attempts to transmit at highest data rate within a given signal bandwidth. Nonlinear PA: Information in phase only. Transmit with constant envelope for power efficiency GSMK, FSK Modestly Linear PA: Information in phase only. Reduce signal bandwidth with non-constant envelope signal π/4 QPSK, OQPSK Linear PA: May encode information in both amplitude and phase. Non-constant envelope; high SNR 64 QAM (c) D. Su Santa Clara SSCS September 2009 p.19 PA Peak to Average Ratio Improved spectral efficiency (higher bits per Hz) Large peak to average ratio reduces power efficiency of the PA Example: a/g OFDM has PAR of 17dB Class A efficiency of ~ 1% Infrequent signal peaks 16-QAM OFDM, PAR of 6dB degrades SNR by only 0.25dB* Class A Efficiency ~ 12% 64-QAM OFDM, PAR of 12dB is needed Class A Efficiency ~ 3% * Van Nee & Prasad, OFDM for Wireless Multimedia Communications, Artech House, 2000 (c) D. Su Santa Clara SSCS September 2009 p.20 10
11 Linear Design Design for P SAT = P AVE + PAR + - Low R output match Stability - Cascoding Linearity - Avoid V GS overdrive - Inter-stage capacitive level-shift (c) D. Su Santa Clara SSCS September 2009 p.21 Cascoded Power Amplifier L1 L2 RF OUT VDD RF IN M1 M2 Cascoding advantages 3.3V supply voltage Stability Capacitive Level-shift Single-ended equivalent Bias Differential Off-chip balun (c) D. Su Santa Clara SSCS September 2009 p.22 11
12 Cascoded Power Amplifier RF OUT RF OUT Bias2 Bias1 Bias1 Bias2 RF IN RF IN P MAX = 22 dbm P OFDM = 17.8 dbm (BPSK) Zargari et al, JSSC Dec 2002 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.23 Measured Power vs Data Rate OFDM Output Power (dbm) 18 IEEE a dB Power Backoff 14 Spectral mask limited EVM limited db Power Backoff Data Rate (Mbps) (c) D. Su Santa Clara SSCS September 2009 p.24 12
13 Leveraging Integration for RF PA Transistors are cheap. LARGE Output Power: Nonlinear PA HIGH Efficiency: Nonlinear PA GOOD Linearity: Use linearization circuits so that the output stage does not need to be linear. SOLUTION: Switched-mode (non-linear) output stage + linearization. (c) D. Su Santa Clara SSCS September 2009 p.25 PA Linearization Concept: Use efficient nonlinear PAs for amplification Techniques to improve linearity An active research area for over half a century! Some examples: Feedforward Predistortion Cartesian feedback: Rectangular I-Q Outphasing / Chirex / LINC: Phase-Phase Polar: Phase-magnitude, EER (many many more) (c) D. Su Santa Clara SSCS September 2009 p.26 13
14 Polar LF Magnitude RF RF Output Phase RF Power Amplifier Input = PHASE and MAGNITUDE Amplified separately and then combined Ref: L. Kahn, Proc. IRE, July (c) D. Su Santa Clara SSCS September 2009 p.27 Digital Polar Digital Magnitude n RF RF Output Phase Parallel RF Power Amplifier (c) D. Su Santa Clara SSCS September 2009 p.28 14
15 Digitally Modulated Polar Power Amplifier 6 Decoder I Q I/Q to Polar Magnitude Phase PA 1 PA 2 OUT PA 64 Kavousian et al, ISSC 2007 (Stanford) (c) D. Su Santa Clara SSCS September 2009 p.29 Digitally Modulated Polar Power Amplifier L2 Matching Network RF OUT Ctrl1 Ctrl2 Ctrl64 Phase M1 M2 M64 Bandwidth: 20MHz Frequency: 1.6GHz EVM: -26.8dB Power: 13.6dBm Kavousian et al, ISSC 2007 (Stanford) (c) D. Su Santa Clara SSCS September 2009 p.30 15
16 RF PA with Envelope Feedback IN PA OUT Gain Control 1/α Linearizes Gain Fixes gain variation over process and temperature Terrovitis et al, ESSCIRC Sept 2009 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.31 Integrating RF Tx/Rx Switch in CMOS Rx LNA Tx/Rx Switch Tx PA MOS pass transistors as switches has too much loss and may not be able to support required voltage breakdown (c) D. Su Santa Clara SSCS September 2009 p.32 16
17 Integrated RF Tx/Rx Switch LNA OUT Rx Mode Tx/Rx Switch LNA IN M2 M1 b2 b1 π matching network Receive chain noise figure = 5.8dB PA OUT M3 M4 PA off b3 PA IN Chang et al, ISSCC 2007 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.33 Integrated RF Tx/Rx Switch LNA OUT Tx Mode Tx/Rx Switch LNA IN M2 M1 b2 b1 PA OUT Transmit output power = 20dBm (< 1dB loss) M3 M4 b3 PA IN Chang et al, ISSCC 2007 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.34 17
18 System-on-a-Chip Integration Analog/RF DIGITAL Digital Assistance: Calibration Techniques Digital Interference: Noise Coupling (c) D. Su Santa Clara SSCS September 2009 p.35 Digital Assisted Analog Design Analog Design Digital Designer (c) D. Su Santa Clara SSCS September 2009 p.36 18
19 Digital Assistance: Calibration Issues Digital logic to compensate/correct for imperfections of analog and RF circuits can enable: Lower power, smaller area, improved reliability of analog/rf Desired properties of calibration: Independent of temperature, aging, frequency Inexpensive (in area and power) to implement Do not interfere with system performance Wireless SoC advantage: Calibration building blocks already exist on-chip: transmitter and receiver, data converters, and CPU No package pin limitation (c) D. Su Santa Clara SSCS September 2009 p.37 Calibration Techniques Test Signal Dedicated test signals from DAC: Tx carrier leak RF loop back: Receive filter bandwidth Thermal noise: Rx Gain Live Rx (signal) traffic: Rx I/Q mismatch Observation Signal Dedicated ADC Implicit ADC: Comparator Tuning Mechanism Dedicated DAC Implicit DAC: Selectable capacitors, resistors, transistors (c) D. Su Santa Clara SSCS September 2009 p.38 19
20 RF loop back: Tx Carrier Leak LO LNA + ADC RX Carrier Leak Correction PA LO DAC Test signal: Tx DAC Observation signal: RF loop back to Rx ADC Tuning: Carrier Leak Correction at Tx DAC input + TX Digital Baseband (c) D. Su Santa Clara SSCS September 2009 p.39 Calibrating Low-pass gm-c Filter Ref Clock Replica Biquad Phase Detector State Machine Capacitor setting IN OUT Low-Q Biquad High-Q Biquad Transresistance Amplifier I in -g m2 g m3 g m4 I out g m1 Zargari et al, JSSC Dec 2004 (c) D. Su Santa Clara SSCS September 2009 p.40 20
21 System-on-a-Chip Integration Analog/RF DIGITAL Digital Assistance: Calibration Techniques Digital Interference: Noise Coupling (c) D. Su Santa Clara SSCS September 2009 p.41 Digital Interference Digital Analog (c) D. Su Santa Clara SSCS September 2009 p.42 21
22 Digital Interference: Noise Coupling Aggressor Accomplice Victim (c) D. Su Santa Clara SSCS September 2009 p.43 Pacify the aggressor Noise Source Reduce noise by turning off unused digital Clock gating Avoid oversized digital buffers Stagger digital switching Avoid large number of digital pads switching simultaneously Avoid switching digital logic at the same sampling instance of sensitive analog (c) D. Su Santa Clara SSCS September 2009 p.44 22
23 Noise Destination Strengthen the victim Increase immunity of sensitive analog and RF circuits Common-mode noise rejection: Fully differential topology Power Supply noise rejection: Good PSRR Dedicated on-chip voltage regulators Avoid package coupling by keeping sensitive nodes on chip (Example: VCO control voltage) (c) D. Su Santa Clara SSCS September 2009 p.45 Coupling Mechanism Deter the accomplice Supply noise coupling Separate or star-connected power supplies Capacitive or inductive coupling to sensitive signals and bias voltages Careful routing of signal traces to reduce parasitic capacitive/inductive coupling Use ground return-path shields (c) D. Su Santa Clara SSCS September 2009 p.46 23
24 Coupling Mechanism (Cont d) Epi vs non-epi substrate Substrate coupling induced V TH modulation Low-impedance substrate connection Guard rings Physical separation Deep Nwell (c) D. Su Santa Clara SSCS September 2009 p.47 Frequency Synthesizer Xtal Osc Reg1 Reg2 Ref Div DFF PFD CP VCO 40MHz On-chip Loop Filter 16/17 Divider Retiming FFs DFF P & S Counter 8/8.5 Div / 2 f vco/4 I Q LO Buffers Terrovitis et al, ISSCC 2004 (Atheros) (c) D. Su Santa Clara SSCS September 2009 p.48 24
25 Conclusions CMOS has become the technology of choice for integrated radio systems Integrating a radio in mixed-signal System-on-a-Chip is no longer a dream but a reality Wireless SoC can provide significant advantages in size, power, and cost (c) D. Su Santa Clara SSCS September 2009 p.49 Continuing Challenges Multi-mode radios to support several wireless standards RF design in scaled CMOS Reduced supply voltage: voltage, current, time nanometer transistors: leaky, low gm.ro How to reduce analog/rf area and power: less analog and more digital Challenge of radio designers will still be: Power consumption / Battery life Range Data rate Cost (c) D. Su Santa Clara SSCS September 2009 p.50 25
26 Acknowledgments Many of the slides are based on previous presentations from Atheros Communications and Stanford University, especially those by: Manolis Terrovitis, Srenik Mehta, William Si, William McFarland, Lalitkumar Nathawad Richard Chang Amirpouya Kavousian (c) D. Su Santa Clara SSCS September 2009 p.51 26
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