60 GHz TX. Waveguide Transmitter Module. Data Sheet Features V60TXWG3. Applications. VubIQ, Inc

Transcription

1 Features Complete millimeter wave transmitter WR-, UG-8/U flange Operates in the to GHz unlicensed band dbm typical output power Up to.8 GHz modulation bandwidth I/Q analog baseband interface On chip synthesizer covers to.8 GHz MHz or MHz step size 8. MHz clock for MHz step size 8. MHz clock for MHz step size Power, control, signals on ST connector Temperature sensor Compact Waveguide Transmitter Applications 8.ad: 8.,.8,.,.8 GHz 8.aj: 9.9,.,.,.8 GHz Any Channel ( MHz or MHz) -.8 GHz Multi-Gbps Digital Communications HD Video Transmission Millimeter Wave Radar Millimeter Wave Imaging Development for 8.ad and 8.aj ATE Equipment for GHz Manufacturing Test The is a highly integrated millimeter wave transmitter that covers the GHz global unlicensed spectrum allocations packaged in a standard waveguide module. Transmitter architecture is a double conversion, sliding IF with wide bandwidth capability through the upconversion chain from baseband to carrier. The I/Q interface accepts analog baseband signals which provides for flexibility in design and applications. The baseband input optionally supports FSK/MSK modulation for non-coherent applications. The transmitter incorporates a complete waveguide interface with low-loss transition between the chip and the WR waveguide port. The integrated package is small and lightweight, with a simple to use multi-pin ST connector for power, reference clock, digital control port and baseband signals. Either of two reference clocks can be used for setting MHz or MHz channel spacing. VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

2 G G WR- UG-8/U Flange." (.8 mm)." (9. mm).9" (. mm) Samtec ST- Connector.9" (. mm).9" (. mm)." (9. mm)." (8. mm) Pin G FIGURE MECHANICAL DIMENSIONS VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

3 G Samtec ST- Pin.V.V V V.V.V.V.V.V.V.V.V VCC VDD VCC_PA VCC_PA VCC VCC VCC VCC VCC VCC VCC VDD CLK DATA SCANOUT BB_QM BB_QP BB_IM BB_IP FMM_Q FMP_Q FMM_I FMP_I REFCLKM REFCLKP Q_E Q_B_C RESET ENABLE Mating Connector: Samtec SS--.-L-D-K-TR FIGURE INTERFACE CONNECTOR PINOUT VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

4 Table Performance Specifications* Parameter Min Typ Max Unit Comment Frequency Range..8 GHz Channel Spacing MHz 8. MHz Reference Channel Spacing MHz 8. MHz Reference Modulation Bandwidth.8 GHz Max BW setting, double-sided at db Gain, Max 8 db Gain, Range db Gain, Step Size. db PdB dbm Psat dbm Image Rejection db Sideband Suppression db Carrier Suppression db x LO Suppression db Phase khz - dbc/hz Phase MHz -8 dbc/hz Phase MHz - dbc/hz Phase MHz - dbc/hz Phase GHz - dbc/hz PLL Loop Bandwidth khz I/Q Balance Phase I/Q Balance Amplitude ± ± degrees db Gain = P out - P in (I/Q differential input) *Test Conditions: Reference Frequency 8. MHz Temperature C I/Q Input Signal Level Referenced to - dbm x at each ohm input port IF Bandwidth Max Output Referenced to WR output port VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

5 Table Recommended Operating Conditions Description Power Supplies Serial Control Port Logic High Serial Control Port Logic Low Name Vcc Vdd DATA CLOCK ENABLE RESET SCANOUT DATA CLOCK ENABLE RESET SCANOUT ST Pin # 8,,,, 8,,, Min Typ Max...8 Unit... V Vcc_PA,,,8.9.. V V V V Serial Control Port Speed MHz REFCLKM Reference Clock REFCLKP - dbm BB_QM I and Q Baseband BB_QP BB_IM mvpp BB_QP 9 FMM_Q FM/MSK Baseband FMP_Q FMM_I 9 mvpp FMP_I Q_E Temperature Sensor Q_B_C Vcc.V Supply Current Icc 9 ma Vdd.V Supply Current Idd 8 ma Vcc_PA V Supply Current I PA ma Operating Temperature - 8 C T A Reference clock power level specified at ohms differential Baseband voltage at each of the individual baseband inputs (I +/-, Q +/-, FMI +/-, FMQ +/-) Temperature sensor is a N9 NPN transistor die connected as a diode junction VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

6 Table Absolute Maximum Ratings VubIQ, Inc Irvine Blvd, Irvine, California 98 USA

7 Transmitter Architecture The transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The LO and IF are generated from a built-in synthesizer that has a step size at the RF carrier frequency of either MHz or MHz depending upon which reference clock frequency is used. The MHz step size uses a 8. MHz reference, and the MHz step uses a 8. MHz frequency. The IEEE channels for 8.ad and 8.aj are supported when the MHz step size is used. I and Q analog baseband signals are upconverted to the IF frequency at the input mixers. The IF signal is filtered with a variable gain amplifier and filter with approximately db range, which is then mixed with the LO. A notch filter attenuates the image frequency. The output of the mixer is fed to the PA stage which is coupled to the low-loss waveguide transition. There are optional FSK/MSK baseband data inputs for non-coherent modulation applications. The overall phase noise and I/Q balance specifications are sufficient for up to QAM operation. Configuration and settings are controlled through a digital serial interface port. The block diagram below shows the various stages and circuits in the module. REFCLKP REFCLKM Synthesizer. to.8 GHz. or. GHz step Div x BB_IP BB_IM PA WR- Waveguide UG-8/U Flange 9 BB_QP BB_QM IF VGA Var IF Filter FMP_Q FMM_Q FMP_I FMM_I Serial Control Registers RESET ENABLE FIGURE BLOCK DIAGRAM CLOCK DATA SCANOUT VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

8 Synthesizer Design The transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at / the RF carrier frequency, and the VCO is at / the RF carrier frequency. The LO is x the VCO frequency. The tables below show the RF carrier, IF, VCO and LO for the frequency range from GHz to.8 GHz at MHz and MHz channel spacing respectively. The reference clock for the synthesizer at MHz spacing is 8. MHz; for MHz spacing it is 8. MHz. The loop bandwidth of the synthesizer phase lock loop is khz. MHz Spacing MHz Spacing frf IF VCO LO frf IF VCO LO VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

9 Digital Control Registers and Serial Interface Protocol Write Operation The is configured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. Register locations are organized into, byte-wide (8-bit) locations. The register locations are written to or read from one byte at a time as shown in Figures and respectively. Figure shows the sequence of the digital control signals for the ENABLE, CLOCK and DATA input pins (ST connector, pins 9, and 8 respectively) to write a single byte into the control register. After the ENABLE signal goes low, the first of 8 data bits (bit ) is placed on the data pin, and ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit. The DATA signal must remain stable for at least ns after the rising edge of the CLOCK. The signal levels are.v CMOS, kω impedance, with a maximum clock rate of MHz. A write operation requires an 8 bit field associated with 8 clock pulses as shown in Figure. The 8 bit field contains the 8-bit data (LSB is clocked in first), followed by the byte address (BYTE through BYTE, to, LSB first, only of the bits are used with the two MSBs set to ), the read/write (R/W) bit (write = ), and the module address which distinguishes between a transmitter module and receiver module (for the VRXWG receiver, RX module = ). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module. The CLOCK signal must be stable in the low state at least ns prior to the rising edge of the ENABLE signal. ENABLE CLOCK DATA 8 9 Data Byte Address R/W TX/RX Module LSB MSB LSB MSB LSB MSB FIGURE WRITE OPERATION TIMING DIAGRAM 9 VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

10 Digital Control Registers and Serial Interface Protocol Read Operation Figure shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register location. A read operation requires a bit field: The first 8 bits are used to clock in the bits on the DATA input pin. The first 8 bits during a read operation are don t care bits as they are placeholders for the 8-bit byte data which would be present during a write operation. The following bits are composed of the byte address (BYTE through BYTE, to, LSB first, only of the bits are used with the two MSBs set to ), the read/write (R/W) bit (read = ), and the module address which distinguishes between a transmitter module and receiver module (for the transmitter, TX module =, LSB first). After clock pulse (8 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single clock pulse (pulse 8) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock pulse 8 through. Following clock pulse, the ENABLE signal goes high while the CLOCK signal is low to end the read operation. ENABLE 8 CLOCK DATA 8 9 Data Byte Address R/W TX/RX Module SCAN OUT LSB MSB LSB MSB LSB MSB Read Data LSB MSB FIGURE READ OPERATION TIMING DIAGRAM VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

11 Table. Register Byte Functions Bit Name BYTE pa_pwrdn BYTE BYTE pa_pwrdn_fast mixer_pwrdn divider_pwrdn if_bgmux_pwrdn if_mixer_pwrdn driver_pwrdn ifvga_pwrdn ipc_pwrdn tripler_pwrdn ifvga_q_cntrl_ ifvga_q_cntrl_ ifvga_q_cntrl_ not used not used not used fdb_ fdb_ fdb_9 fdb_8 pa_sel_vgbs_ pa_sel_vgbs_ pa_sel_vgbs_ pa_sel_vgbs_ Active high to power down PA circuits not controlled by bit <> Active high to power down PA core in < us Active high to power down IF to RF mixer Active high to power down local oscillator divider Active high to power down one of three on-chip refs (IF) and associated mux Active high to power down baseband to IF mixers Active high to power down PA predriver Function Active high to power down IF variable gain amplifier Active high to power down module current reference generator Active high to power down frequency tripler IF filter Q in the VGA amplifier; bits <:> = for highest Q and gain For reduced Q and wider bandwidth, bits <:> =,,, in sequence Not used; bits <:> = xxx Reserved; bits <:> = for normal operation PA output transistors base voltage regulator; bits <:> = for normal operation VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

12 Table. Register Byte Functions Bit Name BYTE BYTE BYTE fdb_ fdb_ fdb_ fdb_ fdb_ fdb_ fdb_ fdb_ pa_sel_vref_ pa_sel_vref_ pa_sel_vref_ pa_sel_vref_ driver_bias_ driver_bias_ driver_bias_ driver_bias_ not used not used not used not used bg_monitor_set if_refsel enable_fm not used Function Reserved: bits <:> = for normal operation Reserved: bits <:> = for normal operation PA output transistors bias current; bits <:> = for normal operation PA predriver bias current; bits <:> = for normal operation PA predriver bias current; bit <> = for normal operation Not used; bits <:> = xxxx Reserved: bits <:> = for normal operation Active high to enable FM/MSK modulator inputs; bit <> = for normal I/Q Not used; bit <> = x VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

13 Table. Register Byte Functions Bit Name BYTE BYTE BYTE 8 ifvga_bias_ ifvga_bias_ ifvga_bias_ ifvga_bias_ ifvga_tune_ ifvga_tune_ ifvga_tune_ ifvga_tune_ ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_ ifvga_vga_adj_ rfmix_tune_ rfmix_tune_ rfmix_tune_ rfmix_tune_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_9 tripler_bias_8 tripler_bias_ tripler_bias_ Function IF VGA bias ; bits <:> = for normal operation IF VGA filter ; bits <:> = for normal operation IF VGA gain control bits; bits <:> = highest gain, lowest gain Attenuation. db/step, db maximum IF filter alignment in the RF mixer; bits <:> = for normal operation Frequency tripler bias (upper 8 bit portion): bits <:> = default VubIQ, Inc sales@vubiq.comvubiq, Inc Irvine Blvd, Irvine, California 98 USA 9 Irvine Blvd, Irvine, California 98 USA

14 Table. Register Byte Functions Bit Name BYTE 9 BYTE BYTE tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ tripler_bias_ driver_bias_ driver_bias_ rdacin_ rdacin_ rdacin_ rdacin_ rdacin_ rdacin_ synreset divratio_ divratio_ divratio_ divratio_ divratio_ band_ band_ band_ rfseldiv Function Frequency tripler bias (lower bit portion): bits <:> = default PA predriver bias current; bits <:> = for normal operation VCO amplitude DAC; bits<:> = for normal operation Synthesizer reset; bit <> = for normal operation Synthesizer divider ratio bit (see Tables. and.) Synthesizer divider ratio bits : (see Tables. and.) VCO band tuning bits : (see Tables. and.) Reserved; bit <> = for normal operation VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

15 Table. Register Byte Functions Bit Name BYTE BYTE BYTE cpbias_ cpbias_ cpbias_ vrsel_ vrsel_ vrsel_ vrsel_ refselvco muxref div_ en_dc ini pd_div_ pd_div_ pd_qp pd_vco pd_cal muxout pdcalc pload wide_ wide_ slew_ slew_ Function Synthesizer charge pump bias; bits <:> = for normal operation Synthesizer lock detector window width; bits <:> = for normal operation Reserved; bit <> = for normal operation Reserved; bit <> = for normal operation Enable synthesizer divider bit ; bit <> = for normal operation Synthesizer reference input DC coupling; bit <> = for normal operation Reserved; bit <> = for normal operation Active high to power down.v circuits in synthesizer divider Active high to power down.v circuits in synthesizer divider Active high to power down synthesizer charge pump Active high to power down synthesizer VCO Active high to power down VCO calibration; bit <> = for normal operation Multiplexer control for ability to read byte ; bit <> = for normal operation Active high to power down VCO ALC; bit <> = for normal operation Active high to load adjustment of VCO; bit <> = for normal operation Control for VCO ALC loop; bits <:> = for normal operation Slew rate control of sub-integer N divider; bits <:> = for normal operation VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

16 Table. Register Byte Functions Bit Name BYTE comp_p comp_n rdacmsb_ rdacmsb_ rdacmsb_ rdacmux_ rdacmux_ rdacmux_ Reserved (read only) Function Synthesizer lock indication (read only): bits <:> = locked, = above window, = below window, = disallowed indicating error VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA

17 Table. MHz Channels Channel Divider Byte Band Byte Reference: 8. MHz Note : Band setting typical, may change from module to module and temperature. Note : Operation above GHz not guaranteed over full operating temperature range. Table. MHz Channels Channel Divider Band Byte Byte Reference: 8. MHz Note : Band setting typical, may change from module to module and temperature. VubIQ, Inc sales@vubiq.com 9 Irvine Blvd, Irvine, California 98 USA