Rev. No. History Issue Date Remark. 0.0 Initial issue January 3, 2002 Preliminary

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1 Preliminary Mouse, Keyboard Transmitter Document Title Mouse, Keyboard Transmitter Revision History Rev. No. History Issue Date Remark 0.0 Initial issue January 3, 2002 Preliminary Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer. PRELIMINARY (January, 2002, Version 0.0) AMIC Technology, Inc.

2 Preliminary Mouse, Keyboard Transmitter Typical Applications Mouse, keyboard transmitter Free Wind Game General Description The A73P24P01 is a monolithic CMOS integrated circuit intended for use as a low cost FSK transmitter in wireless keyboard, mouse and joystick applications. The device is provided in 32-lead plastic QFN5X5 packaging and is designed to provide a fully functional FSK transmitter. The chip is intended for applications in the 2.4GHz to 2.5GHz ISM band. The chip features a fully programmable synthesizer with integrated oscillator circuitry. Pin Configurations DATAIN NC DATAOUT 2 23 NC GND_CHP VDD_CHP Vt BP_BGI XO GND VDD CLK GND_VCO 7 18 EN GND_VCO DATA GND_VCO VDD_VCO RFOUTP RFOUTN GND_VCO BP_BG2 VDD_A GND_A REF_L REF_H BP_VAR VARIN VDD_XTAL GND_XTAL XI NC A73P24P01Q PRELIMINARY (January, 2002, Version 0.0) 1 AMIC Technology, Inc

3 Block Diagram GND VDD Vt EN CLK DATA DATAIN DATAOUT VARIN BP_VAR REF_L REF_H Data Process SP1 VCO AMP RFOUTP RFOUTN PLL XO XI GND_XTAL VDD_XTAL X'tal OSC VDD_VCO GND_VCO 10 7, 8, 9, BP_BG2 Bandgap2 Bandgap1 BP_BG1 6 GND_CHP VDD_CHP GND_A VDD_A PRELIMINARY (January, 2002, Version 0.0) 2 AMIC Technology, Inc

4 Preliminary Specification for RF A73P24P01 IC Parameter Description Min. Typ. Max. Unit General Storage Temperature C Operation Temperature C Supply voltage Tx V Current consumption Tx Active ma Tx Sleep µa BB Interface VDD GND Data I²C PLL en I²C PLL data I²C PLL CLK I²C Modulation FSK Reference Frequency 10,12,14,16 MHz X tal accuracy +/- 10 ppm Frequency Deviation +/- 75 KHz Data Rate Kbps Distance 3 meter Operation Frequency 2416~2478 MHz Number of Channel 32 MHz Channel Space 2 MHz RF I/O impedance Differential 100 ohm Tx Power dbm 2 nd -47 dbm 3 rd -30 dbm Adjacent channel -53 dbm Residue FM Noise 1 KHz Channel hop time 10 ms VCO offset -85 offset -120 dbc/hz PRELIMINARY (January, 2002, Version 0.0) 3 AMIC Technology, Inc

5 Pin Descriptions Pin No. Symbol Function Description 1 DATAIN Data input 2 DATAOUT Recovered data output 3 GND_CHP Ground connection for charge pump circuit. 4 VDD_CHP Supply voltage for charge pump circuit. 5 Vt Tuning voltage for PLL circuit. 6 BP_BGI Bias voltage reference pin for bypassing. The bypass capacitor should be of appropriate size to filter the voltage ripple. 7, 8, 9, 13 GND_VCO Ground connection of Voltage Controlled Oscillator. 10 VDD_VCO Supply voltage for Voltage Controlled Oscillator. 11 RFOUTP Differential RF output 2 12 RFOUTN Differential RF output 1 14 BP_BG2 Bias voltage reference pin for bypassing. The bypass capacitor should be of appropriate size to filter the voltage ripple. 15 VDD_A Supply voltage for analog circuit. 16 GND_A Ground connection of analog circuit. 17 DATA Serial data port. 18 EN Latched data for the serial port. 19 CLK Clock data for the serial port. 20 VDD Supply voltage for digital circuit. 21 GND Ground connection of digital circuit. 22 XO Terminal 2 of crystal. 23, 24, 25 NC No Connection 26 XI Terminal 1 of crystal. 27 GND_XTAL Ground connection of crystal. 28 VDD_XTAL Supply voltage for crystal. 29 VARIN Data pin after shaping 30 BP_VAR Varactor pin for DC bypassing. 31 REF_H The highest voltage for the modulation range 32 REF_L The lowest voltage for the modulation range Absolute Maximum Ratings Parameter Rating Unit Supply voltage 5 Vdc Other I/O pins VSS-0.3, VDD+0.3 Vdc Maximum input RF, LO level 10 dbm Operating ambient temperature -10 ~ +60 C Storage temperature -20 ~ +70 C Specification temperature 0 ~ +50 C PRELIMINARY (January, 2002, Version 0.0) 4 AMIC Technology, Inc

6 Circuit Description 1. Serial to Parallel Interface (SPI) A73P24P01 The signals EN, CLK, DATA comprise the serial interface by which the baseband controller can initiate the accesses to the registers in the SPI. Data registers in the SPI are specified in the following table: Register Number of Bits Comments R_VCO 1 [ cntr0 ] 2 [ cntr1 : cntr2 ] cntr0: adjust the gain of VCO output buffer 1: High gain, 0:Low gain cntr1 cntr2 : reserved R_CHP 1 [ cntr3 ] cntr3 : setting the output current of charge pump 1:High current 300uA; 0:Low current 200uA R_TEST 1 [ts] ts: setting test mode while in product testing R_PLL_M 1:normal mode;0:testing mode 12 [ma0:ma4] [mb0:mb6] ma0 ma4 : setting A counter of the main counter R_PLL_R 12[ ra0:ra4 ] Setting the R counter mb0 mb6 : setting B counter of the main counter R_ADDR 2 [a0:a1] Setting which of the register will be loaded from the serial programming DATA: when a0=1,a1=1, register R_PLL_M is loaded. when a0=1,a1=0,register R_PLL_R is loaded. when a0=0,a1=0,register R_VCO,R_CHP loaded. After setting the EN signal to Low state, the DATA is transferred bit by bit on the rising edge of the CLK signal into the shift register of SPI starting with the MSB bit. When the EN signal has returned to High state, the data packet is loaded into the addressed register shown in the table above according to the register R_ADDR information. Additional leading bits are ignored and the number of the pulse CLK arrived is not being checked during EN low state. The data packet of DATA signal was shown as follows: a. The data packet information for the PLL main counter data (R_PLL_M). MSB Data bits LSB Address bits D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 R_PLL_M for B counter R_PLL_M for A counter R_ADDR mb6 mb5 mb4 mb3 mb2 mb1 mb0 ma4 ma3 ma2 ma1 ma0 1 1 b. The data packet information for the PLL R counter data (R_PLL_R) MSB LSB Data bits Address bits D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 R_PLL_R R_ADDR x x x x x x x ra4 ra3 ra2 ra1 ra0 0 1 Where x means don t care. PRELIMINARY (January, 2002, Version 0.0) 5 AMIC Technology, Inc

7 c. The data packet information for the other data (R_TEST, R_VCO, R_CHP) MSB LSB Data bits Address bits D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 Don t care R_CHP R_VCO R_TEST R_ADDR x x x x x x x icp cntr2 cntr1 cntr0 test 0 0 Where x means don t care. The three signal EN, CLK, DATA timing diagrams are shown as follows: VH N13:MSB N12 N10 N9 N8 N0(C0):LSB VL DATA CLK tcwl EN tcs tch tcwh tew tes The three wire CLK,DATA,EN timing diagrams The timing parameter specification shown in the following table: Value Symbol Parameter Conditions Min. Typ. Max. Units VH The High level of voltage Three wire CLK, DATA, EN timing diagram VCC-0.4 V VL The low level of voltage Three wire CLK, DATA, EN timing diagram 0.4 V tcs DATA to CLK setup time Three wire CLK, DATA, EN timing diagram 50 ns tch CLK to DATA hold time Three wire CLK, DATA, EN timing diagram 10 ns tcwh CLK pulse width high Three wire CLK, DATA, EN timing diagram 50 ns tcwl CLK pulse width low Three wire CLK, DATA, EN timing diagram 50 ns tes CLK to EN setup time Three wire CLK, DATA, EN timing diagram 50 ns tew EN pulse width Three wire CLK, DATA, EN timing diagram 50 ns PRELIMINARY (January, 2002, Version 0.0) 6 AMIC Technology, Inc

8 2. PLL Section The sub-block diagram of PLL is shown as follows: Reference X tal Input R Counter 5 Bit VCO Input PRESCALER 32/33 A Counter 5 Bit B Counter 7 Bit Phase Detector Charge Pump VOUT M counter Control Logic a. PRESCALER 32/33 The dual modulus pre-scalar 32/33 with 5 bits A counter and 7 bits B counter consist of the divided by N counter (where N = B*32+A). The reference frequency for phase detector is set to 1MHz (that is the channel spacing for VCO is 1 MHz). In order to cover the 2.4GHz ISM band frequency range, the value N is designed to be in the range 2400 ~ That requires 5 bits and 7 bits the programmable A, B counter respectively. This pre-scalar is implemented in differential current mode logic topology. With appropriate logic swing, it can operate up to 3GHz maximum frequency and then handle the input signal down to a manageable frequency for CMOS logic A and B counters (100MHz below). b. A and B counters The A and B counters can be programmed through the register R_PLL_M in the SPI block. The corresponding relation between the division ratio of counters and the bits of the register R_PLL_M are shown in the following table: Main counter N B counter A counter B counter of R_PLL_M A counter of R_PLL_M (dec) (dec) (dec) mb6 mb5 mb4 mb3 mb2 mb1 mb0 ma4 ma3 ma2 ma1 ma PRELIMINARY (January, 2002, Version 0.0) 7 AMIC Technology, Inc

9 The maximum frequency counter that A and B can operate is about 200MHz which is enough for the output signal from prescalar. c. R counter The corresponding relationships between the division ratio of counters and the bits of the register R_PLL_R are shown in the following table: R counter division R R_PLL_R register bits (dec) ra4 ra3 ra2 ra1 ra Division ration of R counter from 2 to 31 are allowed. d. Phase Frequency Detector (PFD) and Charge Pump The PFD takes operation of both inputs from R counter and main counter N, producing an output signal proportional to their phase and frequency difference. The following show a simplified schematic. VH D1 Q1 UP VCK CLR2 Delay Element Charge Pump IOUT VH CLR2 D1 Q1 DN RCK PRELIMINARY (January, 2002, Version 0.0) 8 AMIC Technology, Inc

10 The PFD output waveform show below. VCK RCK UP DN IOUT 3. Crystal Oscillator Section The simplified block diagram is shown in the following figure xi xo C1 C2 Pierce Crystal Oscillator Circuit The on-chip amplifier with an appropriate crystal may be used to provide a reference source frequency. The crystal is connected in parallel resonant fundamental mode. The user can also share the reference signal from the Baseband oscillator circuit. The reference signal can be ac coupled to xi pin through a serial capacitor. It can also be directly connected to xi pin for standard CMOS logic levels. In the both cases, the xo pin (the amplifier out) should be left floating. PRELIMINARY (January, 2002, Version 0.0) 9 AMIC Technology, Inc

11 4. Data Process Section A73P24P01 The data process section is composed of OP amplifiers, varactor diodes and switch. The OP amplifier buffers the DC level that is set by external resistors in order to drive the varactor diode. The data rate can then be increased up to 60KHz/bit by this technique. DATAIN R1 REF H + - R3 R2 DATAOUT R4 REF L VCO and Output Buffer Cntr0 RfoutP RfoutN To pre-scalar A 2.4GHz fully integrated VCO with two output buffer amplifiers was included in this chip. The gain of output buffer can be changed by the bit cntr0 from SPI. PRELIMINARY (January, 2002, Version 0.0) 10 AMIC Technology, Inc

12 Ordering Information Part No. A73P24P01Q Package 32L QFN PRELIMINARY (January, 2002, Version 0.0) 11 AMIC Technology, Inc

13 Package Information QFN 32L Outline Dimensions unit: inches/mm B D D D1 E E1 aaa C A 4X c A3 A A2 L b A1 D aaa C Detail B See Detail B D 0.08 C A C Seating Plane D2 bbb M C A B E2 e See Detail A Detail A 0.6max 0.6max b Symbol Dimensions in inches Dimensions in mm Min Nom Max Min Nom Max A A A A b D BSC 5.00 BSC D BSC 4.75 BSC D E BSC 5.00 BSC E BSC 4.75 BSC E e BSC 0.5 BSC L θ aaa bbb chamfer PRELIMINARY (January, 2002, Version 0.0) 12 AMIC Technology, Inc