ISM Band FSK Receiver IC ADF7902
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1 ISM Band FSK Receiver IC FEATURES Single-chip, low power UHF receiver Companion receiver to ADF7901 transmitter Frequency range: MHz to MHz Eight RF channels selectable with three digital inputs Modulation parameters supported FSK demodulation 2 kbps data rate 34.8 khz frequency deviation 5.0 V supply voltage Low power consumption 18.5 ma with receiver enabled 1 μa standby current 24-lead TSSOP GENERAL DESCRIPTION The is a low power UHF receiver. The device demodulates frequency shift keyed (FSK) signals with 34.8 khz frequency deviation and at data rates of up to 2 kbps. There are eight specific RF channels ranging from MHz to MHz on which the receiver can operate. Each channel is selectable by configuring three digital control lines. The is designed for low power applications, consuming 18.5 ma (typical) during normal operation and 1 μa (maximum) in standby mode. FUNCTIONAL BLOCK DIAGRAM GND CE LNA_1 LNA_2 LNA IF FILTER FSK DEMODULATOR Rx_DATA VBAT1 CREG1 VBAT2 CREG2 LDO1 LDO2 N DIVIDER SELECT CH1_SEL CH2_SEL CH3_SEL LNA_RSET BIAS VCO CP PFD OSC CLKOUT CLKOUT_ENB RSET CVCO VCOIN CPOUT OSC1 OSC Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.
2 * PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS Evaluation Board DOCUMENTATION Data Sheet : ISM Band FSK Receiver IC SOFTWARE AND SYSTEMS REQUIREMENTS ADF70xx Evaluation Software ADIismLINK Development Platform TOOLS AND SIMULATIONS ADIsimSRD Design Studio REFERENCE MATERIALS Technical Articles Low Power, Low Cost, Wireless ECG Holter Monitor RF Meets Power Lines: Designing Intelligent Smart Grid Systems that Promote Energy Efficiency Smart Metering Technology Promotes Energy Efficiency for a Greener World The Use of Short Range Wireless in a Multi-Metering System Understand Wireless Short-Range Devices for Global License-Free Systems Wireless Short Range Devices and Narrowband Communications DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
3 TABLE OF CONTENTS Features... 1 General Description... 1 Functional Block Diagram... 1 Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 4 ESD Caution... 4 Pin Configuration and Function Descriptions... 5 Typical Performance Characteristics...6 Applications Information...7 Applications Circuits...7 Test Modes...9 Outline Dimensions Ordering Guide REVISION HISTORY 1/07 Revision 0: Initial Version Rev. 0 Page 2 of 12
4 SPECIFICATIONS VDD =5.0 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Typical specifications TA = 25 C. Table 1. Parameter Min Typ Max Unit Test Conditions CHANNEL FREQUENCIES Channel MHz Channel MHz Channel MHz Channel MHz Channel MHz Channel MHz Channel MHz Channel MHz RECEIVER PARAMETERS Data Rate 2 kbps Frequency Deviation 34.8 khz Data = khz Data = 1 Input Sensitivity 110 dbm LNA Input Impedance 128 j125 Ω frf = MHz CHANNEL FILTERING IF Filter Bandwidth 200 khz 3 db bandwidth Adjacent Channel Rejection 60 db 1 MHz offset Desired signal 3 db above input sensitivity level, with interferer power increased until BER = 10 3 PHASE-LOCKED LOOP CE High to Receive Data 4 ms REFERENCE INPUT Crystal Reference MHz ±25 ppm frequency accuracy INPUT LOGIC LEVELS Input High Voltage, VIH 0.7 VDD V Input Low Voltage, VIL 0.2 VDD V OUTPUT LOGIC LEVELS Output High Voltage, VOH 4.5 V Output Low Voltage, VOL 0.4 V Output Drive Level 2 ma POWER SUPPLY Voltage Supply VDD 5 V Current Consumption Receiver Enabled 18.5 ma CE = 1 Low Power Sleep Mode 1 μa CE = 0 Rev. 0 Page 3 of 12
5 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 2. Parameter Rating VBAT to GND V to +6.0 V Digital I/O Voltage to GND 0.3 V to VBAT V LNA_1, LNA_2 0 dbm Operating Temperature Range Industrial (B Version) 40 C to +85 C Storage Temperature Range 40 C to +125 C Maximum Junction Temperature 125 C TSSOP θja Thermal Impedance C/W Lead Temperature, Soldering Vapor Phase (60 sec) 235 C Infrared (15 sec) 240 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1 GND = GND1 = GND1B = GND2 = 0 V. Rev. 0 Page 4 of 12
6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CREG2 TEST VBAT2 CE Rx_DATA GND1 CH1_SEL CH2_SEL CLKOUT 9 CH3_SEL 10 CLKOUT_ENB 11 CPOUT 12 TOP VIEW (Not to Scale) Figure 2. Pin Configuration 24 VCOIN 23 GND2 22 CVCO 21 RSET 20 LNA_RSET 19 LNA_1 18 LNA_2 17 CREG1 16 VBAT1 15 OSC1 14 OSC2 13 GND1B Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 CREG2 A 0.1 μf capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. 2 TEST Test Output Pin. Leave as no connect. 3 VBAT2 5 V Power Supply for RF Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 4 CE Chip Enable Input. Driving CE low puts the part into power-down mode, drawing <1 μa. 5 Rx_DATA Receiver Output. Demodulated data appears on this pin. 6 GND1 Ground for Digital Circuitry. 7 CH1_SEL Channel Select Pin. This represents the LSB of the channel select pins. 8 CH2_SEL Channel Select Pin. 9 CLKOUT Square Wave Clock Output at the Crystal Frequency. This can be used to drive the OSC2 pin of a partnering. The output has a 50:50 mark-space ratio and switches between 0 V and 2.2 V. If CLKOUT is disabled by setting Pin 11 high, then CLKOUT must be tied low. 10 CH3_SEL Channel Select Pin. 11 CLKOUT_ENB CLKOUT Enable Input. This should be driven low to enable the reference clock signal to appear on the CLKOUT pin. Driving the pin high removes the clock signal on CLKOUT. It should be driven high when an external reference is used. 12 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 13 GND1B Ground for Digital Circuitry. 14 OSC2 The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor should be tied between this pin and ground. A square wave signal can be applied to this pin as an external reference source. 15 OSC1 The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor should be tied between this pin and ground. This pin should be connected to ground when OSC2 is driven by an external reference. 16 VBAT1 5 V Power Supply for Digital Circuitry. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. 17 CREG1 A 0.1 μf capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but may cause higher spurs. 18 LNA_2 LNA Input. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. 19 LNA_1 Complementary LNA Input. 20 LNA_RSET External Bias Resistor for LNA. A value of 1.1 kω is recommended. 21 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. A value of 3.6 kω is recommended. 22 CVCO Voltage Controlled Oscillator (VCO) Capacitor. A 22 nf capacitor should be placed between this pin and CREG2 to reduce VCO noise. 23 GND2 Ground for RF Circuitry. 24 VCOIN The tuning voltage on this pin determines the output frequency of the VCO. The higher the tuning voltage, the higher the output frequency. The output of the loop filter is connected here Rev. 0 Page 5 of 12
7 TYPICAL PERFORMANCE CHARACTERISTICS REJECTION (db) CARRIER ONLY INTERFERER SIGNAL FSK INTERFERER SIGNAL LOG (BER) CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH FREQUENCY (MHz) Figure 3. Narrow-Band Interference Rejection Plot RF INPUT LEVEL (dbm) Figure 5. Sensitivity Plot CARRIER ONLY INTERFERER SIGNAL REJECTION (db) FSK INTERFERER SIGNAL FREQUENCY (MHz) Figure 4. Wideband Interference Rejection Plot Rev. 0 Page 6 of 12
8 APPLICATIONS INFORMATION Table 4. Channel Frequency Truth Table CH1_SEL CH2_SEL CH3_SEL Channel Frequency (MHz) APPLICATIONS CIRCUITS 22nF MICROCONTROLLER 62pF CREG2 VCOIN TEST GND2 VBAT2 CVCO CE RSET Rx_DATA LNA_RSET GND1 LNA_1 3.6kΩ 1.1kΩ MATCHING 10pF ANTENNA CH1_SEL CH2_SEL CLKOUT CH3_SEL CLKOUT_ENB CPOUT LNA_2 CREG1 VBAT1 OSC1 OSC2 GND MHz 62pF 33pF 33pF CRYSTAL 68nH 3.9pF 680pF 3.3kΩ 820Ω 15nF LOOP FILTER 150pF Figure 6. Single Receiver Applications Circuit Rev. 0 Page 7 of 12
9 22nF MICROCONTROLLER 62pF CREG2 TEST VBAT2 CE Rx_DATA GND1 (Rx1) VCOIN GND2 CVCO RSET LNA_RSET LNA_1 3.6kΩ 1.1kΩ MATCHING 6.8pF CH1_SEL LNA_2 62nH CH2_SEL CLKOUT CH3_SEL CLKOUT_ENB CPOUT CREG1 VBAT1 OSC1 OSC2 GND2 Y1 62pF 33pF 33pF CRYSTAL 3.9pF ANTENNA 680pF 3.3kΩ 820Ω 15nF LOOP FILTER 150pF 22nF 62pF CREG2 TEST VBAT2 CE Rx_DATA GND1 (Rx2) VCOIN GND2 CVCO RSET LNA_RSET LNA_1 3.6kΩ 1.1kΩ MATCHING 10pF CH1_SEL LNA_2 68nH CH2_SEL CLKOUT CREG1 VBAT1 3.9pF CH3_SEL CLKOUT_ENB OSC1 OSC2 62pF CPOUT GND2 680pF 3.3kΩ 820Ω 15nF LOOP FILTER 150pF Figure 7. Dual Receiver Applications Circuit Rev. 0 Page 8 of 12
10 TEST MODES If CLKOUT_ENB is tied high, CLKOUT is disabled. The CLKOUT pin is reconfigured as a test enable input. If the CLKOUT pin is then tied low, the part operates as is normal with CLKOUT off. If it is tied high (2.2 V), the part is in test mode. Test mode is described in Table 5. When CLKOUT_ENB = 0, RSSI appears on the test output pin (Pin 2), and CLKOUT is configured as an output with a 9.8 MHz clock coming out. When test mode is enabled, the channel frequency is set to MHz (Channel 1). Table 5. Test Modes CH1_SEL CH2_SEL CH3_SEL Test Mode agc gain is set to maximum (filti is also set to maximum on test output pin) filti on test output pin filtq on test output pin Charge pump output is set to maximum (test pin is also tri-state) Charge pump output is set to minimum (also n-divider output 2 on test output pin) Charge pump is tri-state (test pin is also tri-state) n-divider output 2 on test output pin Recovered data clock on test output pin Rev. 0 Page 9 of 12
11 OUTLINE DIMENSIONS BSC PIN BSC COPLANARITY 1.20 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option BRUZ 1 40 C to +85 C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 BRUZ-RL 1 40 C to +85 C 24-Lead Thin Shrink Small Outline Package [TSSOP], 13 REEL RU-24 BRUZ-RL C to +85 C 24-Lead Thin Shrink Small Outline Package [TSSOP], 7 REEL RU-24 1 Z = Pb-free part. Rev. 0 Page 10 of 12
12 NOTES Rev. 0 Page 11 of 12
13 NOTES 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /07(0) Rev. 0 Page 12 of 12
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FEATURES.8 V to 5.5 V operation Ultralow on resistance.4 Ω typical.6 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion.7 Ω typical.4 Ω maximum RON flatness High current carrying
20 MHz to 500 MHz IF Gain Block ADL5531
Data Sheet FEATURES Fixed gain of 20 db Operation up to 500 MHz Input/output internally matched to 50 Ω Integrated bias control circuit Output IP3 41 dbm at 70 MHz 39 dbm at 190 MHz Output 1 db compression:
DC to 1000 MHz IF Gain Block ADL5530
Data Sheet FEATURES Fixed gain of 16. db Operation up to MHz 37 dbm Output Third-Order Intercept (OIP3) 3 db noise figure Input/output internally matched to Ω Stable temperature and power supply 3 V or
400 MHz to 4000 MHz Low Noise Amplifier ADL5523
FEATURES Operation from MHz to MHz Noise figure of. db at 9 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications
16 V, 4 MHz RR0 Amplifiers AD8665/AD8666/AD8668
6 V, MHz RR Amplifiers AD8665/AD8666/AD8668 FEATURES Offset voltage:.5 mv max Low input bias current: pa max Single-supply operation: 5 V to 6 V Dual-supply operation: ±.5 V to ±8 V Low noise: 8 nv/ Hz
30 MHz to 6 GHz RF/IF Gain Block ADL5611
Preliminary Technical Data FEATURES Fixed gain of 22.1 db Broad operation from 30 MHz to 6 GHz High dynamic range gain block Input/output internally matched to 50 Ω Integrated bias control circuit OIP3
3 V LVDS Quad CMOS Differential Line Driver ADN4667
FEATURES ±15 kv ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum
Low Cost JFET Input Operational Amplifiers ADTL082/ADTL084
Low Cost JFET Input Operational Amplifiers ADTL/ADTL FEATURES TL/TL compatible Low input bias current: pa maximum Offset voltage 5.5 mv maximum (ADTLA/ADTLA) 9 mv maximum (ADTLJ/ADTLJ) ±5 V operation Low
CMOS, 170 MHz, Triple, 10-Bit High Speed Video DAC ADV7123-EP
CMOS, 70 MHz, Triple, 0-Bit High Speed Video DAC ADV723-EP FEATURES 70 MSPS throughput rate Triple, 0-bit digital-to-analog converters (DACs) SFDR 70 db at fclk = 50 MHz; fout = MHz 53 db at fclk = 40
Fault Protection and Detection, 10 Ω RON, Quad SPST Switches ADG5412F-EP
Enhanced Product FEATURES Overvoltage protection up to 55 V and +55 V Power-off protection up to 55 V and +55 V Overvoltage detection on source pins Low on resistance: Ω On-resistance flatness:.5 Ω 5.5
>10 W, GaN Power Amplifier, 0.01 GHz to 1.1 GHz HMC1099
9 1 11 12 13 14 1 16 32 GND 31 29 28 27 26 FEATURES High saturated output power (PSAT):. dbm typical High small signal gain: 18. db typical High power added efficiency (PAE): 69% typical Instantaneous
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 FEATURES ±15 kv ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential
Dual SPDT Switch ADG436
ual SPT Switch AG436 FEATURES 44 V supply maximum ratings VSS to V analog signal range Low on resistance (12 Ω typ) Low RON (3 Ω max) Low RON match (2.5 Ω max) Low power dissipation Fast switching times
100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240
1 MHz to 4 MHz RF/IF Digitally Controlled VGA ADL524 FEATURES Operating frequency from 1 MHz to 4 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit,.5 db digital step attenuator 31.5
9- and 11-Channel, Muxed Input LCD Reference Buffers AD8509/AD8511
9- and -Channel, Muxed Input LCD Reference Buffers AD8509/AD85 FEATURES Single-supply operation: 3.3 V to 6.5 V High output current: 300 ma Low supply current: 6 ma Stable with 000 pf loads Pin compatible
Low Power, Precision, Auto-Zero Op Amps AD8538/AD8539 FEATURES Low offset voltage: 13 μv maximum Input offset drift: 0.03 μv/ C Single-supply operatio
Low Power, Precision, Auto-Zero Op Amps FEATURES Low offset voltage: 3 μv maximum Input offset drift:.3 μv/ C Single-supply operation: 2.7 V to 5.5 V High gain, CMRR, and PSRR Low input bias current: 25
AD864/AD8642/AD8643 TABLE OF CONTENTS Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 5 ESD Caution... 5 Typical Perfo
FEATURES Low supply current: 25 µa max Very low input bias current: pa max Low offset voltage: 75 µv max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±3 V Rail-to-rail output Unity-gain
Dual Processor Supervisors with Watchdog ADM13305
Dual Processor Supervisors with Watchdog ADM335 FEATURES Dual supervisory circuits Supply voltage range of 2.7 V to 5.5 V Pretrimmed threshold options:.8 V, 2.5 V, 3.3 V, and 5 V Adjustable.6 V voltage
Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time ADG774A
Data Sheet FEATURES Bandwidth: >4 MHz Low insertion loss and on resistance: 2.2 Ω typical On resistance flatness:.3 Ω typical Single 3 V/5 V supply operation Very low distortion:
20 MHz to 6 GHz RF/IF Gain Block ADL5542
FEATURES Fixed gain of db Operation up to 6 GHz Input/output internally matched to Ω Integrated bias control circuit Output IP3 46 dbm at MHz 4 dbm at 9 MHz Output 1 db compression:.6 db at 9 MHz Noise
Low Power, Rail-to-Rail Output, Precision JFET Amplifiers AD8641/AD8642/AD8643
Data Sheet Low Power, Rail-to-Rail Output, Precision JFET Amplifiers AD864/AD8642/AD8643 FEATURES Low supply current: 25 μa max Very low input bias current: pa max Low offset voltage: 75 μv max Single-supply
Zero Drift, Digitally Programmable Instrumentation Amplifier AD8231-EP OP FUNCTIONAL BLOCK DIAGRAM FEATURES ENHANCED PRODUCT FEATURES
Zero Drift, Digitally Programmable Instrumentation Amplifier AD8231-EP FEATURES Digitally/pin-programmable gain G = 1, 2, 4, 8, 16, 32, 64, or 128 Specified from 55 C to +125 C 5 nv/ C maximum input offset
Comparators and Reference Circuits ADCMP350/ADCMP354/ADCMP356
Data Sheet Comparators and Reference Circuits ADCMP35/ADCMP354/ADCMP356 FEATURES Comparators with.6 V on-chip references Output stages Open-drain active low (ADCMP35) Open-drain active high (ADCMP354)
Low Power, Adjustable UV and OV Monitor with 400 mv, ±0.275% Reference ADCMP671
Data Sheet Low Power, Adjustable UV and Monitor with mv, ±.7% Reference ADCMP67 FEATURES Window monitoring with minimum processor I/O Individually monitoring N rails with only N + processor I/O mv, ±.7%
Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670
Data Sheet Programmable Low Voltage 1:10 LVDS Clock Driver FEATURES FUNCTIONAL BLOCK DIAGRAM Low output skew
Nonreflective, Silicon SP4T Switch, 0.1 GHz to 6.0 GHz HMC7992
Nonreflective, Silicon SP4T Switch,.1 GHz to 6. GHz FEATURES Nonreflective, 5 Ω design High isolation: 45 db typical at 2 GHz Low insertion loss:.6 db at 2 GHz High power handling 33 dbm through path 27
High Speed, G = +2, Low Cost, Triple Op Amp ADA4862-3
High Speed,, Low Cost, Triple Op Amp ADA4862-3 FEATURES Ideal for RGB/HD/SD video Supports 8i/72p resolution High speed 3 db bandwidth: 3 MHz Slew rate: 75 V/μs Settling time: 9 ns (.5%). db flatness:
Ultraprecision, 36 V, 2.8 nv/ Hz Dual Rail-to-Rail Output Op Amp AD8676
FEATURES Very low voltage noise 2.8 nv/ Hz @ khz Rail-to-rail output swing Low input bias current: 2 na maximum Very low offset voltage: 2 μv typical Low input offset drift:.6 μv/ C maximum Very high gain:
Improved Second Source to the EL2020 ADEL2020
Improved Second Source to the EL ADEL FEATURES Ideal for Video Applications.% Differential Gain. Differential Phase. db Bandwidth to 5 MHz (G = +) High Speed 9 MHz Bandwidth ( db) 5 V/ s Slew Rate ns Settling
400 MHz 4000 MHz Low Noise Amplifier ADL5521
FEATURES Operation from 400 MHz to 4000 MHz Noise figure of 0.8 db at 900 MHz Including external input match Gain of 20.0 db at 900 MHz OIP3 of 37.7 dbm at 900 MHz P1dB of 22.0 dbm at 900 MHz Integrated
Low Capacitance, Low Charge Injection, ±15 V/12 V icmos, Dual SPDT Switch ADG1236
ata Sheet Low Capacitance, Low Charge Injection, ±5 V/2 V icmos, ual SPT Switch FEATURES.3 pf off capacitance 3.5 pf on capacitance pc charge injection 33 V supply range 2 Ω on resistance Fully specified
Low Capacitance, Low Charge Injection, ±15 V/+12 V icmos Dual SPST Switches ADG1221/ADG1222/ADG1223
Data Sheet Low Capacitance, Low Charge Injection, ±15 V/+12 V icmos Dual SPST Switches ADG1221/ADG1222/ADG1223 FEATURES
Low Noise, Micropower 5.0 V Precision Voltage Reference ADR293-EP
Enhanced Product Low Noise, Micropower 5.0 V Precision Voltage Reference FEATURES 6.0 V to 15 V supply range Supply current: 15 μa maximum Low noise: 15 μv p-p typical (0.1 Hz to 10 Hz) High output current:
16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP AD7490-EP
Enhanced Product FEATURES Fast throughput rate: 1 MSPS Specified for VDD of 4.75 V to 5.25 V Low power at maximum throughput rates 12.5 mw maximum at 1 MSPS with 5 V supplies 16 (single-ended) inputs with
4 Ω RON, 4-/8-Channel ±15 V/+12 V/±5 V icmos Multiplexers ADG1408-EP/ADG1409-EP
Enhanced Product 4 Ω RON, 4-/-Channel ±5 V/+2 V/±5 V icmos Multiplexers AG4-EP/AG49-EP FEATURES 4.7 Ω maximum on resistance @ 25 C.5 Ω on resistance flatness Up to 9 ma continuous current Fully specified
Very Low Distortion, Precision Difference Amplifier AD8274
Very Low Distortion, Precision Difference Amplifier AD8274 FEATURES Very low distortion.2% THD + N (2 khz).% THD + N ( khz) Drives Ω loads Excellent gain accuracy.3% maximum gain error 2 ppm/ C maximum
Ultralow Offset Voltage Operational Amplifier OP07
FEATURES Low VOS: 5 μv maximum Low VOS drift:. μv/ C maximum Ultrastable vs. time:.5 μv per month maximum Low noise:. μv p-p maximum Wide input voltage range: ± V typical Wide supply voltage range: ± V
HMC4069LP4E FREQUENCY DIVIDERS AND DETECTORS - SMT. Typical Applications. General Description. Functional Diagram
Typical Applications The HMC4069LPE is ideal for: Point-to-Point Radios Satellite Communication Systems Military Applications Sonet Clock Generation General Description Functional Diagram Features Ultra
Triple Processor Supervisors ADM13307
Triple Processor Supervisors ADM337 FEATURES Triple supervisory circuits Supply voltage range of 2. V to 5.5 V Pretrimmed threshold options:.8 V, 2.5 V, 3.3 V, and 5 V Adjustable.6 V and.25 V voltage references
LC 2 MOS Precision Mini-DIP Analog Switch ADG419
LC 2 MOS Precision Mini-IP Analog Switch AG419 FEATURES 44 V supply maximum ratings VSS to V analog signal range Low on resistance:
Dual Precision, Low Cost, High Speed BiFET Op Amp AD712-EP
Dual Precision, Low Cost, High Speed BiFET Op Amp FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range ( 55 C to +125 C) Controlled manufacturing baseline One
FET Drive Simple Sequencers ADM6819/ADM6820
FET Drive Simple Sequencers ADM6819/ADM682 FEATURES Single chip enables power supply sequencing of two supplies On-board charge pump fully enhances N-channel FET Adjustable primary supply monitor to.618
6 db Differential Line Receiver
a FEATURES High Common-Mode Rejection DC: 9 db typ Hz: 9 db typ khz: 8 db typ Ultralow THD:.% typ @ khz Fast Slew Rate: V/ s typ Wide Bandwidth: 7 MHz typ (G = /) Two Gain Levels Available: G = / or Low
Low Cost, Precision JFET Input Operational Amplifiers ADA4000-1/ADA4000-2/ADA4000-4
Low Cost, Precision JFET Input Operational Amplifiers ADA-/ADA-/ADA- FEATURES High slew rate: V/μs Fast settling time Low offset voltage:.7 mv maximum Bias current: pa maximum ± V to ±8 V operation Low