Multiband multistandard direct-conversion TV tuner

Transcription

1 SPECIFICATION 1 FEATURES TSMC 0.18 um SiGe BiCMOS technology Direct conversion receiver A few number of external components 0.18 um SiGe BiCMOS technology Integrated 75 Ω input matched LNAs Integrated tunable bandwidth channel filters (1 12 MHz) with adjustment to maintain the cut-off frequency over all process variations I/Q differential outputs Dual automatic gain control AGC (RF & Baseband AGC) Integrated fractional-n frequency synthesizer Integrated VCO with quadrature outputs Integrated reference oscillator with output buffer Integrated voltage regulator Fully controlled via I 2 C serial interface Less than 15 mw power consumption in DVB-H mode with 10:1 time slicing Power down mode V power supply 2 APPLICATION Navigation systems Portable receivers Mobile communication Measuring equipment 3 OVERVIEW The NT1022 is multiband multistandard direct-conversion TV tuner designed for Mobile Digital TV applications. The TV tuner supports DVB-H, DVB-T, IP-DAB, T-DMB, FM standards and covers FM (75 MHz to 108 MHz), VHF (170 MHz to 240 MHz), UHF (470 MHz to 860 MHz) bands and L-band (both 1450 MHz to 1490 MHz and 1660 MHz to 1685 MHz). So it is suitable for digital TV reception on portable devices almost anywhere in the world. Based on direct-conversion architecture with zero-if NT1022 is optimal solution for television signal receiving. The TV tuner is a highly integrated circuit therefore a few external components are required. A programmable serial interface allows status monitoring and controlling all the internal operations and test modes. The IC is fabricated on TSMC 0.18 um SiGe BiCMOS technology. Ver. 1.1 August

2 4 PAD DESCRIPTION Pad number Name Description 1A 1B VCC_RF RF circuits supply voltage 2 LNA1_IN VHF LNA input 3 LNA2_IN UHF LNA input 4 LNA3_IN L band LNA input 5A 5B GND_RF RF circuits ground 6 AGC_RF RF AGC capacitor 7 Rref Reference resistor 8 SDN Negative shutdown input for receive/pause in packet mode 9 LDO_OUT LDO voltage regulator output 10A 10B VCC_DIG PLL voltage supply 11 SDA Serial interface data 12 SCL Serial interface clock 13A 13B GND_DIG PLL ground 14 I_AGC I channel BB AGC capacitor 15 Q_AGC Q channel BB AGC capacitor 16A 16B VCC_BB IFA & LPF supply voltage 17 Q_OCC Q channel DC offset compensation circuit (DCOC) capacitor 18 QOUT_P 19 QOUT_N Q channel differential outputs 20 I_OCC I channel DCOC capacitor 21 IOUT_N 22 IOUT_P I channel differential outputs 23A 23B GND_BB IFA & LPF ground 24 XT1 Xtal oscillator input 1 25 XT2 Xtal oscillator input 2 26 XT_OUT Clock frequency output 27A 27B VCC_CP PFD & Charge pump supply voltage 28A 28B GND_CP PFD & Charge pump ground 29 CP_OUT Charge pump output 30A 30B GND_VCO VCO ground 31 ADR Slave address 32A 32B VCC_VCO VCO supply voltage Ver. 1.1 page 2 of 11

3 5 TYPICAL APPLICATION CIRCUIT Figure 1: NT1022 application circuit. Ver. 1.1 page 3 of 11

4 Table 1: External component description Component Nominal value Tolerance Notes C1 0.1 uf ±10 % Supply voltage filter capacitor C2 220 pf ±5 % Supply voltage filter capacitor C3 1 nf ±5 % Blocking capacitor C4 220 pf ±5 % Blocking capacitor C5 220 pf ±5 % Blocking capacitor C6 470 pf ±5 % RF AGC filter capacitor C7 470 pf ±5 % RF AGC filter capacitor C8 2.2 uf ±10 % Voltage regulator output filter capacitor C9 0.1 uf ±10 % Supply voltage filter capacitor C * uf ±10 % BB AGC filter capacitor C * uf ±10 % BB AGC filter capacitor C12 10 uf ±20 % Supply voltage filter capacitor C uf ±10 % Supply voltage filter capacitor C uf ±10 % DCOC capacitor (X5R ceramic) C uf ±10 % DCOC capacitor (X5R ceramic) C16 22 pf ±5 % Ceramic capacitor C17 22 pf ±5 % Ceramic capacitor C pf ±5 % Supply voltage filter capacitor C pf ±5 % Supply voltage filter capacitor C uf ±5 % PLL filter capacitor C21 10 pf ±5 % PLL filter capacitor C uf ±10 % Supply voltage filter capacitor R1 10 Ω ±5 % Supply voltage filter resistor R2 10* Ω ±5 % RF AGC filter resistor R kω ±1 % High precision resistor R4 10 Ω ±5 % Supply voltage filter resistor R5 10* Ω ±5 % BB AGC filter resistor R6 10* Ω ±5 % BB AGC filter resistor R7 10 Ω ±5 % Supply voltage filter resistor R8 10 Ω ±5 % Supply voltage filter resistor R9 12 kω ±5 % PLL filter resistor R10 10 Ω ±5 % Supply voltage filter resistor Y MHz - Crystal Note: * is defined depending on PCB construction and purpose. Ver. 1.1 page 4 of 11

5 6 LAYOUT DESCRIPTION TV tuner dimensions are given in the table 2. Table 2: Block dimensions. Dimension Value Unit Height µm Width µm Figure 2: Block layout view Ver. 1.1 page 5 of 11

6 7 OPERATING CHARACTERISTICS 7.1 TECHNICAL CHARACTERISTICS Technology TSMC SiGe BiCMOS 0.18 μm Status silicon proven Area 8.4 mm DC ELECTRICAL CHARACTERISTICS The values of electrical characteristics are specified for V CC = 2.8 V to 3.6V, T = C. Typical values are at V CC = 3.0V, T =+25 C, unless otherwise specified. Value Parameter Symbol Condition Unit Min Typ Max Supply voltage V cc V I cc Active mode ma Supply current I stb Stand-by mode µa I PM Packet mode, 10: ma Maximum gain - V RF AGC control voltage V cc 1 - AGC_RF Minimum gain V Baseband AGC control Maximum gain - V V cc voltage AGC_BB Minimum gain V Input logic-level low V IL V Input logic-level high V IH - 0.7V cc - V cc V 7.3 AC ELECTRICAL CHARACTERISTICS The values of electrical characteristics are specified for V CC = 2.8 V to 3.6 V, T = C. Typical values are at V CC = 3.0 V, T =+25 C, unless otherwise specified. Parameter Symbol Condition Value Min Typ Max Unit Overall FM VHF Operating frequency range F IN UHF MHz L L Noise figure (DSB) NF db Input VSWR VSWR IN 75 Ω Maximum input signal level P in MAX dbm Overall voltage gain G db IQ phase accuracy Δφ I/Q phase error at 1 MHz degrees IQ amplitude accuracy ΔA mv p-p RF AGC range ΔG RF db BB AGC range ΔG BB db IFA&LPF Output frequency range F BB MHz Nominal output voltage Vout Vp-p Output impedance Rout Differential kω LPF bandwidth BWLPF MHz Ver. 1.1 page 6 of 11

7 Table AC electrical characteristics (continue). Synthesizer Parameter Symbol Condition Value Min Typ Max Phase noise PN Charge-pump output current I CP offset, single-sideband, dbc/hz At 100 khz frequency LO closed loop Reference frequency F ref MHz N divider ratio N R divider ratio R Fractional-N resolution Res Bit Frequency comparison F FC MHz Preset Preset µa Preset Preset VCO VCO frequency range F VCO VCO VCO MHz VCO Output clock frequency F clk MHz Preset Preset Clock frequency output peakto-peak voltage clk Preset A Preset V p-p CMOS Unit Ver. 1.1 page 7 of 11

8 8 TYPICAL OPERATING CHARACTERISTICS Figure 3: Noise figure vs. FM band Figure 4: Noise figure vs. VHF band Figure 5: Noise figure vs. UHF band Figure 6: Noise figure vs. L1 band Figure 7: Noise figure vs. L2 band Ver. 1.1 page 8 of 11

9 Figure 8: Phase noise vs. offset frequency (FM) Figure 9: Phase noise vs. offset frequency (VHF III) Figure 10: Phase noise vs. offset frequency (UHF) Ver. 1.1 page 9 of 11

10 Figure 11: Phase noise vs. offset frequency (L1-L2) Figure 12: BB AGC range Figure 13: RF AGC range Ver. 1.1 page 10 of 11

11 9 DELIVERABLES IP contents: Datasheet Layout View (GDSII) Evaluation kit based on packaged IC Characterization Report Behavioral Model SPICE netlist (.cdl) Integration Support REVISION HISTORY 1. From version 1.0: The section Absolute maximum rating was added (refer to p.6) The section Typical operating characteristics was added (refer to p.7) Ver. 1.1 page 11 of 11