700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO ADRF6614

Transcription

1 7 MHz to 3 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO ADRF664 FEATURES RF frequency: 7 MHz to 3 MHz, continuous LO input frequency: 2 MHz to 27 MHz, high-side or lowside injection IF range: 4 MHz to 5 MHz Power conversion gain of 9. db Phase noise performance of 44 dbc/hz at 8 khz offset supporting stringent GSM standards in both 8 MHz to 9 MHz and 8 MHz to 9 MHz bands Single-sideband (SSB) noise figure of.3 db Input IP3 of 3 dbm Input PdB of.6 dbm Typical LO input drive of dbm Single-ended, 5 Ω RF port Single-ended or balanced LO input port Serial port interface (SPI) control on all functions Exposed pad, 7 mm 7 mm, 48-lead LFCSP APPLICATIONS Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells GENERAL DESCRIPTION The ADRF664 is a dual radio frequency (RF) mixer and intermediate frequency (IF) amplifier with an integrated phaselocked loop (PLL) and voltage controlled oscillators (VCOs). The ADRF664 uses revolutionary broadband square wave limiting local oscillator (LO) amplifiers to achieve a wideband RF bandwidth of 7 MHz to 3 MHz. Unlike narrow-band sine wave LO amplifier solutions, the LO can be applied above or below the RF input over a wide bandwidth. Energy storage elements are not utilized in the LO amplifier, thus dc current consumption also decreases with decreasing LO frequency. The ADRF664 utilizes highly linear, doubly balanced passive mixer cores with integrated RF and LO balancing circuits to allow single-ended operation. Integrated RF baluns allow optimal performance over the 7 MHz to 3 MHz RF input frequency. The balanced passive mixer arrangement provides outstanding LO to RF and LO to IF leakages, excellent RF to IF isolation, and excellent intermodulation performance over the full RF bandwidth. The balanced mixer cores provide extremely high input linearity, allowing the device to be used in demanding wideband applications where in-band blocking signals may otherwise result in the degradation of dynamic range. Noise performance under blocking is comparable to narrow-band passive mixer designs. High linearity Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 3 6 VCC 7 FUNCTIONAL BLOCK DIAGRAM VCOVTUNE VCC2 VCO VCO VCO EXTVCOIN+ 4 EXTVCOIN 5 DECL 8 DECL2 9 VCO LDO DECL3 SPI DECL4 2.5V LDO DECL PLL 3.3V LDO DIV 3.3V LDO LDO4 LDO3 LOOUT+ LOOUT CPOUT REFIN MUXOUT LDO VCC2 SDIO SCLK CS IFOUT+ IFOUT IFOUT2+ IFOUT2 VCC DNC VCC PLL REF BUFFER PFD/CP FRACTIONAL DIVIDER 33 VCC9 32 VCC8 36 RFBCT 35 RFIN TO 32 3 VCC7 3 LDO2 ADRF RFIN2 25 RFBCT2 MUX SPI CONTROL 29 VCC6 28 VCC5 27 VCC Figure. VCC3 DNC IF buffer amplifiers follow the passive mixer cores, yielding typical power conversion gains of 9. db, and can be matched to a wide range of output impedances. The PLL architecture supports both integer-n and fractional-n operation and can generate the entire LO frequency range of 2 MHz to 27 MHz using an external reference input frequency anywhere in the range of 2 MHz to 32 MHz. An external loop filter provides flexibility in trading off phase noise vs. acquisition time. To reduce fractional spurs in fractional-n mode, a Σ-Δ modulator controls the post VCO-programmable divider. The device integrates six VCO cores, four of which provide complete frequency coverage between 2 MHz and 27 MHz, and meet the GSM phase noise requirements in the 8 MHz and 9 MHz bands. Two additional GSM only cores enable the ADRF664 to meet the GSM phase noise requirements in the digital cellular system 8 MHz (DCS8) and personal communications service 9 MHz (PCS9) bands. All features of the ADRF664 are controlled via a 3-wire SPI, resulting in optimum performance and minimum external components. The ADRF664 is fabricated using a BiCMOS, high performance IC process. The device is available in a 7 mm 7 mm, 48-lead LFCSP package and operates over a 4 C to +85 C temperature range. An evaluation board is available. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support 45-

2 ADRF664 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 RF Specifications... 3 Synthesizer/PLL Specifications... 4 VCO Specifications, Open-Loop... 7 Logic Input and Power Specifications... 8 Digital Logic Specifications... 9 Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 3 Mixer, High Performance Mode... 3 Mixer, High Efficiency Mode Synthesizer Data Sheet Spurious Performance Theory of Operation RF Subsystem External LO Generation Internal LO Generation Applications Information Basic Connections by Pin Description Mixer Optimization... 4 RF Input Balun Insertion Loss Optimization... 4 IIP3 Optimization... 4 VGS Programming... 4 Low-Pass Filter Programming... 4 GSM Mode of Operation Register Summary Register Details Evaluation Board Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 3/6 Revision : Initial Version Rev. Page 2 of 6

3 ADRF664 SPECIFICATIONS RF SPECIFICATIONS TA = 25 C, frf = 9 MHz, flo = 697 MHz, ZO = 5 Ω, frequency of the reference (fref) = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RF balun (RFB) and low-pass filter (LPF) settings, unless otherwise noted. Table. High Performance Mode Parameter Test Conditions/Comments Min Typ Max Unit RF INTERFACE Return Loss Tunable to >2 db broadband via serial port 7.9 db Input Impedance 5 Ω RF Frequency Range (frf) 7 3 MHz IF OUTPUT INTERFACE Output Impedance Differential impedance, f = 2 MHz 3.5 Ω pf IF Frequency Range (fif) 4 5 MHz DC Bias Voltage Externally generated IFOUTx± V EXTERNAL LO INPUT External LO Power Input 5 +5 dbm Return Loss db Input Impedance 5 Ω External VCO Input Frequency External VCO input supports divide by, 2, 4, 8, 6, and MHz LO Frequency Range Low-side or high-side LO, internally or externally MHz generated DYNAMIC PERFORMANCE Power Conversion Gain 4: IF port transformer and printed circuit board (PCB) loss 9. db removed Voltage Conversion Gain ZSOURCE = 5 Ω, differential ZLOAD = 2 Ω 5. db SSB Noise Figure.3 db IF Output Phase Noise Under Blocking dbm blocker present MHz above desired the RF input, 53 dbc/hz frf = 9 MHz, fblock = 9 MHz, flo = 697 MHz, fif = 23 MHz, IFBLOCKER = 23 MHz Input Third-Order Intercept (IIP3) frf = 9 MHz, frf2 = 9 MHz, flo = 697 MHz, each RF 3 dbm tone at dbm Input Second-Order Intercept (IIP2) frf = 9 MHz, frf2 = 95 MHz, flo = 697 MHz, each RF 6 dbm tone at dbm Input db Compression Point (PdB).6 dbm LO to IF Output Leakage Unfiltered IF output 35 dbm LO to RF Input Leakage 45 dbm RF to IF Output Isolation 22 db IF/2 Spurious dbm input power 72 dbc IF/3 Spurious dbm input power 69 dbc POWER INTERFACE VCC, VCC2, VCC7, VCC2 Supply Voltage V Quiescent Current 26 ma VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC, VCC, IFOUT+, IFOUT, IFOUT2+, IFOUT2 Supply Voltage V Quiescent Current 24 ma LO OUTPUT (LOOUT+, LOOUT ) Frequency Range (flo) 2 27 MHz Output Level Adjustable via SPI in four steps, in 5 Ω balanced load 5 +7 dbm Output Impedance Balanced 5 Ω Supply voltage must be applied from the external circuit through choke inductors. Rev. Page 3 of 6

4 ADRF664 Data Sheet TA = 25 C, frf = 9 MHz, flo = 697 MHz, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 2. High Efficiency Mode Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Power Conversion Gain 4: IF port transformer and PCB loss removed 8.7 db Voltage Conversion Gain ZSOURCE = 5 Ω, differential ZLOAD = 2 Ω 4.7 db SSB Noise Figure.7 db IIP3 frf = 9 MHz, frf2 = 9 MHz, flo = 697 MHz, 2.5 dbm each RF tone at dbm IIP2 frf = 9 MHz, frf2 = 95 MHz, flo = 697 MHz, 53 dbm each RF tone at dbm Input PdB 8.2 dbm LO to IF Output Leakage Unfiltered IF output 45. dbm LO to RF Input Leakage 52. dbm RF to IF Output Isolation 22.8 db IF/2 Spurious dbm input power 58 dbc IF/3 Spurious dbm input power 58 dbc POWER INTERFACE VCC, VCC2, VCC7, VCC2 Supply Voltage V Quiescent Current 26 ma VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC, VCC, IFOUT+, IFOUT, IFOUT2+, IFOUT2 Supply Voltage V Quiescent Current 2 ma SYNTHESIZER/PLL SPECIFICATIONS High performance mode, TA = 25 C, measured on LO output, flo = 7 MHz, ZO = 5 Ω, fref = MHz, fpfd =.536 MHz, fref power (PREFIN) = 4 dbm, CSCALE = 8 ma, bleed = µa, ABLDLY =.9 ns, integer mode loop filter, unless otherwise noted. Table 3. Integer Mode Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to LO Frequency Range (flo) Internally generated LO 2 27 MHz Figure of Merit (FOM) PREFIN = 6.5 dbm 223 dbc/hz/hz Phase and Frequency Detector (PFD).8 7 MHz Frequency (fpfd) Reference Spurs fpfd =.536 MHz fpfd 5 dbc 4 fpfd 5 dbc >4 fpfd 9 dbc CHARGE PUMP Pump Current Programmable to 25 µa, 5 µa,, 8 ma ma Output Compliance Range V REFERENCE CHARACTERISTICS REFIN, MUXOUT pins REFIN Input Frequency 2 32 MHz REFIN Input Capacitance 4 pf Reference Divider Value Programmable to.5,, 2, 3,, MUXOUT Output Level VOL (lock detect output selected).25 V VOH (lock detect output selected) 2.7 V MUXOUT Duty Cycle Reference output selected 5 % Rev. Page 4 of 6

5 ADRF664 Parameter Test Conditions/Comments Min Typ Max Unit VCO_ Phase Noise, Locked flo = 2.55 GHz khz offset 87 dbc/hz 5 khz offset 94.9 dbc/hz khz offset 3.3 dbc/hz MHz offset 32.9 dbc/hz MHz offset 54. dbc/hz 4 MHz offset 55.2 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.87 rms VCO_ Phase Noise, Locked flo = 2.22 GHz khz offset 9 dbc/hz 5 khz offset 98.4 dbc/hz khz offset 6.5 dbc/hz MHz offset 36. dbc/hz MHz offset 54.8 dbc/hz 4 MHz offset 55.5 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.63 rms VCO_2 Phase Noise, Locked flo =.9 GHz khz offset 9 dbc/hz 5 khz offset 98. dbc/hz khz offset 9.8 dbc/hz MHz offset 37. dbc/hz MHz offset 55.7 dbc/hz 4 MHz offset 56.2 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.6 rms VCO_3 Phase Noise, Locked flo =.6 GHz khz offset 89 dbc/hz 5 khz offset 97.2 dbc/hz khz offset 7 dbc/hz MHz offset 36.2 dbc/hz MHz offset 55.7 dbc/hz 4 MHz offset 57.3 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.64 rms VCO_4 Phase Noise, Locked flo =.57 GHz khz offset 9 dbc/hz 5 khz offset 9 dbc/hz khz offset 9 dbc/hz 8 khz offset 44 dbc/hz MHz offset 45 dbc/hz MHz offset 56 dbc/hz 4 MHz offset 56 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.26 rms VCO_5 Phase Noise, Locked flo =.68 GHz khz offset 93 dbc/hz 5 khz offset 7 dbc/hz khz offset 8 dbc/hz 8 khz offset 44 dbc/hz MHz offset 45 dbc/hz Rev. Page 5 of 6

6 ADRF664 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit MHz offset 57 dbc/hz 4 MHz offset 57.5 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.27 rms The FOM is computed as phase noise (dbc/hz) log(fpfd) 2log(fLO/fPFD). The FOM was measured across the full LO range, with fref = MHz and fref power = 6.5 dbm with a.536 MHz fpfd. The FOM was computed at 5 khz offset. High performance mode, TA = 25 C, measured on LO output, flo = 7 MHz, ZO = 5 Ω, fref = MHz, fpfd = 3.72 MHz, fref power = 4 dbm, CSCALE = 25 µa, bleed = µa, ABLDLY = ns, fractional mode loop filter, unless otherwise noted. Table 4. Fractional Mode Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to LO FOM PREFIN = 6.5 dbm 29 dbc/hz/hz REFERENCE CHARACTERISTICS REFIN, MUXOUT pins VCO_ Phase Noise, Locked flo = 2.55 GHz khz offset 92.5 dbc/hz 5 khz offset 97.4 dbc/hz khz offset 9.7 dbc/hz MHz offset 37.6 dbc/hz MHz offset 53.6 dbc/hz 4 MHz offset 55.5 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.36 rms VCO_ Phase Noise, Locked flo = 2.22 GHz khz offset 93.6 dbc/hz 5 khz offset.8 dbc/hz khz offset 2.5 dbc/hz MHz offset 4.5 dbc/hz MHz offset 54.3 dbc/hz 4 MHz offset 55.3 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.32 rms VCO_2 Phase Noise, Locked flo =.9 GHz khz offset 94.2 dbc/hz 5 khz offset.7 dbc/hz khz offset 2.4 dbc/hz MHz offset 4.3 dbc/hz MHz offset 55.8 dbc/hz 4 MHz offset 56.8 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.32 rms VCO_3 Phase Noise, Locked flo =.6 GHz khz offset 93. dbc/hz 5 khz offset 99.8 dbc/hz khz offset.9 dbc/hz MHz offset 4.2 dbc/hz MHz offset 55.7 dbc/hz 4 MHz offset 57.2 dbc/hz Integrated Phase Noise khz to 4 MHz integration bandwidth.33 rms The FOM is computed as phase noise (dbc/hz) log(fpfd) 2log(fLO/fPFD). The FOM was measured across the full LO range, with fref = MHz and fref power = 6.5 dbm with a 3.72 MHz fpfd. The FOM was computed at 45 khz offset. Rev. Page 6 of 6

7 ADRF664 VCO SPECIFICATIONS, OPEN-LOOP High performance mode, TA = 25 C, measured on LO output, unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit VCO_ PHASE NOISE flo = 2.55 GHz khz offset 5 dbc/hz 5 khz offset 4.4 dbc/hz khz offset 2.6 dbc/hz MHz offset 37.7 dbc/hz MHz offset 54 dbc/hz 4 MHz offset 55. dbc/hz VCO_ PHASE NOISE flo = 2.5 GHz khz offset 54 dbc/hz 5 khz offset 6. dbc/hz khz offset 5 dbc/hz MHz offset 38.9 dbc/hz MHz offset 55.8 dbc/hz 4 MHz offset 55.2 dbc/hz VCO_2 PHASE NOISE flo =.9 GHz khz offset 53.6 dbc/hz 5 khz offset 6.6 dbc/hz khz offset 4.6 dbc/hz MHz offset 4.8 dbc/hz MHz offset 55.4 dbc/hz 4 MHz offset 56.3 dbc/hz VCO_3 PHASE NOISE flo =.6 GHz khz offset 48.5 dbc/hz 5 khz offset 6 dbc/hz khz offset 5.3 dbc/hz 8 khz offset 39.2 dbc/hz MHz offset 4.2 dbc/hz MHz offset 57.7 dbc/hz 4 MHz offset 56.3 dbc/hz VCO_4 PHASE NOISE fvco = 3.4 GHz khz offset 53.8 dbc/hz 5 khz offset.3 dbc/hz khz offset 8 dbc/hz 8 khz offset 39.5 dbc/hz MHz offset 4.6 dbc/hz MHz offset 55.4 dbc/hz 4 MHz offset 57.4 dbc/hz VCO_5 PHASE NOISE fvco = 3.36 GHz khz offset 54 dbc/hz 5 khz offset 8.3 dbc/hz khz offset 6.3 dbc/hz 8 khz offset 38.5 dbc/hz MHz offset 4 dbc/hz MHz offset 56.3 dbc/hz 4 MHz offset 57.8 dbc/hz Rev. Page 7 of 6

8 ADRF664 Data Sheet LOGIC INPUT/OUTPUT AND POWER SPECIFICATIONS TA = 25 C, frf = 9 MHz, flo = 697 MHz, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 6. Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUT/OUTPUTS SCLK, SDIO, CS Input Voltage High, VIH V Low, VIL.7 V Output Voltage High, VOH IOH = µa 2.3 V Low, VOL IOL = µa.2 V Input Current, IINH/IINL. µa POWER SUPPLIES High Performance Mode Voltage Range VCC, VCC2, VCC7, VCC V VCC3, VCC4, VCC5, VCC6, VCC8, VCC9, VCC, V VCC, IFOUT+, IFOUT, IFOUT2+, IFOUT2 Power Dissipation Internal LO mode (internal PLL) External LO output enabled 2.7 W External LO output disabled 2.5 W High Efficiency Mode Voltage Range VCC, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, V VCC9, VCC, VCC, VCC2, IFOUT+, IFOUT, IFOUT2+, IFOUT2 Power Dissipation Internal LO mode (internal PLL) External LO output enabled 2. W External LO output disabled.8 W Rev. Page 8 of 6

9 ADRF664 DIGITAL LOGIC SPECIFICATIONS Table 7. Symbol Description Min Typ Max Unit tclk Serial clock period 38 ns tds Setup time between data and rising edge of SCLK 8 ns tdh Hold time between data and rising edge of SCLK 8 ns ts Setup time between falling edge of CS and SCLK ns th Hold time between rising edge of CS and SCLK ns thigh Minimum period for SCLK to be in a logic high state ns tlow Minimum period for SCLK to be in a logic low state ns taccess Maximum delay between falling edge of SCLK and output data Valid for a read operation 23 ns tz Maximum delay between CS deactivation and SDIO bus return to high impedance 5 ns CS t S t DS t DH t HIGH t LOW t CLK t H t ACCESS SCLK DON'T CARE DON'T CARE t Z SDIO DON'T CARE A6 A5 A4 A3 A2 A A R/W D5 D4 D3 D3 D2 D D DON'T CARE 45-2 Figure 2. Setup and Hold Timing Measurements Rev. Page 9 of 6

10 ADRF664 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Rating Supply Voltage (VCC, VCC2, VCC3,.5 V to +5.5 V VCC4, VCC5, VCC6, VCC7, VCC8, VCC9, VCC, VCC, VCC2, IFOUT+, IFOUT, IFOUT2+, IFOUT2 ) Digital Input/Output (SCLK, SDIO, CS).3 V to +3.6 V RFINx 2 dbm EXTVCOIN+, EXTVCOIN 3 dbm Maximum Junction Temperature 5 C Operating Temperature Range 4 C to +85 C Storage Temperature Range 65 C to +5 C THERMAL RESISTANCE Data Sheet θjc is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 9. Thermal Resistance Package Type θjc Unit 48-Lead LFCSP.62 C/W ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. Page of 6

11 ADRF664 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADRF664 TOP VIEW (Not to Scale) LOOUT+ LOOUT LDO VCC2 SDIO SCLK CS VCC3 DNC IFOUT2+ IFOUT2 CPOUT VCC2 LDO4 LDO3 REFIN MUXOUT VCC DNC IFOUT+ IFOUT VCOVTUNE EXTVCOIN+ EXTVCOIN VCC DECL DECL2 DECL3 DECL4 DECL5 RFBCT RFIN VCC VCC9 VCC8 VCC7 LDO2 VCC6 VCC5 VCC4 RFIN2 RFBCT2 NOTES. DNC = DO NOT CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH LOW THERMAL IMPEDANCE. Figure 3. Pin Configuration 45-3 Table. Pin Function Descriptions Pin No. Mnemonic Description Common Ground Connection for External Loop Filter. 2 VCOVTUNE Control Voltage for Internal VCO. 3, 6 Common Ground for External VCO. 4, 5 EXTVCOIN+, EXTVCOIN Inputs from External VCO to Internal Divider. 7 VCC 3.7 V VCO Supply. 8, 9 DECL, DECL2 LDO Output Decouplers for VCO., DECL3, DECL4 External Decouplers for VCO Buffer. 2 DECL5 External Decoupler for VCO Circuitry. 3, 4 LOOUT+, LOOUT Differential Outputs of Internally Generated LO. 5 LDO External Decoupling for Internal 2.5 V SPI Port LDO. 6 VCC2 3.7 V Supply for Programmable SPI Port. 7 SDIO Serial Data Input/Output for Programmable SPI Port. 8 SCLK Clock for Programmable SPI Port. 9 CS SPI Chip Select, Active Low. 2, 4 VCC3, VCC 5 V Biases for Channel and Channel 2 IF. 2, 4 DNC Do Not Connect. Do not connect these pins externally. 22, 23 IFOUT2+, IFOUT2 Channel 2 Differential IF Outputs. 24, 37 Ground Connections for Channel and Channel 2 IF Stage. 25 RFBCT2 Balun Center Tap Connection for Channel 2 RF Input. 26 RFIN2 Channel 2 RF Input. 27, 28, 29 VCC4, VCC5, VCC6 5 V Supplies for Mixer LO Amplifiers. 3 LDO2 External Decoupling for Internal 3.3 V PLL/Divider LDO. 3 VCC7 3.7 V Supply for Mixer LO Divider Chain. 32, 33, 34 VCC8, VCC9, VCC 5 V Supplies for Mixer LO Amplifiers. 35 RFIN Channel RF Input. 36 RFBCT Balun Center Tap Connection for Channel RF Input. 38, 39 IFOUT, IFOUT+ Channel Differential IF Outputs. 42 MUXOUT Internal Multiplexer Output. Rev. Page of 6

12 ADRF664 Data Sheet Pin No. Mnemonic Description 43 REFIN Reference Input for Internal PLL (Single-Ended, CMOS). 44 LDO3 External Decoupling for Internal 2.5 V PLL LDO. 45 LDO4 External Decoupling for Internal 3.3 V PLL LDO. 46 VCC2 3.7 V Supply for Internal PLL. 47 CPOUT Charge Pump Output. 48 Common Ground for External Charge Pump. EPAD Exposed Pad. The exposed pad must be connected to a ground plane with low thermal impedance. Rev. Page 2 of 6

13 ADRF664 TYPICAL PERFORMANCE CHARACTERISTICS MIXER, HIGH PERFORMANCE MODE TA = 25 C, frf = 9 MHz, flo = 697 MHz, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. For integer mode: fpfd =.536 MHz, CSCALE = 8 ma, bleed = µa, ABLDLY =.9 ns. For fractional mode: fpfd = 3.72 MHz, CSCALE = 25 µa, bleed = µa, ABLDLY =. ns. POWER DISSIPATION (W) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 4. Power Dissipation vs. RF Frequency over Three Temperatures 45-4 INPUT IP2 (dbm) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 7. Input IP2 vs. RF Frequency over Three Temperatures 45-7 CONVERSION GAIN (db) T A = 4 C, HIGH-SIDE LO 5.5 T A = +25 C, HIGH-SIDE LO 5. T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO 4.5 T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 5. Power Conversion Gain vs. RF Frequency over Three Temperatures, IF Balun and Board Loss Removed INPUT IP3 (dbm) T A = 4 C, HIGH-SIDE LO 6 T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO 4 T A = 4 C, LOW-SIDE LO 2 T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 6. Input IP3 vs. RF Frequency over Three Temperatures INPUT PdB (dbm) SSB NOISE FIGURE (db) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 8. Input PdB vs. RF Frequency over Three Temperatures C LOCKED 4 C EXTERNAL LO +25 C LOCKED +25 C EXTERNAL LO +85 C LOCKED +85 C EXTERNAL LO Figure 9. SSB Noise Figure vs. RF Frequency over Three Temperatures Rev. Page 3 of 6

14 ADRF664 Data Sheet POWER DISSIPATION (W) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO.7 RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO TEMPERATURE ( C) Figure. Power Dissipation vs. Temperature for Three RF Frequencies 45- INPUT IP2 (dbm) RF = 9MHz, LOW-SIDE LO 46 RF = 9MHz, LOW-SIDE LO 44 RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO 42 RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO TEMPERATURE ( C) Figure 3. Input IP2 vs. Temperature for Three RF Frequencies 45-3 CONVERSION GAIN (db) TEMPERATURE ( C) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO Figure. Power Conversion Gain vs. Temperature for Three RF Frequencies 45- INPUT PdB (dbm) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO RF = 27MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 27MHz, HIGH-SIDE LO TEMPERATURE ( C) Figure 4. Input PdB vs. Temperature for Three RF Frequencies INPUT IP3 (dbm) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO 22 RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO 2 RF = 9MHz, HIGH-SIDE LO 2 RF = 25MHz, HIGH-SIDE LO TEMPERATURE ( C) Figure 2. Input IP3 vs. Temperature for Three RF Frequencies 45-2 SSB NOISE FIGURE (db) RF = 9MHz RF = 9MHz RF = 25MHz TEMPERATURE ( C) Figure 5. SSB Noise Figure vs. Temperature for Three RF Frequencies 45-5 Rev. Page 4 of 6

15 ADRF664 POWER DISSIPATION (W) RF = 25MHz, HIGH-SIDE LO RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, LOW-SIDE LO IF FREQUENCY (MHz) Figure 6. Power Dissipation vs. IF Frequency for Three RF Frequencies 45-6 INPUT IP2 (dbm) RF = 9MHz, LOW-SIDE LO 4 RF = 9MHz, LOW-SIDE LO RF = 25MHz, LOW-SIDE LO 35 RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 9. Input IP2 vs. IF Frequency for Three RF Frequencies 45-9 CONVERSION GAIN (db) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 7. Power Conversion Gain vs. IF Frequency for Three RF Frequencies 45-7 INPUT PdB (dbm) RF = 9MHz, LOW-SIDE LO RF = 9MHz, LOW-SIDE LO RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 2. Input PdB vs. IF Frequency for Three RF Frequencies 45-2 INPUT IP3 (dbm) RF = 9MHz, LOW-SIDE LO 6 RF = 9MHz, LOW-SIDE LO 4 RF = 25MHz, LOW-SIDE LO RF = 9MHz, HIGH-SIDE LO 2 RF = 9MHz, HIGH-SIDE LO RF = 25MHz, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 8. Input IP3 vs. IF Frequency for Three RF Frequencies 45-8 SSB NOISE FIGURE (db) 8 4 C, LOW-SIDE LO C, LOW-SIDE LO +85 C, LOW-SIDE LO 4 C, HIGH-SIDE LO C, HIGH-SIDE LO +85 C, HIGH-SIDE LO IF FREQUENCY (MHz) Figure 2. SSB Noise Figure vs. IF Frequency for Three Temperatures 45-2 Rev. Page 5 of 6

16 ADRF664 Data Sheet IF/2 SPURIOUS (db) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 22. IF/2 Spurious vs. RF Frequency over Three Temperatures LO TO IF LEAKAGE (dbm) T A = 4 C T A = +25 C T A = +85 C Figure 25. LO to IF Leakage vs. LO Frequency over Three Temperatures IF/3 SPURIOUS (db) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 23. IF/3 Spurious vs. RF Frequency over Three Temperatures LO TO RF LEAKAGE (dbm) T A = 4 C T A = +25 C T A = +85 C Figure 26. LO to RF Leakage vs. LO Frequency over Three Temperatures T A = 4 C, HIGH-SIDE LO 4 T A = +25 C, HIGH-SIDE LO 6 T A = +85 C, HIGH-SIDE LO 8 T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO 2 T A = +85 C, LOW-SIDE LO RF TO IF ISOLATION (dbc) Figure 24. RF to IF Isolation vs. RF Frequency over Three Temperatures LO LEAKAGE (dbm) T A = 4 C T A = +25 C T A = +85 C LO TO RF 2 LO TO IF Figure LO Leakage vs. LO Frequency over Three Temperatures (2 LO to RF and 2 LO to IF) Rev. Page 6 of 6

17 ADRF664 3 LO LEAKAGE (dbm) T A = 4 C T A = +25 C T A = +85 C 3 LO TO RF LO TO IF Figure LO Leakage vs. LO Frequency over Three Temperatures (3 LO to RF and 3 LO to IF) PERCENT (%) MEAN: 7.94 SD:.7% CONVERSION GAIN (db) Figure 3. Conversion Gain Distribution RETURN LOSS (dbm) HIGH-SIDE LO LOW-SIDE LO PERCENT (%) MEAN: 3.23 SD:.34% INPUT IP3 (dbm) Figure 29. RF Port Return Loss, Fixed IF LO Return Loss Figure 32. Input IP3 Distribution 5 8 MEAN:.59 SD:.39% RETURN LOSS (db) 5 2 PERCENT (%) INPUT PdB (dbm) Figure 3. LO Return Loss Figure 33. Input PdB Distribution Rev. Page 7 of 6

18 ADRF664 Data Sheet 2 8 RESISTANCE (Ω) FREQUENCY (MHz) CAPACITANCE (pf) IF CHANNEL-TO-CHANNEL ISOLATION (dbc) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO 3 T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO 25 T A = +25 C, LOW-SIDE LO 2 T A = +85 C, LOW-SIDE LO Figure 34. IF Output Impedance (R Parallel C Equivalent) Figure 37. IF Channel to Channel Isolation vs. RF Frequency over Three Temperatures CONVERSION GAIN (db) BAL_COUT = 3 BAL_COUT = 2 BAL_COUT = 4 2 BAL_COUT = 6 BAL_COUT = 8 BAL_COUT = BAL_COUT = 2 BAL_COUT = INPUT IP3 (dbm) BAL_COUT = BAL_COUT = 2 BAL_COUT = 4 BAL_COUT = 6 BAL_COUT = 8 BAL_COUT = BAL_COUT = 2 BAL_COUT = Figure 35. Conversion Gain vs. RF Frequency for All RFB Settings, VGS Bit and LPF Use Optimum Settings Figure 38. Input IP3 vs. RF Frequency for All RFB Settings, VGS Bit and LPF Use Optimum Settings INPUT PdB (dbm) BAL_COUT = BAL_COUT = 2 BAL_COUT = 4 BAL_COUT = 6 BAL_COUT = 8 BAL_COUT = BAL_COUT = 2 BAL_COUT = Figure 36. Input PdB vs. RF Frequency for All RFB Settings, VGS Bit and LPF Use Optimum Settings SSB NOISE FIGURE (db) BAL_COUT = BAL_COUT = 2 BAL_COUT = 4 BAL_COUT = 6 BAL_COUT = 8 BAL_COUT = BAL_COUT = 2 BAL_COUT = Figure 39. SSB Noise Figure vs. RF Frequency for All RFB Settings, VGS Bit and LPF Use Optimum Settings Rev. Page 8 of 6

19 ADRF664 CONVERSION GAIN (db) INPUT IP3 (dbm) VGS = VGS = VGS = 2 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = Figure 4. Conversion Gain vs. RF Frequency for All VGS Bit Settings, RFB and LPF Use Optimum Settings VGS = VGS = VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = Figure 4. Input IP3 vs. RF Frequency for All VGS Bit Settings, RFB and LPF Use Optimum Settings INPUT PdB (dbm) SSB NOISE FIGURE (db) VGS = VGS = VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = Figure 43. Input PdB vs. RF Frequency for All VGS Bit Settings, RFB and LPF Use Optimum Settings VGS = VGS = VGS = 2 VGS = 3 VGS = 4 VGS = 5 VGS = 6 VGS = Figure 44. SSB Noise Figure vs. RF Frequency for All VGS Bit Settings, RFB and LPF Use Optimum Settings CONVERSION GAIN (db) LPF = LPF = 2 LPF = 4 LPF = Figure 42. Conversion Gain vs. RF Frequency for All LPF Settings, RFB and VGS Bit Use Optimum Settings INPUT PdB (dbm) LPF = LPF = 2 LPF = 4 LPF = Figure 45. Input PdB vs. RF Frequency for All LPF Settings, RFB and VGS Bit Use Optimum Settings Rev. Page 9 of 6

20 ADRF664 Data Sheet INPUT IP3 (dbm) LPF = LPF = 2 LPF = 4 LPF = Figure 46. Input IP3 vs. RF Frequency for All LPF Settings, RFB and VGS Bit Use Optimum Settings SSB NOISE FIGURE (db) LPF = LPF = 2 LPF = 4 LPF = Figure 49. SSB Noise Figure vs. RF Frequency for All LPF Settings, RFB and VGS Bit Use Optimum Settings 45-5 POWER DISSIPATION (W) IFA_MAINBIAS = 3 IFA_MAINBIAS = 4 IFA_MAINBIAS = 5 IFA_MAINBIAS = 6 IFA_MAINBIAS = 7 IFA_MAINBIAS = 8 IFA_MAINBIAS = 9 IFA_MAINBIAS = IFA_MAINBIAS = IFA_MAINBIAS = TEMPERATURE ( C) IFA_MAINBIAS = 3 IFA_MAINBIAS = 4 IFA_MAINBIAS = 5 Figure 47. Power Dissipation vs. Temperature for Various IFA_MAINBIAS Settings INPUT IP3 (dbm) IFA_MAINBIAS = 3 IFA_MAINBIAS = IFA_MAINBIAS = 4 IFA_MAINBIAS = 5 IFA_MAINBIAS = 5 IFA_MAINBIAS = 2 IFA_MAINBIAS = 6 IFA_MAINBIAS = 3 IFA_MAINBIAS = 7 IFA_MAINBIAS = 4 IFA_MAINBIAS = 8 IFA_MAINBIAS = 5 IFA_MAINBIAS = TEMPERATURE ( C) Figure 5. Input IP3 vs. Temperature for Various IFA_MAINBIAS Settings POWER DISSIPATION (W) IFA_LINBIAS = IFA_LINBIAS = IFA_LINBIAS = 2 IFA_LINBIAS = 3 IFA_LINBIAS = 4 IFA_LINBIAS = 5 IFA_LINBIAS = 6 IFA_LINBIAS = 7 IFA_LINBIAS = 8 IFA_LINBIAS = 9 IFA_LINBIAS = IFA_LINBIAS = IFA_LINBIAS = 2 IFA_LINBIAS = 3 IFA_LINBIAS = 4 IFA_LINBIAS = TEMPERATURE ( C) Figure 48. Power Dissipation vs. Temperature for Various IFA_LINBIAS Settings INPUT IP3 (dbm) IFA_LINBIAS = IFA_LINBIAS = 8 IFA_LINBIAS = IFA_LINBIAS = 9 IFA_LINBIAS = 2 IFA_LINBIAS = 24 IFA_LINBIAS = 3 IFA_LINBIAS = IFA_LINBIAS = 4 IFA_LINBIAS = 2 IFA_LINBIAS = 5 IFA_LINBIAS = 3 IFA_LINBIAS = 6 IFA_LINBIAS = 4 22 IFA_LINBIAS = 7 IFA_LINBIAS = TEMPERATURE ( C) Figure 5. Input IP3 vs. Temperature for Various IFA_LINBIAS Settings Rev. Page 2 of 6

21 ADRF MHz +dbm 9MHz +dbm 25MHz +dbm MHz +dbm 9MHz +dbm 25MHz +dbm 8 8 PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) OFFSET FREQUENCY (MHz) Figure 52. Phase Noise at IF Output vs. Offset Frequency with dbm Blocker in Integer Mode OFFSET FREQUENCY (MHz) Figure 53. Phase Noise at IF Output vs. Offset Frequency with dbm Blocker in Fractional Mode Rev. Page 2 of 6

22 ADRF664 Data Sheet MIXER, HIGH EFFICIENCY MODE TA = 25 C, frf = 9 MHz, flo = 697 MHz, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. POWER DISSIPATION (W) T A = 4 C, HIGH-SIDE LO T A = 25 C, HIGH-SIDE LO T A = 85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = 25 C, LOW-SIDE LO T A = 85 C, LOW-SIDE LO Figure 54. Power Dissipation vs. RF Frequency over Three Temperatures 45-5 INPUT IP2 (dbm) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO 35 T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 57. Input IP2 vs. RF Frequency over Three Temperatures CONVERSION GAIN (db) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 55. Conversion Gain vs. RF Frequency over Three Temperatures INPUT PdB (dbm) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 58. Input PdB vs. RF Frequency over Three Temperatures INPUT IP3 (dbm) T A = 4 C, HIGH-SIDE LO T A = +25 C, HIGH-SIDE LO T A = +85 C, HIGH-SIDE LO T A = 4 C, LOW-SIDE LO T A = +25 C, LOW-SIDE LO T A = +85 C, LOW-SIDE LO Figure 56. Input IP3 vs. RF Frequency over Three Temperatures SSB NOISE FIGURE (db) C LOCKED 4 C EXTERNAL LO +25 C LOCKED +25 C EXTERNAL LO +85 C LOCKED +85 C EXTERNAL LO Figure 59. SSB Noise Figure vs. RF Frequency over Three Temperatures Rev. Page 22 of 6

23 ADRF664 SYNTHESIZER VS = high performance mode, TA = 25 C, measured on LO output, flo = 7 MHz, ZO = 5 Ω, fref = MHz, fpfd =.536 MHz, fref power = 4 dbm, integer mode loop filter, unless otherwise noted. OPEN-LOOP PHASE NOISE (dbc/hz) CLOSED-LOOP PHASE NOISE (dbc/hz) LO_DIV = 2 LO_DIV = 4 LO_DIV = 8 OPEN-LOOP PHASE NOISE (dbc/hz) OPEN-LOOP PHASE NOISE (dbc/hz) 8 k k k M M M OFFSET FREQUENCY (Hz) Figure 6. VCO_ Open-Loop Phase Noise vs. Offset Frequency, fvco_ = 2.55 GHz, Divide by Two Selected, VCOVTUNE =.5 V k k k M M M OFFSET FREQUENCY (Hz) Figure 6. VCO_ Open-Loop Phase Noise vs. Offset Frequency, fvco_ = 2.2 GHz, Divide by Two Selected, VCOVTUNE =.5 V k k k M M M OFFSET FREQUENCY (Hz) Figure 62. VCO_2 Open-Loop Phase Noise vs. Offset Frequency, fvco_2 =.9 GHz, Divide by Two Selected, VCOVTUNE =.5 V OFFSET FREQUENCY (MHz) Figure 63. VCO_ Closed-Loop Phase Noise vs. Offset Frequency for Various LO_DIV Dividers, fvco_ = 5. GHz CLOSED-LOOP PHASE NOISE (dbc/hz) LO_DIV = 2 LO_DIV = 4 LO_DIV = OFFSET FREQUENCY (MHz) Figure 64. VCO_ Closed-Loop Phase Noise vs. Offset Frequency for Various LO_DIV Dividers, fvco_ = 4.5 GHz CLOSED-LOOP PHASE NOISE (dbc/hz) LO_DIV = 2 LO_DIV = 4 LO_DIV = OFFSET FREQUENCY (MHz) Figure 65. VCO_2 Closed-Loop Phase Noise vs. Offset Frequency for Various LO_DIV Dividers, fvco_2 = 3.8 GHz Rev. Page 23 of 6

24 ADRF664 Data Sheet OPEN-LOOP PHASE NOISE (dbc/hz) CLOSED-LOOP PHASE NOISE (dbc/hz) LO_DIV = 2 LO_DIV = 4 LO_DIV = 8 OPEN-LOOP PHASE NOISE (dbc/hz) OPEN-LOOP PHASE NOISE (dbc/hz) 6 k k k M M M OFFSET FREQUENCY (Hz) Figure 66. VCO_3 Open-Loop Phase Noise vs. Offset Frequency, fvco_3 =.6 GHz, Divide by Two Selected, VCOVTUNE =.5 V k k k M M M OFFSET FREQUENCY (Hz) Figure 67. VCO_4 Open-Loop Phase Noise vs. Offset Frequency, fvco_4 = 3.87 GHz, Divide by One Selected, VCOVTUNE =.5 V k k k M M M OFFSET FREQUENCY (Hz) Figure 68. VCO_5 Open-Loop Phase Noise vs. Offset Frequency, fvco_5 = GHz, Divide by One Selected, VCOVTUNE =.5 V OFFSET FREQUENCY (MHz) Figure 69. VCO_3 Closed-Loop Phase Noise for Various LO_DIV Dividers vs. Offset Frequency, fvco_3 = 3.2 GHz CLOSED-LOOP PHASE NOISE (dbc/hz) C +25 C +85 C 8... OFFSET FREQUENCY (MHz) Figure 7. VCO_4 Closed-Loop Phase Noise for Various Temperatures vs. Offset Frequency, fvco_4 =.536 GHz, Divide by Two Selected CLOSED-LOOP PHASE NOISE (dbc/hz) C +25 C +85 C 8... OFFSET FREQUENCY (MHz) Figure 7. VCO_5 Closed-Loop Phase Noise for Various Temperatures vs. Offset Frequency, fvco_5 =.688 GHz, Divide by Two Selected Rev. Page 24 of 6

25 ADRF664 FOM (dbc/hz/hz) C +25 C +85 C OPEN-LOOP PHASE NOISE (dbc/hz) kHz OFFSET 2kHz OFFSET MHz OFFSET 4MHz OFFSET 4 C +25 C +85 C Figure 72. PLL Figure of Merit (FOM) vs. LO Frequency, Integer Mode Figure 75. Open-Loop Phase Noise vs. LO Frequency, Divide by Two Selected OPEN-LOOP PHASE NOISE (dbc/hz) C +25 C +85 C khz OFFSET khz OFFSET 5kHz OFFSET MHz OFFSET PHASE NOISE (dbc/hz) C +25 C +85 C khz OFFSET khz OFFSET 5kHz OFFSET MHz OFFSET Figure 73. Open-Loop Phase Noise vs. LO Frequency, Divide by Two Selected Figure 76. Integer Loop Filter Phase Noise vs. LO Frequency, Divide by Two Selected, Offset = khz, khz, 5 khz, and MHz C +25 C +85 C C +25 C +85 C khz OFFSET FOM (dbc/hz/hz) PHASE NOISE (dbc/hz) 2 4 khz OFFSET 5kHz OFFSET MHz OFFSET Figure 74. PLL Figure of Merit (FOM) vs. LO Frequency, Fractional Mode, Offset = 45 khz, Bleed = 25 µa Figure 77. VCO_4 GSM Loop Filter Phase Noise, Divide by Two Selected, Offset = khz, khz, 5 khz, and MHz Rev. Page 25 of 6

26 ADRF664 Data Sheet PHASE NOISE (dbc/hz) C +25 C +85 C 5 khz OFFSET 2 khz OFFSET MHz OFFSET 4MHz OFFSET LO FREQUENCY (Hz) Figure 78. Integer Loop Filter Phase Noise vs. LO Frequency, Divide by Two Selected, Offset = 5 khz, 2 khz, MHz, and 4 MHz PHASE NOISE (dbc/hz) C +25 C +85 C 5kHz OFFSET 2kHz OFFSET MHz OFFSET 4MHz OFFSET Figure 79. VCO_4 GSM Loop Filter Phase Noise, Divide by Two Selected, Offset = 5 khz, 2 khz, MHz, and 4 MHz PHASE NOISE (dbc/hz) C +25 C +85 C khz OFFSET khz OFFSET 5kHz OFFSET MHz OFFSET Figure 8. VCO_5 GSM Loop Filter Phase Noise, Divide by Two Selected, Offset = khz, khz, 5 khz, and MHz INTEGRATED PHASE NOISE, WITH SPURS ( rms) C +25 C +85 C LO_DIV = 2 LO_DIV = 4 LO_DIV = VCO FREQUENCY (MHz) Figure 8. khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, Divide by Two, Four, and Eight, Including Spurs INTEGRATED PHASE NOISE WITH SPURS ( rms) PHASE NOISE (dbc/hz) C +25 C +85 C Figure 82. VCO_4 khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, For Various Temperatures, Including Spurs C +25 C +85 C 5kHz OFFSET 2kHz OFFSET MHz OFFSET 4MHz OFFSET Figure 83. VCO_5 GSM Loop Filter Phase Noise, Divide by Two Selected, Offset = 5 khz, 2 khz, MHz, and 4 MHz Rev. Page 26 of 6

27 ADRF664 INTEGRATED PHASE NOISE, WITHOUT SPURS ( rms) C +25 C +85 C LO_DIV = 2 LO_DIV = 8 LO_DIV = VCO FREQUENCY (MHz) Figure 84. khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, Divide by Two, Four, and Eight, Excluding Spurs INTEGRATED PHASE NOISE WITHOUT SPURS ( rms) C +25 C +85 C Figure 85. VCO_4 khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, For Various Temperatures, Excluding Spurs REFERENCE SPURS (dbc), PFD OFFSET REFERENCE SPURS (dbc), 3 PFD OFFSET C LO_DIV = C LO_DIV = C LO_DIV = 2 4 C LO_DIV = C LO_DIV = C LO_DIV = 4 4 C LO_DIV = C LO_DIV = C LO_DIV = 8 VCO FREQUENCY (MHz) Figure 87. fpfd Reference Spurs vs. VCO Frequency, PFD Offset, Measured at LO Output, Integer Mode 4 C LO_DIV = C LO_DIV = C LO_DIV = 2 4 C LO_DIV = C LO_DIV = C LO_DIV = 4 4 C LO_DIV = C LO_DIV = C LO_DIV = VCO FREQUENCY (MHz) Figure 88. fpfd Reference Spurs vs. VCO Frequency, 3 PFD Offset, Measured at LO Output, Integer Mode INTEGRATED PHASE NOISE WITH SPURS ( rms) C +25 C +85 C Figure 86. VCO_5 khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, For Various Temperatures, Including Spurs INTEGRATED PHASE NOISE WITHOUT SPURS ( rms) C +25 C +85 C Figure 89. VCO_5 khz to 4 MHz Integrated Phase Noise vs. VCO Frequency, For Various Temperatures, Excluding Spurs Rev. Page 27 of 6

28 ADRF664 Data Sheet REFERENCE SPURS (dbc), 4 PFD OFFSET C LO_DIV = C LO_DIV = C LO_DIV = 2 4 C LO_DIV = C LO_DIV = C LO_DIV = 4 4 C LO_DIV = C LO_DIV = C LO_DIV = 8 REFERENCE SPURS (dbc), 2 PFD OFFSET C +25 C +85 C VCO FREQUENCY (MHz) Figure 9. fpfd Reference Spurs vs. VCO Frequency, 2 PFD Offset, Measured at LO Output, Integer Mode Figure 93. fpfd Reference Spurs vs. LO Frequency, 2 PFD Offset, Measured at LO Output, Fractional Mode REFERENCE SPURS (dbc), 4 PFD OFFSET C LO_DIV = /2 +25 C LO_DIV = /2 +85 C LO_DIV = /2 4 C LO_DIV = /4 +25 C LO_DIV = /4 +85 C LO_DIV = /4 4 C LO_DIV = /8 +25 C LO_DIV = /8 +85 C LO_DIV = /8 REFERENCE SPURS (dbc), 3 PFD OFFSET C +25 C +85 C VCO FREQUENCY (MHz) Figure 9. fpfd Reference Spurs vs. VCO Frequency, 4 PFD Offset, Measured at LO Output, Integer Mode Figure 94. fpfd Reference Spurs vs. LO Frequency, 3 PFD Offset, Measured at LO Output, Fractional Mode REFERENCE SPURS (dbc), PFD OFFSET C +25 C +85 C REFERENCE SPURS (dbc), 4 PFD OFFSET C +25 C +85 C Figure 92. fpfd Reference Spurs vs. LO Frequency, PFD Offset, Measured at LO Output, Fractional Mode Figure 95. fpfd Reference Spurs vs. LO Frequency, 4 PFD Offset, Measured at LO Output, Fractional Mode Rev. Page 28 of 6

29 ADRF664 REFERENCE SPURS (dbc), PFD OFFSET IF AT 4 C IF AT +25 C IF AT +85 C LO AT 4 C LO AT +25 C LO AT +85 C ISOLATION (db) Figure 96. fpfd Reference Spurs vs. LO Frequency, Divide by Two Selected, PFD Offset, Measured on LO Output and IF Output Figure 99. RF to LO Output Feedthrough, LO_DRV_LVL = LO AMPLITUDE (dbm) LO_DRV_LVL = AT 4 C LO_DRV_LVL = AT +25 C LO_DRV_LVL = AT +85 C LO_DRV_LVL = AT 4 C LO_DRV_LVL = AT +25 C LO_DRV_LVL = AT +85 C 8 LO_DRV_LVL = 2 AT 4 C LO_DRV_LVL = 3 AT 4 C LO_DRV_LVL = 2 AT +25 C LO_DRV_LVL = 3 AT +25 C LO_DRV_LVL = 2 AT +85 C LO_DRV_LVL = 3 AT +85 C Figure 97. LO Amplitude vs. LO Frequency, LO_DRV_LVL =,, 2, and LOCK TIME (ms) Figure. LO Frequency Settling Time, Integer Mode Loop Filter, Integer Mode VCC7 SUPPLY CURRENT (ma) LO_DRV_LVL = AT 4 C 45 LO_DRV_LVL = AT +25 C LO_DRV_LVL = AT +85 C 35 LO_DRV_LVL = AT 4 C LO_DRV_LVL = AT +25 C LO_DRV_LVL = AT +85 C LO_DRV_LVL = 3 AT 4 C LO_DRV_LVL = 3 AT +25 C LO_DRV_LVL = 3 AT +85 C LO_DRV_LVL = 2 AT 4 C LO_DRV_LVL = 2 AT +25 C LO_DRV_LVL = 2 AT +85 C Figure 98. Supply Current for VCC7 vs. LO Frequency, LO_DRV_LVL =,, 2, and LOCK TIME (ms) Figure. LO Frequency Settling Time, Fractional Loop Filter, Fractional Mode Rev. Page 29 of 6

30 ADRF664 Data Sheet C 4 C GHz 3.8GHz 4.45GHz 5.8GHz V TUNE (V).5..5 PFD SPURS (dbc) Figure 2. VCO Tuning Voltage (VTUNE) vs. LO Frequency for Lock at Cold Drift to Hot OFFSET FREQUENCY (MHz) Figure 4. PFD Spurs vs. Offset Frequency for Four VCOs, Integer Mode C 4 C C 4 C 2.5 V TUNE (V).5..5 V TUNE (V) Figure 3. VTUNE vs. LO Frequency for Lock at Hot Drift to Cold Figure 5. VCO_4 VTUNE vs. LO Frequency for Lock at Hot Drift to Cold Rev. Page 3 of 6

31 ADRF C 4 C C 4 C V TUNE (V) 2..5 V TUNE (V) Figure 6. VCO_5 VTUNE vs. LO Frequency for Lock at Hot Drift to Cold Figure 8. VCO_5 VTUNE vs. LO Frequency for Lock at Cold Drift to Hot C 4 C 2.5 V TUNE (V) Figure 7. VCO_4 VTUNE vs. LO Frequency for Lock at Cold Drift to Hot Rev. Page 3 of 6

32 ADRF664 Data Sheet SPURIOUS PERFORMANCE (N frf) (M flo) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dbc from the IF output power level. Data was measured only for frequencies less than 6 GHz; blank cells indicate frequencies that were not measured. Typical noise floor of the measurement system = dbm. High Performance Mode VS = high performance mode, TA = 25 C, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table. RF = 9 MHz, LO = 697 MHz M < 68.3 < 8.6 < < 79.5 < 94. < < < < N 4 < 56.6 < < < < < < < < 5 < 43.6 < < < < < < < < 6 < 66.7 < < < < < < < < < < < < < < < < 8 < < < < < < < < 9 < < < < < < Table 2. RF = 9 MHz, LO = 697 MHz M < 3 < < < < < N 4 < < < < < < < < 5 < < < < < < < 6 < < < < < < 7 < < < < < 8 < < < < 9 < < < Table 3. RF = 25 MHz, LO = 2297 MHz M < < < N 4 < < < < < 5 < < < < < < 6 < < < 92.5 < < 7 < < < < 8 < < < 9 < < Rev. Page 32 of 6

33 ADRF664 High Efficiency Mode VS = high efficiency mode, TA = 25 C, ZO = 5 Ω, fref = MHz, fref power = 4 dbm, fpfd =.536 MHz, low-side LO injection, optimum RFB and LPF settings, unless otherwise noted. Table 4. RF = 9 MHz, LO = 697 MHz M < 79. < < 85. < < < < N 4 < < 97.9 < < < < < < < 5 < < < < < < < < < < 6 < < < < < < < < < < 7 < < < < < < < < < 8 < < < < < < < < 9 < < < < < < Table 5. RF = 9 MHz, LO = 697 MHz M < 3 < < < < < N 4 < < < < < < < < 5 < < < < < < < 6 < < < < < < 7 < < < < < 8 < < < < 9 < < < Table 6. RF = 25 MHz, LO = 2297 MHz M < < N < < < < 5 < < < < < < 6 < < < < < < 7 < < < < 8 < < < 9 < < Rev. Page 33 of 6

34 ADRF664 THEORY OF OPERATION The ADRF664 consists of two primary components: the RF subsystem and the LO subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance device with excellent electrical, mechanical, and thermal properties. The wideband frequency response and flexible frequency programming simplifies the receiver design, saves on-board space, and minimizes the need for external components. The RF subsystem consists of an integrated, tunable, low loss RF balun, a double balanced, passive MOSFET mixer, a tunable sum termination network, and an IF amplifier. The LO subsystem consists of a multistage, limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A schematic of the device is shown in Figure. RF SUBSYSTEM The single-ended, 5 Ω RF input is internally transformed to a balanced signal using a tunable, low loss, unbalanced to balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended to use a blocking capacitor to avoid running excessive dc current through the device. The RF balun can easily support an RF input frequency range of 7 MHz to 3 MHz. This balun is tuned over the frequency range by a SPI controlled switched capacitor network at the output of the RF balun. The resulting balanced RF signal is applied to a passive mixer that commutates the RF input in accordance with the output of the LO subsystem. The passive mixer is a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms. The IF amplifier is a balanced feedback design that simultaneously provides the gain, noise figure, and input impedance required to achieve the overall performance. The balanced open-collector output of the IF amplifier, with an impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, a differential amplifier, or an REFIN TO 89 (REG x2[:]) PFD CPOUT CHARGE PUMP Data Sheet analog-to-digital converter (ADC) input while providing optimum second-order intermodulation suppression. The differential output impedance of the IF amplifier is approximately 2 Ω. If operation in a 5 Ω system is desired, the output can be transformed to 5 Ω by using a 4: transformer or an LC impedance matching network. EXTERNAL LO GENERATION The ADRF664 LO can be generated by an externally applied source or by using the internal PLL synthesizer. To select the external LO mode, write to Register x22, Bits[2:] and apply the differential LO signal to Pin 4 (EXTVCOIN+) and Pin 5 (EXTVCOIN ). Internal dividers allow the externally applied LO signal to be divided before this signal arrives at the mixer LO input. The divider value is set by Register x22, Bits[5:3] and has possible values of, 2, 4, and 8. With the divider set to, the externally applied LO input frequency range is 25 MHz to 285 MHz. When using a divider value of other than, the maximum externally applied LO frequency is 57 MHz. The external LO input pins present a broadband differential 5 Ω input impedance. The EXTVCOIN+ and EXTVCOIN input pins must be ac-coupled. When not in use, EXTVCOIN+ and EXTVCOIN can be left unconnected. INTERNAL LO GENERATION Reference Input Circuitry The ADRF664 includes an on-chip PLL for LO synthesis. The PLL, shown in Figure 9, consists of a reference input and input dividers, a PFD, a charge pump, VCOs, and a programmable fractional/integer divider with a 2 prescaler. The reference path takes in a reference clock and divides it by a factor of to 89 before passing it to the PFD. The PFD compares this signal to the divided down signal from the VCO. Depending on the PFD polarity selected, the PFD sends an up or down signal to the charge pump if the VCO signal is slow or fast compared to the reference frequency. The charge pump sends a current pulse to the off-chip loop filter to increase or decrease the tuning voltage (VCOVTUNE). R7 C8 C2 C22 CP VCOVTUNE LOOP FILTER R8 R C23 N = INT + FRAC MOD (REG x2, REG x3, REG x4) 2 PRESCALER MIXER LO MIXER 2 LO Rev. Page 34 of 6 LO DIVIDER (, 2, 4, 8, 6, 32) (REG x22[5:3]) Figure 9. LO Generation Block Diagram EXTERNAL LO INPUT 45-9

35 In-band (within the band of the loop filter) phase noise performance is typically limited by the reference source. Due to the inherent phase noise reduction when performing frequency division, improved in-band phase noise performance can be achieved with higher reference divide values. However, the divide chain adds its own small amount of phase noise; thus, there is a limit on how much improvement can be gained by increasing the divider value. Loop Filters Defining a loop filter for the ADRF664 depends on several dynamic: the PLL REFIN and PFD frequency and desired PFD and fractional spur levels. Higher reference and PFD frequencies spread the PFD spurs over a wider bandwidth (wider separation between spurs), but also lead to higher levels of spurs coupling through the reference divider chain. Lower reference and PFD frequencies lower the spacing between PFD spurs, but the spur levels can be significantly improved by using lower frequencies. At lower PFD frequencies, it may also be possible to achieve the desired synthesizer frequency step size using the integer divider mode, therefore eliminating the risk of fractional spurs. Table 7 shows the recommended loop filter components and dynamic loop settings when using integer mode and PFD frequencies at less than MHz. Table 7. Integer Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components PLL Dynamic Settings C8 5 pf R7 9 Ω C2 33 nf R8.8 kω C22 56 pf R 2 kω C23 39 pf CSCALE 8 µa Bleed Current µa ABLDLY.9 ns If a smaller frequency step size is desired, the ADRF664 can be used in fractional mode. The 6-bit FRAC_DIV and MOD_DIV values available in the ADRF664 mean that small step sizes can be achieved with high PFD frequencies. PFD spurs may be higher in amplitude, but are spaced further apart. Fractional spurs may be present as well. ADRF664 Table 8. Fractional Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components PLL Dynamic Settings C8 pf R7 7 Ω C2 33 nf R8.8 kω C22 56 pf R 2 kω C23 39 pf CSCALE 5 µa Bleed Current µa ABLDLY ns For GSM mode of operation at the PFD rate of.536 MHz, the recommended loop filter components and dynamic loop settings are shown in Table 9. Table 9. GSM Mode Loop Filter Components and PLL Dynamic Settings Loop Filter Components PLL Dynamic Settings C8 22 pf R7.2 kω C2 47 nf R8 kω C22 2 pf R 6.2 kω C23 33 pf CSCALE 8 ma Bleed Current µa ABLDLY.9 ns VCOs and Dividers The ADRF664 has six internal VCOs. Considering the range of these VCOs, the fixed 2 prescaler after the VCO, and the LO_DIV (, 2, 4, 8, 6, and 32) range, the total LO range allows an RF generation of 2 MHz to 27 MHz. Table 2. VCO Range VCO_SEL (Register x22, Bits[2:]) Frequency Range (GHz) 4.6 to to to to to to 3.46 Rev. Page 35 of 6

36 ADRF664 For the VCO_, VCO_, VCO_2, and VCO_3 selections, it is required to set VTUNE_DAC_SLOPE (Register x49, Bits[3:9]) = d, VTUNE_DAC_OFFSET (Register x49, Bits[8:]) = 84d, VCO_LDO_R2 (Register x22, Bits[:8]) = d, and VCO_ LDO_R4 (Register x22, Bits[5:2]) = 5d. For VCO_4 and VC_5 selections, the required settings are VTUNE_DAC_ SLOPE (Register x49, Bits[3:9]) = 9d, VTUNE_DAC_OFFSET (Register x49, Bits[8:]) = 7d, VCO_LDO_R2 (Register x22, Bits[:8]) = 2d, and VCO_LDO_R4 (Register x22, Bits[5:2]) = d. In transitioning from a GSM VCO (VCO_4 and VCO_5) to an octave VCO, the LDO settings must be changed before changing the VCO selection. The N-divider divides down the differential VCO signal to the PFD frequency. The N-divider can be configured for fractional mode or integer mode by addressing the DIV_MODE bit (Register x2, Bit 5). The default configuration is set for fractional mode. The following equations can be used to determine the N value and the PLL frequency: f PFD fvco = 2 N where: fpfd is the phase frequency detector frequency. fvco is the voltage controlled oscillator frequency. N is the fractional divide ratio. N = INT + FRAC MOD where: INT is the integer divide ratio programmed in Register x2. FRAC is the fractional divide ratio programmed in Register x3. MOD is the modulus divide ratio programmed in Register x4. f PFD 2 N f LO = LO_DIVIDER where: flo is the LO frequency going to the mixer core when the loop is locked. LO_DIVIDER is the final divider block that divides the VCO frequency down by, 2, 4, or 8 before it reaches the mixer (see Table 2). This control is located in the LO_DIV bits (Register x22, Bits[5:3]). Table 2. LO Divider LO_DIV (Register x22, Bits[5:3]) LO_DIVIDER Data Sheet The lock detect signal is available as one of the selectable outputs through the MUXOUT pin; a logic high indicates that the loop is locked. The MUXOUT pin is controlled by the REF_MUX_SEL bits (Register x2, Bits[4:3]); the PLL lock detect signal is the default configuration. To ensure that the PLL locks to the desired frequency, follow the proper write sequence of the PLL registers. The PLL registers must be configured accordingly to achieve the desired frequency, and the last writes must be to Register x2 (INT_DIV in Table 26), Register x3 (FRAC_DIV in Table 26), or Register x4 (MOD_DIV in Table 26). When one of these registers is programmed, an internal VCO calibration is initiated, which is the last step in locking the PLL. The time it takes to lock the PLL after the last register is written can be broken down into two parts: VCO band calibration and loop settling. After the last register is written, the PLL automatically performs a VCO band calibration to choose the correct VCO band. This calibration takes approximately 52 PFD cycles. For a 4 MHz fpfd, this corresponds to 28 µs. After calibration is complete, the feedback action of the PLL causes the VCO to lock eventually to the correct frequency. The speed with which this locking occurs depends on the nonlinear cycle slipping behavior, as well as the small signal settling of the loop. For an accurate estimation of the lock time, download the ADIsimPLL tool, which correctly captures these effects. In general, higher bandwidth loops tend to lock faster than lower bandwidth loops. Additional LO Controls To access the LO signal going to the mixer core through the LOOUT+ and LOOUT pins (Pin 3 and Pin 4), enable the LO_DRV_EN bit in Register x, Bit 7. This setting offers direct monitoring of the LO signal to the mixer for debug purposes; or the LO signal can be used to daisy-chain many devices synchronously. One ADRF664 can serve as the master where the LO signal is sourced, and the subsequent slave devices share the same LO signal from the master. This flexibility substantially eases the LO requirements of a system with multiple LOs. The LO output drive level is controlled by the LO_DRV_LVL bits (Register x22, Bits[7:6]). Table 22 shows the available drive levels. Table 22. LO Drive Levels LO_DRV_LVL (Register x22, Bits[7:6]) Amplitude (dbm) Rev. Page 36 of 6

37 ADRF664 DECL DECL2 DECL3 VCC2 VCC3 VCC4 VCC5 28 VCC6 29 VCC7 3 VCC8 32 EXTVCOIN+ 4 EXTVCOIN 5 26 RFIN2 25 RFBCT2 SDIO SCLK CS LOOUT+ LOOUT DNC IFOUT2+ IFOUT2 LDO LDO2 VCC2 VCC VCC VCOVTUNE CPOUT REFIN MUXOUT DNC IFOUT+ IFOUT VCO LDO DECL PLL CHARGE PUMP 3.3V LDO 2 DECL5 45 LDO4 VCO VCO DIVIDE BY TO RFIN 36 RFBCT VCO SPI CONTROL SPI 2.5V LDO LO DIV 3.3V LDO 44 LDO VCC EXPOSED PAD VCC 7 REFIN DIVIDER VCO BUFFER LDO PFD LOCK DETECT VPTAT SCAN VCO BAND SWITCH LDO N-DIVIDER INT N-DIVIDER 2.5V LDO 45-9 Figure. Simplified Schematic Rev. Page 37 of 6

38 ADRF664 APPLICATIONS INFORMATION The ADRF664 mixer is designed to downconvert radio frequencies (RF) primarily between 7 MHz and 3 MHz to lower intermediate frequencies (IF) between 4 MHz to 5 MHz. Figure depicts the basic connections of the mixer. It is Data Sheet recommended to ac couple the RF and LO input ports to prevent nonzero dc voltages from damaging the RF balun or LO input circuit. A RFIN capacitor value of 22 pf is recommended. +5V µf (63) µf (63) µf (63) µf (63) µf (63) µf (63) µf (63) µf (63) LOIN µf (63).µF.µF.µF.µF.µF.µF.µF.µF pf pf µf (63) µf (63).µF pf pf pf pf pf pf pf pf µf (63).µF.µF pf EXPOSED PAD VCC 7 VCC2 6 VCC3 2 VCC4 27 VCC5 28 VCC6 29 VCC7 3 VCC8 32 EXTVCOIN+ 4 EXTVCOIN 5 22pF.µF pf kω 6.8pF pf VCC2 46 pf VCC 4 VCC VCO VCO VCO 34 VCC9 33 VCOVTUNE 2 kω CPOUT 47 22pF 27pF 3.6kΩ REFIN DIVIDER PFD N-DIVIDER SPI CONTROL REFIN 43 5Ω pf MUXOUT 42 DIVIDE BY TO 32 REFIN DNC 33nH 4 LOCK DETECT VPTAT SCAN IFOUT+ IFOUT nH 5pF 5pF VCO LDO DECL 8 DECL2 PLL CHARGE PUMP 3.3V LDO SPI 2.5V LDO 5pF 9 VCO BUFFER LDO VCO BAND SWITCH LDO INT N-DIVIDER 2.5V LDO LO DIV 3.3V LDO pf pf IFOUT LDO pF RFIN 35 RFBCT 36 RFIN2 26 RFBCT2 25 LDO3 44 µf (63) µf (63) DECL3 pf DECL4 pf DECL5 2 pf pf 22pF pf pf µf (63) µf (63) µf (63) µf (63) pf nf (63) µf (63) nf (63) RFIN RFIN SDIO LOOUT SCLK CS LOOUT+ pf LOOUT DNC pf IFOUT2+ IFOUT2 LDO 5pF LDO2 pf pf µf (63) IFOUT2 µf (63) 5pF 33nH 33nH 5pF Figure. Basic Connections Diagram +5V Rev. Page 38 of 6

39 ADRF664 BASIC CONNECTIONS BY PIN DESCRIPTION Table 23. Basic Connections Pin No. Mnemonic Description Basic Connection 5 V Power Decouple to with a µf, a. µf, and a pf capacitor as close to the pin as possible. 7 VCC 5 V VCO supply 6 VCC2 5 V supply for SPI port 2, 4 VCC3, VCC 5 V biases for IF Channel 2 and IF Channel 27, 28, 29, 32, 33, 34 VCC4, VCC5, VCC6, VCC8, VCC9, VCC 5 V supplies for mixer LO amplifier 3 VCC7 5 V supply for mixer LO divider chain 46 VCC2 5 V supply for internal PLL Internal LDO Nodes 8, 9 DECL, DECL2 VCO LDO outputs,, 2 DECL3, DECL4, DECL5 External decoupling for VCO circuitry 5 LDO External decoupling for internal 2.5 V SPI LDO 3 LDO2 External decoupling for internal 3.3 V PLL/divider LDO 44 LDO3 External decoupling for internal 2.5 V PLL LDO 45 LDO4 External decoupling for internal 3.3 V PLL LDO Decouple to with a µf and a pf capacitor, as close to the pin as possible. Connect directly to the PCB ground through a low impedance connection. External loop filter ground 3, 6 Common ground for external loop filter 24, 37 IF stage, Channel 2 and Channel ground 48 External charge pump ground SPI 7 SDIO SPI port data input/output 8 SCLK SPI port clock 9 CS SPI port chip select RF, Mixer, IF Path 4, 5 EXTVCOIN+, External VCO or LO inputs DC block with pf capacitors. EXTVCOIN 3, 4 LOOUT+, LOOUT Differential LO outputs DC block with pf capacitors. 22, 23 IFOUT2+, IFOUT2 Channel 2 differential IF outputs Bias to 5 V supply with 33 nh inductors and dc block with 5 pf capacitors. 25 RFBCT2 Internal mixer bias control for Channel 2 RF input Decouple to with a pf and a nf capacitor, as close to the pin as possible. 26 RFIN2 Channel 2 single-ended RF input DC block with a 22 pf capacitor. 36 RFBCT Internal mixer bias control for Channel RF input Decouple to with a pf and a nf capacitor, as close to the pin as possible. 35 RFIN Channel single-ended RF input DC block with a 22 pf capacitor. 38, 39 IFOUT, IFOUT+ Channel differential IF outputs Bias to 5 V supply with 33 nh inductors and dc block with 5 pf capacitors. PLL/VCO 2 VCOVTUNE Control voltage for internal VCO Output from external loop filter. 43 REFIN External reference for internal PLL 47 CPOUT Charge pump output Input to external loop filter. Other 42 MUXOUT Output for various internal analog signals, including PLL lock detect and voltage proportional to absolute temperature (VPTAT) 2, 4 DNC Do not connect Can be read directly from the pin; the user must be careful of loading effects; not a low impedance output. Rev. Page 39 of 6

40 ADRF664 Data Sheet MIXER OPTIMIZATION RF INPUT BALUN INSERTION LOSS OPTIMIZATION At lower input frequencies, more capacitance is needed. This increase is achieved by programming higher codes into BAL_COUT. At high frequencies, less capacitance is required; therefore, lower BAL_COUT codes are appropriate. As shown in Figure 2 and Figure 3, this tuning range can be further optimized by adding capacitance across the RF input in conjunction with tuning BAL_COUT. This added capacitance can help to increase the low frequency range of the device significantly. RETURN LOSS (db) NO CAP 4pF 8 pf 2pF 5.6pF 6.8pF 3.3pF Figure 2. Return Loss; Optimum BAL_COUT vs. RF Frequency for Various Tuning Capacitor Values on RFINx Using a High-Side LO RETURN LOSS (db) NO CAP 4pF 8 pf 5.6pF 2pF 6.8pF 3.3pF Figure 3. Return Loss; Optimum BAL_COUT vs. RF Frequency for Various Tuning Capacitor Values on RFINx Using a Low-Side LO IIP3 OPTIMIZATION In applications in which performance is critical, the ADRF664 offers IIP3 optimization. The IF amplifier bias current can be reduced to trade performance vs. power consumption. This tradeoff saves on the overall power at the expense of degraded performance. Figure 4 to Figure 7 show the IIP3 sweeps for all combinations of IFA main bias and linearity bias. The IIP3 vs. main bias and linearity bias figures show both a surface and a contour plot in one Rev. Page 4 of 6 figure. The contour plot is located directly underneath the surface plot. The best approach for reading the figure is to localize the peaks on the surface plot, which indicate maximum IIP3, and to follow the same color pattern to the contour plot to determine the optimized IFA main bias and linearity bias settings. IIP3 (dbm) IIP3 (dbm) IIP3 (dbm) IFA_LINBIAS = IFA_LINBIAS = 8 IFA_LINBIAS = IFA_LINBIAS = 9 IFA_LINBIAS = 2 IFA_LINBIAS = IFA_LINBIAS = 3 IFA_LINBIAS = IFA_LINBIAS = 4 IFA_LINBIAS = 2 5 IFA_LINBIAS = 5 IFA_LINBIAS = 3 IFA_LINBIAS = 6 IFA_LINBIAS = 4 IFA_LINBIAS = IFA_MAINBIAS Figure 4. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias (IFA_LINBIAS) Level at IF Frequency = 5 MHz IFA_LINBIAS = IFA_LINBIAS = 8 IFA_LINBIAS = IFA_LINBIAS = 9 IFA_LINBIAS = 2 IFA_LINBIAS = IFA_LINBIAS = 3 IFA_LINBIAS = IFA_LINBIAS = 4 IFA_LINBIAS = 2 5 IFA_LINBIAS = 5 IFA_LINBIAS = 3 IFA_LINBIAS = 6 IFA_LINBIAS = 4 IFA_LINBIAS = IFA_MAINBIAS Figure 5. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias (IFA_LINBIAS) Level at IF Frequency = MHz IFA_LINBIAS = IFA_LINBIAS = 8 IFA_LINBIAS = IFA_LINBIAS = 9 IFA_LINBIAS = 2 IFA_LINBIAS = IFA_LINBIAS = 3 IFA_LINBIAS = IFA_LINBIAS = 4 IFA_LINBIAS = 2 5 IFA_LINBIAS = 5 IFA_LINBIAS = 3 IFA_LINBIAS = 6 IFA_LINBIAS = 4 IFA_LINBIAS = IFA_MAIN Figure 6. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias (IFA_LINBIAS) Level at IF Frequency = 5 MHz

41 ADRF664 IIP3 (dbm) IFA_LINBIAS = IFA_LINBIAS = 8 IFA_LINBIAS = IFA_LINBIAS = 9 IFA_LINBIAS = 2 IFA_LINBIAS = IFA_LINBIAS = 3 IFA_LINBIAS = IFA_LINBIAS = 4 IFA_LINBIAS = 2 5 IFA_LINBIAS = 5 IFA_LINBIAS = 3 IFA_LINBIAS = 6 IFA_LINBIAS = 4 IFA_LINBIAS = IFA_MAINBIAS Figure 7. IIP3 vs. Main Bias (IFA_MAINBIAS) and Linearity Bias (IFA_LINBIAS) Level at IF Frequency = 2 MHz VGS PROGRAMMING The ADRF664 allows programmability for internal gate-tosource voltages (VGS) for optimizing mixer performance over the desired frequency bands. The ADRF664 default VGS setting is. Both channels of the ADRF664 are programmed together using the same VGS setting. Power conversion gain, input IP3, input PdB, and SSB noise figure can be optimized, as shown in Figure 4, Figure 4, Figure 43, and Figure 44, respectively. LOW-PASS FILTER PROGRAMMING The ADRF664 allows programmability for the low-pass filter terminating the mixer output. This filter blocks sum term mixing products at the expense of some noise figure and gain and can significantly increase input IP3. The ADRF664 default LPF setting is. Both channels of the ADRF664 are programmed together using the same LPF settings. Power conversion gain, input PdB, input IP3, and SSB noise figure can be optimized as shown in Figure 42, Figure 45, Figure 46, and Figure 49, respectively. Rev. Page 4 of 6

42 ADRF664 Data Sheet Table 24. Recommended Optimum Settings for High Performance Mode (in Decimal) RF Frequency (MHz) LO Frequency (MHz) IFA_MAINBIAS IFA_LINBIAS BAL_COUT LPF VGS Table 25. Recommended Optimum Settings for High Efficiency Mode (in Decimal) RF Frequency (MHz) LO Frequency (MHz) IFA_MAINBIAS IFA_LINBIAS BAL_COUT LPF VGS Rev. Page 42 of 6

43 GSM MODE OF OPERATION The ADRF664 supports GSM phase noise specifications in typical GSM bands such as the 8 MHz, 9 MHz, 8 MHz, and 9 MHz. GSM phase noise performance in the 8 MHz and 9 MHz bands is met by simply tuning the integrated PLLVCO to the desired frequency. Integrated VCO cores (VCO_4 and VCO_5) support GSM phase noise performance in the 8 MHz and 9 MHz GSM bands. To ensure that GSM phase noise performance is achieved when using the ADRF664 in 8 MHz or 9 MHz bands, select the VCO_4 core by writing the VCO_SEL bits in the VCO_ CTRL register (Register x22, Bits[2:]) for a frequency range of.525 GHz to.547 GHz, and the VCO_5 core for a frequency range of.668 GHz to.78 GHz. The VCO_4 and VCO_5 cores operate at fundamental frequencies of 3.5 GHz to 3.94 GHz and GHz to 3.46 GHz, respectively. To generate the desired LO frequency in the 8 MHz and 9 MHz bands, enable divide by 2 by writing to LO_DIV (Register x22, Bits[5:3]). For the GSM mode of operation, the recommended loop filter components and dynamic loop settings are shown in Table 9 at the PFD rate of.536 MHz. See Figure 8 for the GSM mode phase noise performance of 45 dbc/hz at 8 khz offset at the carrier frequency of.535 GHz. ADRF664 When using the VCO_4 or VCO_5 cores, it is required to set VTUNE_DAC_SLOPE (Register x49, Bits[3:9]) = 9d, VTUNE_DAC_OFFSET (Register x49, Bits[8:]) = 7d, VCO_LDO_R2 (Register x22, Bits[:8]) = 2d, and VCO_ LDO_R4 (Register x22, Bits[5:2]) = d. In transitioning from a GSM VCO (VCO_4 and VCO_5) to an octave VCO, the LDO settings must be changed before changing the VCO selection. PHASE NOISE (db) : 2: khz khz dBc/Hz 9.2dBc/Hz 3: 5kHz.8226dBc/Hz 4: khz 2.286dBc/Hz 5 5: 6: 5kHz 8kHz 4.46dBc/Hz dBc/Hz 6 7 7: 8: 9: MHz MHz 4MHz dBc/Hz dBc/Hz dBc/Hz 8 : MHz dBc/Hz START: 5Hz 9 STOP: 2MHz CENTER:.25MHz SPAN: MHz 2 INTG NOISE: dBc/9.7MHz RMS NOISE: mrad mdeg 3 RMS JITTER: 65.68fs RESIDUAL FM: Hz k k k M M M FREQUENCY (Hz) Figure 8. GSM Phase Noise Performance at.535 GHz Rev. Page 43 of 6

44 ADRF664 Data Sheet REGISTER SUMMARY Table 26. Register Summary Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit Reset RW x SOFT_RESET [5:8] SOFT_RESET[5:8] x R [7:] SOFT_RESET[7:] x ENABLES [5:8] LO_LDO_EN LO2_ENP BALUN_EN LO_ENP DIV2P5_EN PWRUPRX LO_PATH_EN x RW [7:] LO_DRV_EN VCOBUF_LDO_ EN REF_BUF_EN VCO_EN DIV_EN CP_EN VCO_LDO_EN LDO_3P3_EN x2 INT_DIV [5:8] DIV_MODE INT_DIV[4:8] x58 RW [7:] INT_DIV[7:] x3 FRAC_DIV [5:8] FRAC_DIV[5:8] x25 RW [7:] FRAC_DIV[7:] x4 MOD_DIV [5:8] MOD_DIV[5:8] x6 RW [7:] MOD_DIV[7:] x IF_BIAS [5:8] IFA_LIN_HIEFFP IFA_MAIN_ HIEFFP IFA_LINSLOPE IFA_MAINSLOPE IFA_LINBIAS[3:2] x2b5 RW [7:] IFA_LINBIAS[:] IFA_LINBIAS_EN IFA_MAINBIAS IFA_MAINBIAS_EN x2 CP_CTRL [5:8] UNUSED CSCALE x26 RW [7:] BLEED_ POLARITY BLEED x2 PFD_CTRL [5:8] UNUSED REF_MUX_SEL PFD_POLARITY REFSEL[:8] x3 RW [7:] REFSEL[7:] x22 VCO_CTRL [5:8] VCO_LDO_R4 VCO_LDO_R2 xa RW [7:] LO_DRV_LVL LO_DIV VCO_SEL x3 BALUN_CTRL [5:8] UNUSED VGS LPF x RW [7:] BAL_COUT RESERVED x4 PFD_CTRL2 [5:8] UNUSED ABLDLY[3] x RW [7:] ABLDLY[2:] CPCTRL CLKEDGE x42 DITH_CTRL [5:8] UNUSED[:4] xe RW [7:] UNUSED[3:] DITH_EN DITH_MAG DITH_VAL_H x43 DITH_CTRL2 [5:8] DITH_VAL_L[5:8] x RW [7:] DITH_VAL_L[7:] x44 SYNTH_FCNTN_ CTRL [5:8] UNUSED[9:2] x RW [7:] UNUSED[:] DIV_SDM_ DIS VCOCNT_CG_ DIS BANDCAL_CG_ DIS SDM_CG_ DIS SDM_DIVD_ CLR BANDCAL_DIVD_ CLR x45 VCO_CTRL2 [5:8] UNUSED x2 RW [7:] VCO_BAND_SRC BAND x46 VCO_CTRL3 [5:8] UNUSED x RW [7:] VCO_CNTR_ DONE VCO_BAND x47 VCO_CNTR_ CTRL [5:8] UNUSED[:4] x RW [7:] UNUSED[3:] VCO_CNTR_REFCNT VCO_CNTR_ CLR VCO_CNTR_EN x48 VCO_CNTR_RB [5:8] VCO_CNTR_RB[5:8] x R [7:] VCO_CNTR_RB[7:] x49 VTUNE_DAC_ CTRL [5:8] UNUSED VTUNE_DAC_SLOPE VTUNE_DAC_ OFFSET[8] [7:] VTUNE_DAC_OFFSET[7:] x4a VCO_BUF_LDO [5:8] UNUSED x RW [7:] VCOBUF_LDO_R4 VCOBUF_LDO_R2 x RW Rev. Page 44 of 6

45 ADRF664 REGISTER DETAILS Address: x, Reset: x, Name: SOFT_RESET Table 27. Bit Descriptions for SOFT_RESET Bits Bit Name Settings Description Reset Access [5:] SOFT_RESET Soft reset bit. x R Any write to this register asserts a soft reset command. x R Address: x, Reset: x, Name: ENABLES Table 28. Bit Descriptions for ENABLES Bits Bit Name Settings Description Reset Access 5 LO_LDO_EN Power up LO LDO. x RW 4 LO2_ENP LO 2 enable. x RW 3 BALUN_EN Input balun enable. x RW 2 LO_ENP LO enable. x RW DIV2P5_EN Enable dividers 2.5 V LDO. x RW [:9] PWRUPRX Power up Rx. x RW x Power down both mixer channels. x Power up mixer Channel. x2 Power up mixer Channel 2. x3 Power up both mixer channels. 8 LO_PATH_EN External LO path enable. x RW 7 LO_DRV_EN LO driver enable. x RW Rev. Page 45 of 6

46 ADRF664 Data Sheet Bits Bit Name Settings Description Reset Access 6 VCOBUF_LDO_EN VCO buffer LDO enable. x RW 5 REF_BUF_EN Reference buffer enable. x RW 4 VCO_EN Power up VCOs. x RW 3 DIV_EN Power up dividers. x RW 2 CP_EN Power up charge pump. x RW VCO_LDO_EN Power up VCO LDO. x RW LDO_3P3_EN Power up 3.3 V LDO. x RW Address: x2, Reset: x58, Name: INT_DIV Table 29. Bit Descriptions for INT_DIV Bits Bit Name Settings Description Reset Access 5 DIV_MODE Set fractional/integer mode. x RW Fractional. Integer. [4:] INT_DIV Set divider INT value. x58 RW Address: x3, Reset: x25, Name: FRAC_DIV Table 3. Bit Descriptions for FRAC_DIV Bits Bit Name Settings Description Reset Access [5:] FRAC_DIV Set divider FRAC value. x25 RW Address: x4, Reset: x6, Name: MOD_DIV Table 3. Bit Descriptions for MOD_DIV Bits Bit Name Settings Description Reset Access [5:] MOD_DIV Set divider MOD value. x6 RW Rev. Page 46 of 6

47 ADRF664 Address: x, Reset: x2b5, Name: IF_BIAS Table 32. Bit Descriptions for IF_BIAS Bits Bit Name Settings Description Reset Access 5 IFA_LIN_HIEFFP Linearity RDAC. x RW High performance mode. High efficiency mode. 4 IFA_MAIN_HIEFFP Main RDAC. x RW High performance mode. High efficiency mode. [3:2] IFA_LINSLOPE Linearity slope adjust for IF amps (IPMix). x RW [:] IFA_MAINSLOPE Main slope adjust for IF amps (IPMix). x RW [9:6] IFA_LINBIAS Linearity bias adjust for IF amps (IPMix). xa RW 5 IFA_LINBIAS_EN Enable internal linearity bias adjust for IF amps (IPMix). x RW [4:] IFA_MAINBIAS Main bias adjust for IF amps (IPMix). xa RW IFA_MAINBIAS_EN Enable internal main bias adjust for IF amps (IPMix). x RW Address: x2, Reset: x26, Name: CP_CTRL Table 33. Bit Descriptions for CP_CTRL Bits Bit Name Settings Description Reset Access [5:4] UNUSED Unused. x RW [3:8] CSCALE Charge pump current adjust. x RW 7 BLEED_POLARITY Charge pump bleed current polarity. x RW [6:] BLEED Charge pump bleed. x26 RW Rev. Page 47 of 6

48 ADRF664 Data Sheet Address: x2, Reset: x3, Name: PFD_CTRL Table 34. Bit Descriptions for PFD_CTRL Bits Bit Name Settings Description Reset Access 5 UNUSED Unused. x RW [4:3] REF_MUX_SEL Reference output divide ratio/vptat/scan/lock_det. x RW LOCK_DET. VPTAT. REFCLK. REFCLK/2. REFCLK 2. REFCLK/8. REFCLK/4. SCAN. 2 PFD_POLARITY PFD polarity. x RW Positive. Negative. [:] REFSEL Reference input divide ratio. x3 RW Rev. Page 48 of 6

49 ADRF664 Address: x22, Reset: xa, Name: VCO_CTRL Table 35. Bit Descriptions for VCO_CTRL Bits Bit Name Settings Description Reset Access [5:2] VCO_LDO_R4 VCO LDO R4 resistor control setting. x RW [:8] VCO_LDO_R2 VCO LDO R2 resistor control setting. x RW [7:6] LO_DRV_LVL External LO amplitude. x RW.8 dbm/5 ma. 4.6 dbm/28 ma. 7.5 dbm/4 ma. 9.2 dbm/49 ma. [5:3] LO_DIV LO divider. x RW Divide by. Divide by 2. Divide by 4. Divide by 8. [2:] VCO_SEL Select VCO core/external LO. x2 RW VCO_ 4.6 GHz to 5.7 GHz. VCO_ 4.2 GHz to 4.6 GHz. VCO_2 3.5 GHz to 4.2 GHz. VCO_ GHz to 3.5 GHz. VCO_4 3.5 GHz to 3.94 GHz VCO_ GHz to 3.46 GHz External LO/VCO. None Rev. Page 49 of 6

50 ADRF664 Data Sheet Address: x3, Reset: x, Name: BALUN_CTRL Table 36. Bit Descriptions for BALUN_CTRL Bits Bit Name Settings Description Reset Access [5:4] UNUSED Unused. x RW [3:] VGS Mixer VGS bias. x RW [:8] LPF Mixer output IF low-pass filter. x RW [7:4] BAL_COUT Set balun COUT (both channels). x RW [3:] RESERVED Reserved, set to x. x RW Address: x4, Reset: x, Name: PFD_CTRL2 Table 37. Bit Descriptions for PFD_CTRL2 Bits Bit Name Settings Description Reset Access [5:9] UNUSED Unused. x RW [8:5] ABLDLY Set antibacklash delay. x RW ns..5 ns..75 ns..9 ns. Rev. Page 5 of 6

51 ADRF664 Bits Bit Name Settings Description Reset Access [4:2] CPCTRL Set charge pump control. x4 RW Both on. Pump down. Pump up. Tristate. PFD. Unused. Unused. Unused. [:] CLKEDGE Set PFD edge sensitivity. x RW Divider and reference down edge. Divider down edge, reference up edge. Divider up edge, reference down edge. Divider and reference up edge. Address: x42, Reset: xe, Name: DITH_CTRL Table 38. Bit Descriptions for DITH_CTRL Bits Bit Name Settings Description Reset Access [5:4] UNUSED Unused register bits. x RW 3 DITH_EN Set dither enable. x RW Disable. Enable. [2:] DITH_MAG Dither magnitude. x3 RW DITH_VAL_H Highest bit of 7-bit dither value. x RW Address: x43, Reset: x, Name: DITH_CTRL2 Table 39. Bit Descriptions for DITH_CTRL2 Bits Bit Name Settings Description Reset Access [5:] DITH_VAL_L Lowest 6 bits of 7-bit dither value. x RW Rev. Page 5 of 6

52 ADRF664 Data Sheet Address: x44, Reset: x, Name: SYNTH_FCNTN_CTRL Table 4. Bit Descriptions for SYNTH_FCNTN_CTRL Bits Bit Name Settings Description Reset Access [5:6] UNUSED Unused. x RW 5 DIV_SDM_DIS Disable sigma-delta modulator (SDM) divider. x RW 4 VCOCNT_CG_DIS Disable built in self test (BIST) clock. x RW 3 BANDCAL_CG_DIS Disable VCO band calibration (BANDCAL) clock. x RW 2 SDM_CG_DIS Disable SDM clock. x RW SDM_DIVD_CLR Clear SDM divider. x RW BANDCAL_DIVD_CLR Clear BANDCAL divider. x RW Address: x45, Reset: x2, Name: VCO_CTRL2 Table 4. Bit Descriptions for VCO_CTRL2 Bits Bit Name Settings Description Reset Access [5:8] UNUSED Unused. x RW 7 VCO_BAND_SRC Set VCO band source. x RW Automatic Manual [6:] BAND Set VCO band. x2 RW Rev. Page 52 of 6

53 ADRF664 Address: x46, Reset: x, Name: VCO_CTRL3 Table 42. Bit Descriptions for VCO_CTRL3 Bits Bit Name Settings Description Reset Access [5:8] UNUSED Unused. x RW 7 VCO_CNTR_DONE Read back BIST counter status. x R [6:] VCO_BAND Read back output of band capacitor mux. x R Address: x47, Reset: x, Name: VCO_CNTR_CTRL Table 43. Bit Descriptions for VCO_CNTR_CTRL Bits Bit Name Settings Description Reset Access [5:4] UNUSED Unused. x RW [3:2] VCO_CNTR_REFCNT BIST counter integration interval. x RW VCO_CNTR_CLR Clear BIST counter. x RW VCO_CNTR_EN Enable BIST counter. x RW Address: x48, Reset: x, Name: VCO_CNTR_RB Table 44. Bit Descriptions for VCO_CNTR_RB Bits Bit Name Settings Description Reset Access [5:] VCO_CNTR_RB Read back output of BIST counter. x R Rev. Page 53 of 6

54 ADRF664 Data Sheet Address: x49, Reset: x, Name: VTUNE_DAC_CTRL Table 45. Bit Descriptions for VTUNE_DAC_CTRL Bits Bit Name Settings Description Reset Access [5:4] UNUSED Unused. x RW [3:9] VTUNE_DAC_SLOPE Set VTUNE proportional to absolute temperature (PTAT) DAC. x RW [8:] VTUNE_DAC_OFFSET Set VTUNE zero to absolute temperature (ZTAT) DAC. x RW Address: x4a, Reset: x, Name: VCO_BUF_LDO Table 46. Bit Descriptions for VCO_BUF_LDO Bits Bit Name Settings Description Reset Access [5:8] UNUSED Unused. x RW [7:4] VCOBUF_LDO_R4 VCOBUF LDO R4 control. x RW [3:] VCOBUF_LDO_R2 VCOBUF LDO R2 control. x RW Rev. Page 54 of 6

55 EVALUATION BOARD An evaluation board is available for the ADRF664. The standard evaluation board schematic is presented in Figure 9. The USB interface circuitry schematic is presented in Figure 2 and/or Figure 2. The evaluation board layout is shown in Figure 22 ADRF664 and Figure 23. The evaluation board is fabricated using Rogers 33 material. Table 47 details the configuration for the mixer characterization. The evaluation board software is available on Rev. Page 55 of 6

56 ADRF664 Data Sheet C4 C5 PF.UF VCC_IF IFP L JOHNSON CPOUT R38 IFP BLK BLK BLU 33NH C36 T4 VTUNE C29 C33 R7 BLU.UF 5PF R98 5PF DNI IF OUTPUT R4 C IFN BLK BLK VCOTUNE R R8 R97 L2 JOHNSON PF TC4-W+ R39 IFN 2K.8K DNI 33NH DNI C59 C23 C22 C2 C32 R5 5PF PF 56PF.33UF 5PF C8 5PF R7 MUXOUT 9 VCC_SYNTH (VCC5PLL) C7 PF C2.UF VCC_LO (VCCLO4) VCC_LO (VCCLO3) VCC_LO (VCCLO2) VCC_SYNTH C C52 PF.UF R96 K DNI PLL REF IN (VCC5DIV) VCC_LO (VCC2LO2) VCC_LO (VCC2LO3) VCC_LO (VCC2LO4) MUX_OUT JOHNSON C54 PLL_REF_IN JOHNSON PLL_REF_IN PF R R36 2K TP5 BLU VCC_SYNTH (VCC5VCO) CR3 SML-2MTT86 A C46 C53 PF.UF R95 K DNI VCC_IF C LDO2P5PLL LDO3P3PLL VCC_SYNTH CPOUT C9 PF C3.UF RF_IN JOHNSON C44 PF PAD C4 PF EP CPOUT VCC2 LDO4 LDO3 REFIN MUXOUT VCC DNC IFOUT+ IFOUT- EXT VCO OUTPUT VCC_SYNTH TC--43A+ AT224- EXT_LOIN JOHNSON (VCC5SPI) C47 C55 PF.UF C25 T C82 U PF PF C27 C2 PF C6.UF THESE SIX PF CAPS SHOULD BE LOCATED AS CLOSE AS POSSIBLE TO C42 22PF VCC_LO VCC_LO VCC_LO VCC_SYNTH LDO3P3DIV VCC_LO VCC_LO VCC_LO VCC_SYNTH PF C2 UF C PF Figure 9. Evaluation Board, Main Circuitry Rev. Page 56 of 6 ADRF664ACPZ PINS 27,28,29,32,33, RFBCT RFIN VCC VCC9 VCC8 VCC7 LDO2 VCC6 VCC5 VCC4 RFIN2 RFBCT2 VCOVTUNE EXTVCOIN+ EXTVCOIN- VCC DECL DECL2 DECL3 DECL4 DECL5 SEC PRI 2 C43 22PF C26 UF C PF VCC_IF (VCCIF2) C48 C56 PF.UF IFOUT2- IFPOUT2+ DNC VCC3 CS_N SCLK SDIO VCC2 LDO LOOUT- LOOUT C24 TBD85 DNI C5 UF C3 C89 C4 PF UF PF C9 C2.UF PF C4 C45 PF PF RF_IN2 JOHNSON TP4 BLU LDO2P5SPI VCC_SYNTH DATA CLK LE VCC_IF TC--43A+ AT224- LO_OUT C28 T2 R35 R94 K DNI R93 K DNI PF SEC PRI JOHNSON VCC_IF C3 C49 C9 PF.UF (VCCIF) IF2P PF VCC_IF JOHNSON IF2P L3 R37 C6 C7.UF PF IF OUTPUT 2 33NH C38 T5 C34 C3 R8 5PF.UF 5PF DNI C39 IF2N TC4-W+ R4 IF2N C6 DNI C5 C9 DNI 5PF PF.UF R6 JOHNSON L4 5PF 33NH C35 5PF LDO3P3DIV VCC_LO VCC_IF VCC_SYNTH RED RED RED VCC_SYNTH VCC_LO VCC_IF LDO2P5SPI LDO2P5PLL LDO3P3PLL C P C8 UF N UF P C92 UF P N N C58 UF C57 PF C5 C C7 C8 C4 C5 PF UF UF UF PF PF ALL PF DECOUPLING CAPS SHOULD BE AS CLOSE AS POSSIBLE TO THE PINS ON THE CHIP

57 ADRF MEGHZ PF.UF SNS PF.UF D 24LC64-I-SN.UF JPR42 JPR42 JPR42 U3 C77 R32 ADP3334ACPZ C8 UF 2K PF IN OUT D IN OUT SD FB PAD CR PAD 78.7K BLK DNI UF TP2 BLK DNI D SML-2MTT86 SML-2MTT86 Y 3 5V_USB R3 K P2 3V3_USB 3V3_USB U4 C74.UF G G2 G3 G4 C62 C69 3V3_USB 42 RDY_SLRD RESET_N 4 RDY_SLWR 4 AVCC PA7_FLAGD_SLCS_N 39 XTALOUT PA6_PKTEND 38 XTALIN PA5_FIFOADR 37 PA4_FIFOADR 36 AVCC PA3_WU2 CY7C683A-56LTXC 35 DPLUS PA2_SLOE 34 DMINUS PA_INT_N 33 PA_INT_N 3V3_USB 32 3V3_USB VCC VCC 2 3 CTL2_FLAGC 3 3 IFCLK CTL_FLAGB 4 29 R29 RESERVED CTL_FLAGA 2K CR2 SNS 2 3V3_USB C72 3V3_USB C73 DECOUPLING FOR U R27 R28 2K 2K C6 C63 C64 C65 C66 C67 C68.UF.UF.UF.UF.UF.UF.UF U2 A VCC A A2 R3 K C75 JP JP2 JP3 5V_USB 3V3_USB 3V3_USB R33 R2 4K CLK DATA LE TP C C A C7 CASE 22PF 4 2 C7 D 22PF D D C A 3V3_USB 3V3_USB PAD D PINS D D D D D SCL SDA WC_N D D D C78 C79 R25 C76 R24 R22 TBD42 TBD42 K TBD42 K K 33PF 33PF DNI 33PF DNI DNI DNI DNI DNI D D D D D D D D D D VCC PB7_FD7 PB6_FD6 PB5_FD5 PB4_FD4 PB3_FD3 PB2_FD2 PB_FD PB_FD VCC SDA SCL PAD VCC CLKOUT PD7_FD5 PD6_FD4 PD5_FD3 PD4_FD2 PD3_FD PD2_FD PD_FD9 PD_FD8 WAKEUP VCC Figure 2. Evaluation Board, Legacy USB Interface Rev. Page 57 of 6

58 ADRF664 Data Sheet R99 8 U TBD63 VCC DNI DNI 2 A A 3 5 A2 SDA 6 SCL 7 WP R VSS K 4 DNI D D 24LC32A-I/MS E46 JEDEC_TYPE=MSOP8 TP6 DATA JP6 2 DATA_SDP JPR42 DNI R34 DNI R6 DNI TP7 JP4 CLK CLK_SDP R9 JPR42 DNI 2 D D FX8-2S-SV(2) P7 DNI TP8 LE JP5 2 LE_SDP JPR42 DNI VCC_SYNTH R DNI FX8-2S-SV(2) D P7 K DNI Figure 2. Evaluation Board, Analog Devices, Inc. SDP-S USB Interface Rev. Page 58 of 6

59 ADRF664 Table 47. Evaluation Board Bill of Materials Components Description Default Conditions C, C2, C8, C, C2, C3, C4, C5, C8, C9, C2, C23, C26, C27 Power supply decoupling. Nominal supply decoupling consists of a. μf capacitor to ground in parallel with a pf capacitor to ground positioned as close to the device as possible. C6, C7, C24, C25 RF input interface. The input channels are ac-coupled through C6 and C24. C7 and C25 provide bypassing for the center tap of the RF input baluns. C3, C4, C5, C28, C29, C3, L, L2, L3, L4, R2, R2, R22, R23, T, T2 IF output interface. The open-collector IF output interfaces are biased through pull-up choke Inductors L, L2, L3, and L4. T and T2 are 4: impedance transformers used to provide single-ended IF output interfaces, with C5 and C3 providing center tap bypassing. Remove R2 and R22 for balanced output operation. C, C2, C26, C27 =. μf (size 42) C8, C, C2, C3, C4, C5, C8, C9 C2, C23 = pf (size 42) C6, C24 = 22 pf (size 42) C7, C25 = 22 pf (size 42) C3, C4, C5, C28, C29, C3 = 2 pf (size 42) L, L2, L3, L4 = 47 nh (size 63) R2, R23 = open R2, R22 = Ω (size 42) T, T2 = TC4-W+ (Mini-Circuits ) C7 LO interface. C7 provides ac coupling for the local oscillator input. C7 = 22 pf (size 42) R, R2 Bias control. Rand R2 set the bias point for the internal IF amplifier. R, R2 = 9 Ω (size 42) Figure 22. Evaluation Board, Top Layer Rev. Page 59 of 6

60 ADRF664 Data Sheet Figure 23. Evaluation Board, Bottom Layer Rev. Page 6 of 6