26.5 GHz, Integer N/Fractional-N, PLL Synthesizer ADF41513

Transcription

1 265 GHz, Integer N/Fractional-N, PLL Synthesizer ADF453 FEATURES GENERAL DESCRIPTION GHz to 265 GHz bandwidth The ADF453 is an ultralow noise frequency synthesizer that Ultralow noise PLL can be used to implement local oscillators (LOs) as high as Integer N: 234 dbc/hz, fractional-n: 23 dbc/hz 265 GHz in the upconversion and downconversion sections of High maximum PFD frequency wireless receivers and transmitters Integer N: 25 MHz, fractional-n: 25 MHz The ADF453 is designed on a high performance silicon 25-bit fixed/49-bit variable fractional modulus mode geranium (SiGe), bipolar complementary metal-oxide Single-ended reference input semiconductor (BiCMOS) process, achieving a normalized 33 V power supply, 33 V charge pump phase noise floor of 234 dbc/hz The phase frequency Integrated 8 V logic capability detector (PFD) operates up to 25 MHz (integer N mode)/ Phase resync 25 MHz (fractional-n mode) for improved phase noise and Programmable charge pump currents: 6 range spur performance The variable modulus, -Δ modulator allows Digital lock detect extremely fine resolution when using a 49-bit divide value The 3-wire serial interface with register readback option ADF453 can be used as either an integer N phase-locked loop Hardware and software power-down mode (PLL) or fractional-n PLL with either a fixed modulus for APPLICATIONS subhertz frequency resolution or variable modulus for subhertz Test equipment and instrumentation exact frequency resolution Wireless infrastructure A complete PLL is implemented when the synthesizer is used Microwave point to point and multipoint radios with an external loop filter and voltage controlled oscillator VSAT radios (VCO) The 265 GHz bandwidth means a frequency doubler or divider stage can be eliminated, simplifying system architecture and reducing cost The ADF453 is packaged in a compact, 24-lead, 4 mm 4 mm LFCSP FUNCTIONAL BLOCK DIAGRAM V P AV DD AV DD AV DD2 AV DD3 AV DD4 AV DD5 R SET ADF453 REF IN 2 DOUBLER MUXOUT DLD HIGH-Z OUTPUT MUX N DGND AV DD DV DD R DIV 5-BIT R COUNTER LOCK DETECT 2 DIVIDER + PHASE FREQUENCY DETECTOR N COUNTER REFERENCE CHARGE PUMP + CSR CP DC DC2 RF IN A RF IN B CE TX DATA SD OUT 25-BIT FIXED/49-BIT VARIABLE FRACTIONAL INTERPOLATOR CLK DATA LE 32-BIT DATA REGISTER FRACTION VALUE MODULUS 2 25 VALUE INTEGER VALUE 8V REGULATOR C REG C REG2 GND Figure 685- Rev PrL Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way, PO Box 96, Norwood, MA , USA Tel: Analog Devices, Inc All rights reserved Technical Support wwwanalogcom

2 ADF453 TABLE OF CONTENTS Features Applications General Description Functional Block Diagram Specifications 3 Timing Characteristics 4 Absolute Maximum Ratings 6 ESD Caution 6 Pin Configuration and Function Description 7 Typical Performance Characteristics 9 Theory of Operation Reference Input RF Input Stage N Divider and R Counter R Counter 2 PFD and Charge Pump 2 MUXOUT 2 Lock Detector 2 Readback 3 Input Shift Registers 3 Program Modes 3 Register Maps 4 Register (R) Map 7 Register (R) Map 8 Register 2 (R2) Map 9 Register 3 (R3) Map 2 Register 4 (R4) Map 2 Register 5 (R5) Map 22 Register 6 (R6) Map 24 Register 7 (R7) Map 26 Register 8 (R8) Map 27 Register 9 (R9) Map 27 Register (R) Map 28 Register (R) Map 28 Register 2 (R2) Map 29 Register 3 (R3) Map 3 Applications information 3 Initialization Sequence 3 RF Synthesizer: A Worked Example of 25-Bit Fixed Modulus Mode 3 RF Synthesizer: A Worked Example of Variable Modulus Mode 3 Modulus 3 Reference Doubler and Reference Divider 3 Spur Mechanisms 32 Phase Resync 32 Outline Dimensions 33 Rev PrL Page 2 of 33

3 ADF453 SPECIFICATIONS AVDDX = VP = 33 V ± 5%, GND = V, R SET = 27 kω, dbm referred to 5 Ω, TA = TMAX to TMIN, unless otherwise noted Table Parameter Min Typ Max Unit Test Conditions/Comments RADIO FREQUENCY (RF) CHARACTERISTICS RF Input Frequency (frfin) Range 265 GHz For lower frequencies, ensure slew rate > 32 V/µs RF Input Sensitivity Range 5 +5 dbm Measured single-ended to RFINA via a pf series capacitor, pf capacitor to GND on RFINB Maximum Allowable Prescaler 3325 MHz Output Frequency INPUT REFERENCE FREQUENCY (REFIN) CHARACTERISTICS REFIN Input Frequency 8 MHz REFIN Input Voltage Range 8 V REFIN Input Sensitivity Range 8 dbm Biased at V, 2 use square wave at low power and/or frequency to ensure slew rate is > 32 V/µs REFIN Input Capacitance pf REFIN Input Current ± µa Doubler Input Frequency 225 MHz Maximum reference frequency when the doubler is enabled MAXIMUM PFD FREQUENCY Integer N Mode 25 MHz 25-Bit Fixed Modulus Mode 25 MHz 49-Bit Variable Modulus Mode TBD MHz N DIVIDER RANGE 6-Bit N Divider Range /5 prescaler /9 prescaler CHARGE PUMP (CP) CP Current (ICP) Sink and Source Programmable High Value 48 ma With RSET = 27 kω Low Value 3 ma Absolute Accuracy 5 % With RSET = 27 kω RSET Range 8 27 kω 5% accuracy ICP Three-State Leakage 2 na TA = 25 C Sink and Source Current Matching 5 % V CP voltage (VCP) VP V ICP vs VCP 5 % V VCP VP V ICP vs Temperature 5 % VCP = VP/2 LOGIC INPUTS Input High Voltage (VIH) 4 V The serial port interface (SPI) block can accept both 8 V or 33 V logic inputs Input Low Voltage (VIL) 6 V Input Current (IINH, IINL) ± µa Input Capacitance (CIN) pf LOGIC OUTPUTS Output High Voltage (VOH) 4 V MUXOUT voltage = 8 V 26 V MUXOUT voltage = 33 V Output Low Voltage (VOL) 4 V Output High Current, Output Low Current (IOH, IOL) 5 µa Rev PrL Page 3 of 33

4 ADF453 Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLIES AVDD, AVDD2, AVDD3, AVDD4, AVDD5, VP V IDD 3 3 ma Current drawn by AVDD IDD ma Current drawn by AVDD2 IDD3 5 2 ma Current drawn by AVDD3 IDD ma Current drawn by AVDD4 IDD5 7 7 ma Current drawn by AVDD5 IP 45 ma Current drawn by VP Power-Down Mode 4 µa TA = 25 C, CE = low, total of all rails NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 8 in Integer N Mode 234 dbc/hz PLL loop bandwidth (BW) = MHz (integer N mode) Normalized Phase Noise Floor 23 dbc/hz PLL loop BW = MHz (fractional-n mode) (PNSYNTH) 5 in Fractional-N Mode Normalized f Noise (PN_f) 9 27 dbc/hz khz offset, normalized to GHz SPURIOUS SIGNALS Reference Spurious 9 dbc At reference = MHz PFD Spurious 87 dbc At PFD = 5 MHz In-Band Integer Boundary Spurious 45 dbc khz offset, PLL loop BW = 25 khz This is the maximum operating frequency of the N counter Ensure that the RF input divides down to a frequency that is less than this value by choosing a prescaler value that is less than the maximum operating frequency of the N counter 2 AC coupling ensures V bias 3 TA = 25 C, AVDD = 33 V, prescaler (P) = 8/9, frfin = 2 GHz, REFIN = MHz, PFD frequency input (fpfd) = MHz 4 TA = 25 C, AVDD2 = 33 V, P = 8/9, frfin = 2 GHz, REFIN = MHz, fpfd = MHz 5 TA = 25 C, AVDD3 = 33 V, P = 8/9, frfin = 2 GHz, REFIN = MHz, fpfd = MHz 6 TA = 25 C, AVDD4 = 33 V, P = 8/9, frfin = 2 GHz, REFIN = MHz, fpfd = MHz 7 TA = 25 C, AVDD5 = 33 V, P = 8/9, frfin = 2 GHz, REFIN = MHz, fpfd = MHz 8 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 2 log N (where N is the N divider value) and log fpfd PNSYNTH = total phase noise measured at the VCO output (PNTOT) log fpfd 2 log N 9 The PLL phase noise is composed of /f (flicker) noise plus the normalized PLL noise floor The formula for calculating the /f noise contribution at an RF frequency, frf, and at a frequency offset, f, is given by phase noise (PN) = P_f + log( khz/f) + 2 log(frf/ GHz) Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL TIMING CHARACTERISTICS AVDDX = VP = 33 V ± 5%, GND = V, R SET = 27 kω, dbm referred to 5 Ω, TA = TMAX to TMIN, unless otherwise noted Table 2 Read and Write Timing Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments t 2 ns min LE setup time t2 ns min DATA to CLK setup time t3 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 ns min CLK to LE setup time t7 2 ns min LE pulse width t8 ns min LE setup time to MUXOUT when MUXOUT is configured as SPI output t9 5 ns min CLK setup time to MUXOUT when MUXOUT is configured as SPI output Rev PrL Page 4 of 33

5 ADF453 t 4 t 5 CLK t 2 t 3 DATA DB3 (MSB) DB3 DB2 ( BIT C3) DB ( BIT C2) DB (LSB) ( BIT C) t 7 LE t t 6 MUXOUT DB3 (MSB) DB3 DB DB t 8 t 9 Figure 2 Read and Write Timing Rev PrL Page 5 of 33

6 ADF453 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted Table 3 Parameter AVDDX to GND VP to GND VP to AVDDX Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND RFINA, RFINB to GND RFINA to RFINB REFIN to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature 5 C Reflow Soldering Peak Temperature 26 C Rating 3 V to +36 V 3 V to +36 V 3 V to +3 V 3 V to VDD + 3 V 3 V to VP + 3 V 3 V to +36 V ±4 V 3 V to +2 V 4 C to +85 C 65 C to +25 C Time at Peak Temperature 4 sec Transistor Count CMOS 25,726 Bipolar 625 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied Operation beyond the maximum operating conditions for extended periods may affect product reliability This device is a high performance RF IC with an electrostatic discharge (ESD) rating of <2 kv, and the device is ESD sensitive Take proper precautions for handling and assembly ESD CAUTION Approximately 3 dbm into a 5 Ω input Rev PrL Page 6 of 33

7 DLD DC ADF453 PIN CONFIGURATION AND FUNCTION DESCRIPTION 24 CP 23 R SET DC2 22 V P C REG2 GND AV DD 2 AV DD 3 RF IN B 4 RF IN A 5 AV DD2 6 ADF453 TOP VIEW (Not to Scale) 8 7 C REG MUXOUT 6 LE 5 DATA 4 CLK 3 CE AV DD3 AV DD4 AV DD5 REF IN TX DATA NOTES EXPOSED PAD THE EXPOSED PAD MUST BE CONNECTED TO GND Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Function GND Ground Pin 2, 3 AVDD PFD and Up and Down Digital Driver Power Supply These pins can be tied together Place three parallel capacitors as close as possible to the AVDD pins: µf, nf, and pf 4 RFINB Complementary Input to the RF Prescaler In single-ended mode, decouple this pin to the ground plane with a small bypass capacitor, typically pf 5 RFINA Input to the RF Prescaler AC-couple this signal to the external VCO 6 AVDD2 RF Buffer and Prescaler Power Supply Place three parallel capacitors as close as possible to the AVDD2 pin: µf, nf, and pf 7 AVDD3 N Divider Power Supply Place three parallel capacitors as close as possible to the AVDD3 pin: µf, nf, and pf 8 AVDD4 R Divider and Lock Detector Power Supply Place three parallel capacitors as close as possible to the AVDD4 pin: µf, µf, and nf This pin powers the internal low dropout (LDO) regulator for the reference divider 9 AVDD5 Σ-Δ Modulator and SPI Power Supply Place three parallel capacitors as close as possible to the AVDD5 pin: µf, µf, and nf This pin powers the internal LDO regulator for the Σ-Δ modulator REFIN Reference Input The reference can accept either a single-ended CMOS (dc-coupled) or single-ended sine wave (accoupled) The single-ended input has a nominal threshold of V and a dc equivalent input resistance of 2 kω DLD Digital Lock Detect Pin A logic high on this pin indicates PLL lock 2 TXDATA Transmit Data Pin This pin is not used Connect to GND 3 CE Chip Enable A logic low on this pin powers down the device and puts the charge pump output into three-state mode Registers do not hold their values when CE = low 4 CLK Serial Clock Input CLK clocks in the serial data to the registers The data is latched into the 32-bit shift register on the CLK rising edge This input is a high impedance CMOS input 5 DATA Serial Data Input The serial data is loaded most significant bit (MSB) first with the two least significant bits (LSBs) as the control bits This input is a high impedance CMOS input 6 LE Load Enable, CMOS Input When LE goes high, the data stored in the shift registers is loaded into one of the four latches with the latch being selected using the control bits 7 MUXOUT Multiplexer Output This multiplexer output allows the lock detect, the scaled RF, the scaled reference frequency, logic high, logic low, or register readback data to be accessed externally 8 CREG Internal 8 V Regulator Output Pin Place three parallel capacitors as close to the CREG pin as possible: 47 µf, nf, and nf 9 CREG2 Internal 8 V Regulator Output Pin Place three parallel capacitors as close to the CREG2 pin as possible: 47 µf, nf, and nf 2 DC Place a µf capacitor in parallel with a nf capacitor to ground as close as possible to the DC pin 2 DC2 Place a µf capacitor in parallel with a nf capacitor to ground as close as possible to the DC2 pin 22 VP Charge Pump Power Supply Rev PrL Page 7 of 33

8 ADF453 Pin No Mnemonic Function 23 RSET Maximum Charge Pump Current Setting Resistor Connecting a resistor between the RSET pin and GND sets the maximum charge pump output current The nominal voltage potential at the RSET pin is 66 V The relationship between ICP and RSET is ICP_MAX = 296/RSET For example, with RSET = 27 kω, ICP MAX = 48 ma 24 CP Charge Pump Output When enabled, this provides ±ICP to the external loop filter, which in turn, drives the external VCO EPAD Exposed Pad The exposed pad must be connected to GND Rev PrL Page 8 of 33

9 TYPICAL PERFORMANCE CHARACTERISTICS PHASE NOISE (dbc/hz) HMC733, GHz HMC733, 5GHz HMC733, 2GHz 8 k k k M M M OFFSET FREQUENCY (Hz) Figure 4 Phase Noise vs Offset Frequency at GHz, 5 GHz, and 2 GHz with the HMC733, ICP = 35 ma, Integer Mode PHASE NOISE (dbc) ADF453 5 : Hz dBc/Hz 6 2: khz 3: khz 772dBc/Hz 622dBc/Hz 7 4: khz 5: MHz 6: 5MHz 7257dBc/Hz 2455dBc/Hz dBc/Hz 8 9 7: 5MHz dBc/Hz CARRIER GHz 6758dBm 7 k k k M M FREQUENCY (Hz) Figure 7 8 GHz Phase Noise vs Frequency with the HMC59, ICP = 35 ma, Fractional-N Mode PHASE NOISE (dbc) : Hz dBc/Hz 2: khz 8882dBc/Hz 3: khz 96385dBc/Hz 4: khz 97789dBc/Hz 5: MHz 9989dBc/Hz 6: 5MHz 2477dBc/Hz 7: MHz 3876dBc/Hz 8: 4MHz 54377dBc/Hz PHASE NOISE (dbc/hz) BLEED 5 6 PHASE NOISE db/ref 6dBc/Hz CARRIER GHz 37dBm 7 k k k FREQUENCY (Hz) Figure 5 2 GHz Phase Noise vs Frequency with the HMC733, ICP = 35 ma, Fractional-N Mode M M BLEED 3 k k k M M FREQUENCY OFFSET (Hz) Figure 8 Phase Noise vs Frequency Offset for Various Bleeds CURRENT (ma) mA UP 6582mA UP 55687mA UP 45562mA UP 35437mA UP 2532mA UP 587mA UP 562mA UP VOLTAGE (V) 562mA DOWN 587mA DOWN 2532mA DOWN 35437mA DOWN 45562mA DOWN 55687mA DOWN 6582mA DOWN 75937mA DOWN SENSITIVITY (dbm) INPUT FREQUENCY (GHz) Figure 6 Current vs CP Voltage, Charge Pump Compliance Figure 9 Sensitivity vs Input Frequency Rev PrL Page 9 of 33

10 ADF453 PHASE NOISE (dbc/hz) INT = pf INT = 68pF INT = pf INT = 5pF INT = 22pF PHASE NOISE (dbc/hz) dBm 4dBm dbm 4dBm 8dBm 2dBm 6dBm 2dBm k k k M M OFFSET FREQUENCY (Hz) Figure 57 MHz Phase Noise vs Offset Frequency at Various DC Block Capacitor Values, Integer Mode k k k M M M OFFSET FREQUENCY (Hz) Figure 5 GHz Phase Noise vs Offset Frequency at Various REFIN Powers, Fractional-N Mode, PFD = MHz Rev PrL Page of 33

11 THEORY OF OPERATION REFERENCE INPUT The reference input stage is shown in Figure 2 The reference input accepts an ac-coupled, single-ended signal During power-down, this circuit remains active and draws the same current from AVDD4 as during normal operation With no reference connected, AVDD4 drops to approximately 6 µa REF IN 2kΩ BUFFER TO R COUNTER ADF453 The N divider value is generated by a Σ-Δ modulator The ADF453 contains two selectable Σ-Δ modulators One modulator has a 25-bit fixed modulus (see Figure 4) and one has a variable modulus up to 49 bits (see Figure 5) DB28 in Register selects the modulator FROM RF INPUT STAGE RF INT DIVIDER N = INT + FRAC/2 25 N COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR TO PFD RF INPUT STAGE Figure 2 Reference Input Stage The RF input stage is shown in Figure 3 A 2-stage limiting amplifier follows the RF input stage to generate the current mode logic (CML) clock levels needed for the prescaler The RFINA and RFINB inputs require dc blocking capacitors to isolate the 65 V bias level from the input signal BIAS GENERATOR 65V AV DD FROM RF INPUT STAGE INT VALUE 2 25 FRAC VALUE Figure 4 Fixed Modulus N Divider RF INT DIVIDER N COUNTER N = INT + FRAC + 2 FRAC2 MOD2 THIRD-ORDER FRACTIONAL INTERPOLATOR TO PFD EXTERNAL AC COUPLING FOR SE INPUT 768Ω 768Ω INT REG FRAC REG FRAC2 VALUE MOD2 VALUE pf pf RF IN A RF IN B Figure 3 RF Input Stage GND N DIVIDER AND R COUNTER The N divider is used to divide the RF input signal down to the PFD frequency (fpfd) fpfd = REFIN (( + D)/(R ( + T))) () where: REFIN is the reference input frequency D is the REFIN doubler bit ( or ) R is the preset divide ratio of the binary 5-bit programmable reference counter ( to 32) T is the REFIN divide by 2 bit ( or ) Figure 5 Variable Modulus N Divider 25-Bit Fixed Modulus (R, DB28 = ) For the 25-bit fixed modulus, the RF VCO frequency (RFOUT) equation is RFOUT = fpfd (INT + (FRAC/2 25 )) (2) where: RFOUT is the RF VCO frequency INT is a 6-bit value set by DB[9:4] in Register (23 to for 4 5 prescaler, 75 to 65,535 for 8 9 prescaler) FRAC is a 25-bit value set by DB[28:4] in Register The minimum RF output resolution is set by fpfd 2 25 For example, if fpfd = MHz, the minimum resolution is 298 Hz By default, due to the architecture of the Σ-Δ modulator, there is a fixed (fpfd/2 26 ) offset added or subtracted from the programmed output frequency To remove this offset, set LSB_P (Register 5, DB24) Rev PrL Page of 33

12 ADF453 Variable Modulus (R, DB28 = ) For the variable modulus, the RF VCO frequency (RFOUT) equation is where: RFOUT = fpfd (INT + (FRAC + (FRAC2/MOD2))/2 25 ) (3) RFOUT is the output frequency of external VCO INT is a 6-bit value set by DB[9:4] in Register (23 to 65,535 for 4 5 prescaler, 75 to 65,535 for 8 9 prescaler) FRAC is a 25-bit value set by DB[28:4] in Register FRAC2 is a 24-bit value set by DB[27:4] in Register 3 MOD2 is a 24-bit value set by DB[27:4] in Register 4 The minimum RF output resolution is set by fpfd/2 49 Therefore, for fpfd = MHz, the minimum resolution is 776 µhz To achieve this resolution, MOD2 must be set to its maximum (2 24 ), 6,777,25 R COUNTER The 5-bit R counter allows the REFIN to be divided down to produce the reference clock to the PFD Division ratios from to 32 are allowed PFD AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between these inputs Figure 6 shows a PFD simplified schematic The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically ns This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level HIGH +IN HIGH IN D U CLR Q CLR2 D2 Q2 U2 UP DELAY DOWN U3 CHARGE PUMP Figure 6 PFD Simplified Schematic MUXOUT The output multiplexer on the ADF453 allows the user to access various internal nodes on the chip The M4, M3, M2, and M bits in Register 2 (see the Register 2 (R2) Map section) controls the state of MUXOUT Figure 7 shows the MUXOUT section in block diagram form Many of these access points are useful for debug For example, select the N divider output to check if the N divider is functioning correctly Most of the access points are self explanatory Set the CLK divider output signal to access the internal CLK divider signal used for phase resync During power-down (CE = logic low), MUXOUT is set to GND CP THREE-STATE OUTPUT DV DD GND R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT SERIAL DATA OUTPUT CLK DIVIDER OUTPUT R DIVIDER/2 N DIVIDER/2 READBACK DV DD MUX MUXOUT Figure 7 MUXOUT Schematic GND LOCK DETECTOR The lock detector compares the PFD output pulse width against a lock detector window Measurements are performed every PFD comparison cycle when LD CLK SEL = or every 32 nd cycle when LD CLK SEL = If the pulse width falls within the lock window, a counter is incremented If the counter reaches the count set by LD COUNT without an up or down pulse width exceeding the lock detect window and without a cycle slip occurring, the lock detect is declared When the lock detector has declared lock, the main mechanism to declare a loss of lock is for a cycle slip to occur This cycle slip is usually caused by a frequency error at the phase detector input, causing the phase error to grow until the error exceeds 36 The phase error then wraps around to This phase wrap around is a cycle slip A high level on MUXOUT indicates the PLL is in lock The lock detector window size, LD COUNT, and LD CLK SEL all affect the sensitivity of the lock detector Larger windows, smaller LD COUNT values, and LD CLK SEL = shorten the overall lock detect time and increase sensitivity Smaller windows, larger LD COUNT values, and LD CLK SEL = increase the overall lock detect time and reduce sensitivity Excessive lock detector sensitivity can cause multiple transitions between a locked state and out of lock state during frequency changes Insufficient lock detector sensitivity can cause the detector to indicate an out of lock state when, in fact, the PLL is locked The window size can be adjusted between 9 ns and 5 ns with LDP, Bits[9:8] in Register 6 and LD BIAS, Bits[3:3] in Register 9 The ideal window size is half way between the maximum window, set by the phase comparison period, tpfd ( ns for MHz reference and R = ), and the minimum is set by (IBLEED/ICP) tpfd (4) LD COUNT can range from 2 counts to 892 counts The fastest lock indication requires two measurement cycles (2 ns with MHz reference, R =, and LD CLK SEL = ) In practice, the lock indication takes much longer because of the loop filter on the phase comparator When LD CLK SEL =, a minimum 64 measurements are required (64 ns) Rev PrL Page 2 of 33

13 READBACK Register data can be read by setting MUXOUT to serial data output In this mode, the MUXOUT line concurrently transfers 32 bits of the previous written register value while clocking in 32 bits of write data To read back a specific register, chip revision code, or bit pattern, write b to Bits[3:28], Register 2 Writing to Bits[3:28] sets the MUXOUT pin to read back what is selected by Bits[9:4] in Register 2 INPUT SHIFT REGISTERS The ADF453 contains a programmable digital block Data is clocked into the 32-bit shift register on each rising edge of CLK The data is clocked in MSB first Data is transferred from the shift register to the chosen register on the rising edge of LE The destination latch is determined by the state of the four control bits (C4, C3, C2, and C) in the shift register The following are the four LSBs: DB3, DB2, DB, and DB The truth table for these bits is shown in Table 5 Figure 8 through Figure 2 show a summary of how the registers are programmed PROGRAM MODES Table 5 and Figure 2 through Figure 34 show how to set up the program modes in the ADF453 Several settings in the ADF453 are double buffered These include the MOD2, FRAC, FRAC2, R counter value, reference doubler, LSB P, CP, current setting, and RDIV2 Two events must occur before the device uses a new value for any of the double buffered settings First, the new value is latched into the device by writing to the appropriate register Second, a new ADF453 write must be performed on Register For example, updating the FRAC value requires a write to Register and a write to Register Write to Register first, followed by the write to Register The frequency change begins after the write to Register Double buffering ensures that the bits written to Register do not take effect until after the write to Register Table 5 C3, C2, and C Truth Table Control Bits C4 C3 C2 C Register R R R2 R3 R4 R5 R6 R7 R8 R9 R R R2 R3 Rev PrL Page 3 of 33

14 ADF453 REGISTER MAPS INT REGISTER (R) VARIABLE MODULUS 6-BIT INTEGER VALUE (INT) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB V N6 N5 N4 N3 N2 N N N9 N8 N7 N6 N5 N4 N3 N2 N C4() C3() C2() C() FRAC REGISTER (R) DITHER2 25-BIT FRAC VALUE (FRAC) DBB DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB D F25 F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() PHASE REGISTER (R2) DBB PHASE ADJUST 2-BIT PHASE VALUE (PHASE) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB PA P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P C4() C3() C2() C() FRAC2 REGISTER (R3) 24-BIT FRAC2 VALUE (FRAC2) DBB DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() MOD2 REGISTER (R4) 24-BIT MOD2 VALUE (MOD2) DBB DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M24 M23 M22 M2 M2 M9 M8 M7 M6 M5 M4 M3 M2 M M M9 M8 M7 M6 M5 M4 M3 M2 M C4() C3() C2() C() NOTES DBB = DOUBLE-BUFFERED Figure 8 Register Summary for Register (R) to Register 4 (R4) Rev PrL Page 4 of 33

15 ADF453 R DIVIDER REGISTER (R5) DLD MODES CP CURRENT SETTING DBB DBB DBB DBB LSB_P PRESCALER RDIV2 DBB REFERENCE DOUBLER DBB 5-BIT R COUNTER 2-BIT CLK DIVIDER VALUE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4D DB3 DB2 DB DB DL2 DL CPI4 CPI3 CPI2 CPI L P U2 U R5 R4 R3 R2 R D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D C4() C3() C2() C() FUNCTION REGISTER (R6) BLEED CURRENT BLEED POLARITY BLEED ENABLE INT MODE ABP LOL EN SD RESET CP_TRISTATE LDP PD POLARITY POWER DOWN CP THREE-STATE COUNTER RESET DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC BP BE IM A LOL SD CP LDP2 LDP PP PD C3 CR C4() C3() C2() C() CLOCK 2 REGISTER (R7) LD COUNT LD CLK SEL N DELAY PS BIAS CLK DIV MODE 2-BIT CLK 2 DIVIDER VALUE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB CN3 CN2 CN LD ND2 ND PB2 PB C2 C D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D C4() C3() C2() C() REGISTER (R8) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() LOCK DETECTOR BIAS REGISTER (R9) LD BIAS DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB LB2 LB C4() C3() C2() C() NOTES DBB = DOUBLE-BUFFERED Figure 9 Register Summary for Register 5 (R5) to Register 9 (R9) Rev PrL Page 5 of 33

16 ADF453 REGISTER (R) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() POWER-DOWN SELECT REGISTER (R) POWER-DOWN SELECT DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB PDS C4() C3() C2() C() MUXOUT REGISTER (R2) MUXOUT LOGIC LEVEL MASTER RESET LE SEL READBACK SELECT DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M4 M3 M2 M LL MR L R6 R5 R4 R3 R2 R C4() C3() C2() C() REGISTER (R3) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() Figure 2 Register Summary for Register (R) to Register 3 (R3) Rev PrL Page 6 of 33

17 ADF453 REGISTER (R) MAP Frequency changes only occur on a write to Register Variable Modulus Register, Bit 28 = enables the 25-bit fixed modulus Register, Bit 28 = enables the variable modulus See the N Divider and R Counter section for more information INT REGISTER (R) INT Value Register, Bits[9:4] set the INT value See the N Divider and R Counter section for more information VARIABLE MODULUS 6-BIT INTEGER VALUE (INT) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB V N6 N5 N4 N3 N2 N N N9 N8 N7 N6 N5 N4 N3 N2 N C4() C3() C2() C() V VARIABLE MODULUS 25-BIT FIXED MODULUS VARIABLE MODULUS N6 N5 N5 N4 N3 N2 N INTEGER WORD NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED ,533 65,534 65,535 Figure 2 Register (R) Map PRESCALER 4/5: 23 INT 3277 PRESCALER 8/9: 75 INT Rev PrL Page 7 of 33

18 ADF453 REGISTER (R) MAP DITHER2 Set Register, Bit 3 = to enable the Σ-Δ modulator dither Enabling DITHER2 can reduce fractional spurs DITHER2 FRAC FRAC REGISTER (R) 25-BIT FRAC VALUE (FRAC) Register, Bits[28:4] set the FRAC value See the N Divider and R Counter section for more information When using a fixed modulus, Bits [28:4] are the FRAC value DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DBB D F25 F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() D DITHER2 OFF ON NOTES DBB = DOUBLE-BUFFERED F25 F24 F2 F FRAC WORD ,554,428 33,554,429 33,554,43 33,554,43 Figure 22 Register (R) Map Rev PrL Page 8 of 33

19 ADF453 REGISTER 2 (R2) MAP Phase Adjust Set Register 2, Bit 3 to to enable phase adjust Phase adjust increases the phase of the output relative to the current phase The phase change occurs after a write to Register Phase Shift = (Phase Value 36 )/2 2 (5) PHASE ADJUST PHASE REGISTER (R2) Phase Value Register 2, Bits[5:4] set the phase value for phase adjust For example, setting the phase value = 52 increases the output phase by 45 If phase adjust is not used, set the phase value to 2-BIT PHASE VALUE (PHASE) DBB DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB PA P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P C4() C3() C2() C() PA PHASE ADJUST DISABLED ENABLED NOTES DBB = DOUBLE-BUFFERED Figure 23 Register 2 (R2) Map P2 P P2 P PHASE VALUE 2 3 4,92 4,93 4,94 4, Rev PrL Page 9 of 33

20 ADF453 REGISTER 3 (R3) MAP FRAC2 Register 3, Bits[27:4] set the FRAC2 value See the N Divider and R Counter section for more information When using a fixed modulus, FRAC2 is ignored FRAC2 REGISTER (R3) 24-BIT FRAC2 VALUE (FRAC2) DBB DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() ) NOTES DBB = DOUBLE-BUFFERED F24 F23 F2 F FRAC2 WORD 2 3 6,777,22 6,777,23 6,777,24 6,777,25 Figure 24 Register 3 (R3) Map Rev PrL Page 2 of 33

21 REGISTER 4 (R4) MAP MOD2 Register 4, Bits[27:4] set the MOD2 value See the N Divider and R Counter section for more information When using a fixed modulus, MOD2 is ignored MOD2 REGISTER (R4) 24-BIT MOD2 VALUE (MOD2) DBB ADF453 DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M24 M23 M22 M2 M2 M9 M8 M7 M6 M5 M4 M3 M2 M M M9 M8 M7 M6 M5 M4 M3 M2 M C4() C3() C2() C() NOTES DBB = DOUBLE-BUFFERED M24 M23 M2 M MOD2 WORD 2 3 6,777,22 6,777,23 6,777,24 6,777,25 Figure 25 Register 4 (R4) Map Rev PrL Page 2 of 33

22 ADF453 REGISTER 5 (R5) MAP DLD Mode Register 5, Bits[3:3] set the digital lock detect pin state For normal digital lock detect, set Register 5, Bits[3:3] = b Other options tristate the pin and force high or low logic levels, as shown in Figure 26 CP Current Setting Register 5, Bits[28:25] set the charge pump current Set these bits to the charge pump current that the loop filter is designed for based on the application of the user The recommended practice is to design the loop filter for a charge pump current of 24 ma or 27 ma and then use the programmable charge pump current to fine tune the loop filter frequency response LSB_P Register 5, Bit 24 = enables a 26 th bit in the fixed modulus MOD value Enabling the 26 th bit reduces fractional spurs but the reduction also adds a fixed fpfd/2 26 frequency offset to the output frequency To disable this frequency offset, set Register 5, Bit 24 = Prescaler The dual modulus prescaler (4/5 and 8/9) is set by Register 5, Bit 23 The prescaler, at the input to the N divider, divides down the frfin signal so that the N divider can work The prescaler is based on a synchronous 4/5 core The prescaler setting affects the RF frequency and the minimum and maximum INT value as follows: Prescaler 4/5: 23 INT 3277, frfin_max = 325 GHz Prescaler 8/9: 75 INT 65535, frfin_max = 265 GHz RDIV2 Register 5, Bit 22 controls the reference divide by 2 block See the N Divider and R Counter section for more information This feature can provide a 5% duty cycle signal to the PFD Reference Doubler Register 5, Bit 2 controls the reference doubler block See the N Divider and R Counter section for more information R Counter Register 5, Bits[2:6] control the R counter value See the N Divider and R Counter section for more information CLK Divider Register 5, Bits[5:4] control the CLK divider value See the Phase Resync section for more information Rev PrL Page 22 of 33

23 ADF453 R DIVIDER REGISTER (R5) DBB DBB DBB DBB DLD MODE CP CURRENT SETTING LSB_P PRESCALER RDIV2 DBB REFERENCE DOUBLER DBB 5-BIT R COUNTER 2-BIT CLK DIVIDER VALUE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DL2 DL CPI4 CPI3 CPI2 CPI L P U2 U R5 R4 R3 R2 R D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D C4() C3() C2() C() DL2 DL DLD PIN TRISTATE DIGITAL LOCK DETECT LOW HIGH U REFERENCE DOUBLER DISABLED ENABLED U2 R DIVIDER DISABLED ENABLED P PRESCALER 4/5 D2 D D2 D CLK DIVIDER VALUE 2 3 4,92 4,93 4,94 4,95 8/9 NOTES DBB = DOUBLE-BUFFERED L LSB P ON: 5 LSB OFFSET OFF: NO OFFSET I CP (ma) CPI4 CPI3 CPI2 CPI 27kΩ R5 R4 R3 R2 R R COUNTER DIVIDE RATIO Figure 26 Register 5 (R5) Map Rev PrL Page 23 of 33

24 ADF453 REGISTER 6 (R6) MAP Bleed Current Register 6, Bits[3:24] set the bleed current The optimum bleed current is set by Bleed Current (µa) = (8 9 + (7/fRF)) (ICP fpfd) 6 (6) where: frf is the RF signal frequency in Hz ICP is the charge pump current in A fpfd is the PFD frequency in Hz Bleed Polarity Register 6, Bit 23 controls the polarity of the bleed current Negative polarity is the typical usage Bleed Enable In fractional mode of operation, charge pump linearity and, ultimately, phase noise and spurious performance, is much better if the VCO and reference inputs to the phase detector operate with a phase offset This phase offset is implemented by adding a constant bleed current at the output of the charge pump Use bleed only when operating in fractional-n mode, that is FRAC or FRAC2 not equal to Set Register 6, Bit 22 = to enable bleed INT Mode Register 6, Bit 2 completely disables the fractional-n Σ-Δ modulator (SDM) Setting Register 6, Bit 2 = disables the SDM so the ADF453 operates purely in integer N mode Disabling the SDM improves phase noise performance and changes the frequency resolution to fpfd ABP Register 6, Bit 9 affects the antibacklash pulse width Recommended setting for best figure of merit (FOM) is narrow (Register 6, Bit 9 = ) Loss of Lock (LOL) Enable When loss of lock is enabled, if digital lock detect is asserted, and the reference signal is removed, digital lock detect goes low Set Register 6, Bit 8 = to enable loss of lock (recommended) Sigma-Delta (SD) Reset When Register 6, Bit 7 = on a write to Register, the SDM is temporarily set to a fractional value of The SD reset ensures a consistent fractional spur pattern but also results in a glitch in the output frequency when the N divider momentarily outputs FRAC = Remove this glitch by setting Register 6, Bit 7 = (recommended setting) CP Tristate When Register 6, Bit 6 =, the phase detector operates but the charge pump output is tristate Lock Detect Precision (LDP) Register 6, Bits[9:8] and Register 9, Bits[3:3] control the sensitivity of the digital lock detector Lock detect precision (Register 6, Bits[9:8]) in conjunction with lock detector bias (Register 9, Bits[3:3]) adjusts the width of the digital lock detector window Lock is declared when the PFD reference arrival time and divided VCO input arrival times consistently differ by less than the LDP value Small LDP settings may cause a false out of lock indication when used with large bleed currents See the Lock Detector section for more information Phase Detector (PD) Polarity If using a noninverting loop filter and a VCO with a positive tuning slope, set PD polarity to positive If using an inverting loop filter and a VCO with a negative tuning slope, set PD polarity to positive If using a noninverting loop filter and a VCO with a negative tuning slope, set PD polarity to negative If using an inverting loop filter and a VCO with a positive tuning slope, set PD polarity to negative Power Down Set Register 6, Bit 6 = to perform a software power-down All circuit blocks are disabled and the chip enters a low power state drawing approximately 3 ma Set Register 6, Bit 6 = to reenable the chip Register values are not lost during power-down Only one power-down mode is available via Register, Bit 3 Set Register, Bit 3 = to leave the internal 8 V N divider regulator on during power-down CP Three-State Setting Register 6, Bit 5 = tristates the charge pump output Set Register 5, Bit 5 = for normal operation Counter Reset Setting Register 6, Bit 4 = holds the N divider and R counter in reset For example, there are no signals going to the PFD Rev PrL Page 24 of 33

25 ADF453 FUNCTION REGISTER (R6) BLEED CURRENT BLEED POLARITY BLEED ENABLE INT MODE ABP LOL EN SD RESET CP_TRISTATE LDP PD POLARITY POWER DOWN CP THREE-STATE COUNTER RESET DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC BP BE IM A LOL SD CP LDP2 LDP PP PD C3 CR C4() C3() C2() C() BLEED POLARITY NEGATIVE POSITIVE IM INT MODE SD ON (FRAC-N) SD OFF (INT-N) CP CHARGE PUMP TRISTATE CR COUNTER RESET DISABLED ENABLED BLEED ENABLE DISABLED ENABLED A ABP WIDE NARROW OFF ON C3 CP THREE-STATE DISABLED ENABLED L LOL PD POWER DOWN DISABLED NORMAL OPERATION ENABLED POWER-DOWN DEVICE BC8 BC7 BC2 BC BLEED CURRENT (µa) SD SD RESET RESET ON R WRITE NO RESET PP PD POLARITY NEGATIVE POSITIVE LDP2 LDP R9[3] R9[3] LDP 43ns 28ns 7ns 9ns 52ns 35ns 2ns 2ns 7ns 47ns 29ns 6ns 5ns 79ns 49ns 28ns Figure 27 Register 6 (R6) Map Rev PrL Page 25 of 33

26 ADF453 REGISTER 7 (R7) MAP Lock Detector Count (LD COUNT) Initial value of the lock detect counter See operation of the lock detector in the Lock Detector section for more information Lock Detect Clock Select (LD CLK SEL) The lock detector checks for lock on every phase comparison cycle when LD CLK SEL = Otherwise, the lock detector checks for lock on every 32 nd cycle Use LD CLK SEL = to speed up declaration of lock at the cost of reduced lock indication stability during frequency changes SDM to N Divider Timing Adjustment (N Delay) This control adjusts the timing between the SDM output and the N divider Set these bits to b Prescaler Bias (PS BIAS) Set these bits to b CLK Divider Mode Setting Register 7, Bits[9:8] = b enables phase resync See the Phase Resync section for more information When not using phase resync, set Register 7, Bits[9:8] = b CLK 2 Divider Value Register 7, Bits[7:6] control the CLK2 divider value This controls the timing of the phase resync pulse See the Phase Resync section for more information CLOCK 2 REGISTER (R7) LD COUNT LD CLK SEL N DELAY PS BIAS CLK DIV MODE 2-BIT CLK 2 DIVIDER VALUE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB CN3 CN2 CN LD ND2 ND PB2 PB C2 C D2 D D D9 D8 D7 D6 D5 D4 D3 D2 D C4() C3() C2() C() CN3 CN2 CN LOCK DETECTOR COUNT ND2 PB2 PB PRESCALER BIAS PROGRAM THIS VALUE SDM TO N DELAY ND PROGRAM THIS VALUE DB7 DB6 DB7 DB6 C2 C CLK DIV MODE CLK DIVIDER OFF PHASE RESYNC CLK2 DIVIDER VALUE 2 3 4,92 4,93 4,94 4,95 LD LOCK DETECTOR CLOCK SELECT f PFD 32 f PFD Figure 28 Register 7 (R7) Map Rev PrL Page 26 of 33

27 REGISTER 8 (R8) MAP Set all reserved bits to zero REGISTER 9 (R9) MAP Lock Detector Bias ADF453 The lock detector window size is set by adjusting the lock detector bias in conjunction with the lock detector precision (Register 6, Bits[9:8]) See the Lock Detector section REGISTER (R8) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() Figure 29 Register 8 (R8) Map LOCK DETECTOR BIAS REGISTER (R9) LD BIAS DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB LB2 LB C4() C3() C2() C() LB2 LB LOCK DETECTOR BIAS 4µA 3µA 2µA µa Figure 3 Register 9 (R9) Map Rev PrL Page 27 of 33

28 ADF453 REGISTER (R) MAP Set all reserved bits to zero REGISTER (R) MAP Power-Down Select Only one power-down option is available Program Register, Bit 3 = Set Register 6, Bit 6 = to power down the device REGISTER (R) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB Figure 3 Register (R) Map C4() C3() C2() C() POWER-DOWN SELECT REGISTER (R) POWER-DOWN SELECT DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB PDS C4() C3() C2() C() PDS POWER-DOWN SELECT PROGRAM THIS VALUE Figure 32 Register (R) Map Rev PrL Page 28 of 33

29 REGISTER 2 (R2) MAP MUXOUT Register 2, Bits[3:28] are used to select the MUXOUT signal Register data can be read either by selecting serial data output or readback Serial data output sends the 32 bits of register data that was written in the previous access Readback sends the data as defined by the readback select bits, Register 2, Bits[9:4] Logic Level Register 2, Bit 27 selects the DLD and MUXOUT logic level Master Reset Register 2, Bit 22 = resets all registers to all zeros ADF453 LE SEL Register 2, Bit 2 = synchronizes the rising edge of LE on an SPI write with the falling edge of the reference signal This recommended setting ensures there is no glitch from asynchronous loading Set Register 2, Bit 2 = if it is necessary to write data into the ADF453 when no reference is present Readback Select Register 2, Bits[9:4] select the value to be read back For more information, see the Readback section MUXOUT REGISTER (R2) MUXOUT LOGIC LEVEL MASTER RESET LE SEL READBACK SELECT DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M4 M3 M2 M LL MR L R6 R5 R4 R3 R2 R C4() C3() C2() C() R6 R5 R4 R3 R2 R READBACK SELECT LL DLD AND MUXOUT LEVEL 8V LOGIC HIGH 33V LOGIC HIGH MR MASTER RESET NORMAL OPERATION RESETS ALL REGISTERS L LE SEL LE FROM PIN LE SYNC D WITH RISING EDGE OF R-DIVIDER OUTPUT 32 ZEROS R R R2 R3 R4 R5 R6 R7 R8 R9 R R R2 M4 M3 M2 M OUTPUT THREE-STATE OUTPUT R3 INT (6-BIT R[9:4] VALUE) FRAC (7-BIT R[:4] VALUE) DV DD GND R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT SERIAL DATA OUTPUT READBACK CLK DIVIDER OUTPUT R DIVIDER/2 N DIVIDER/2 32 ZEROS REVISION CODE Figure 33 Register 2 (R2) Map Rev PrL Page 29 of 33

30 ADF453 REGISTER 3 (R3) MAP Set all reserved bits to zero REGISTER (R3) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB Figure 34 Register 3 (R3) Map C4() C3() C2() C() Rev PrL Page 3 of 33

31 APPLICATIONS INFORMATION INITIALIZATION SEQUENCE The following sequence of registers is the correct sequence for initial power-up of the ADF453 after the correct application of voltages to the supply pins: Register 3 2 Register 2 3 Register 4 Register 5 Register 9 6 Register 8 7 Register 7 8 Register 6 9 Register 5 Register 4 Register 3 2 Register 2 3 Register 4 Register RF SYNTHESIZER: A WORKED EXAMPLE OF 25-BIT FIXED MODULUS MODE The following equation governs how to program the synthesizer: RFOUT = (INT + (FRAC/2 25 )) fpfd (7) where: RFOUT is the RF frequency output INT is the integer division factor FRAC is the fractional numerator fpfd is the PFD frequency For example, in a system where a 22 GHz RF frequency output (RFOUT) is required and a MHz reference frequency input (REFIN) is available, the frequency resolution is fres = REFIN/2 25 fres = MHz/2 25 = 298 Hz From Equation and Equation 2, fpfd = ( MHz ( + )/) = MHz 22 GHz = MHz (N + FRAC/2 25 ) Calculating INT and FRAC values, INT = int(rfout/fpfd) = 2; FRAC = (int(rfout/fpfd) INT) 2 25 = where: INT is the 6-bit INT value in Register FRAC is the 25-bit FRAC value in Register int() makes an integer of the argument in parentheses ADF453 Note that is rounded to 67,89, resulting in a small frequency error For exact frequency, use the variable modulus mode RF SYNTHESIZER: A WORKED EXAMPLE OF VARIABLE MODULUS MODE The following is an example how to program the ADF453 synthesizer: RFOUT = fpfd (INT + (FRAC + (FRAC2/MOD2))/2 25 ) (8) where: RFOUT is the output frequency of external VCO INT is a 6-bit value set by DB[9:4] in Register (23 to 65,535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler) FRAC is a 25-bit value set by DB[28:4] in Register FRAC2 is a 24-bit value set by DB[27:4] in Register 3 MOD2 is a 24-bit value set by DB[27:4] in Register 4 fpfd is the PFD frequency For example, in a system where 22 GHz RFOUT is required and a MHz fpfd is available, INT = int(rfout/fpfd) = 2 FRAC = int(((rfout/fpfd) INT) 2 25 ) = 6788 where: int() makes an integer of the argument in parentheses Remainder = 64 Remainder = FRAC2/MOD2 = 64 FRAC2 = 64 MOD2 = MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fres) required at the RF output REFERENCE DOUBLER AND REFERENCE DIVIDER The on-chip reference doubler allows the input reference signal to be doubled Doubling is useful for increasing the PFD comparison frequency Setting the PFD frequency higher improves the noise performance of the system Doubling the PFD frequency usually improves noise performance by 3 db It is important to note that the reference input cannot operate above 225 MHz when the reference doubler is on The PFD maximum operating frequency is 25 MHz (integer N mode) or 25 MHz (fractional-n mode) due to a limitation in the speed of the Σ-Δ circuit The reference divide by 2 divides the reference signal by 2, resulting in a 5% duty cycle PFD frequency Rev PrL Page 3 of 33

32 ADF453 SPUR MECHANISMS This section describes the two different spur mechanisms that arise with a PLL, and how to minimize them in the ADF453 Integer Boundary Spurs Interactions between the RF VCO frequency and the reference frequency cause integer boundary spurs When these frequencies are not integer related (the point of a fractional-n synthesizer), spur sidebands appear on the VCO output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the VCO frequency These spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth Therefore, the name integer boundary spurs Reference Spurs Reference spurs are generally not a problem in fractional-n synthesizers because the reference offset is far outside the loop bandwidth However, any reference feedthrough mechanism that bypass the loop can cause a problem Feedthrough of low levels of on-chip reference switching noise, through the RFINA pin or the RFINB pin back to the VCO, can result in reference spur levels as high as 9 dbc PCB layout must ensure adequate isolation between VCO traces and the input reference to avoid a possible feedthrough path on the board PHASE RESYNC The output of a 25-bit fractional-n PLL can settle to any of the 2 25 phase offsets with respect to the input reference The phase resync feature in the ADF453 produces a consistent output phase offset with respect to the input reference This consistent output phase offset with respect to the input reference is necessary in applications where the output phase and frequency are important, such as digital beam forming See the Phase Programmability section to program a specific RF output phase when using phase resync Phase resync is enabled by setting Register 7, Bits[9:8] = b When phase resync is enabled, an internal timer generates sync signals at intervals of tsync given by the following formula: tsync = CLK CLK2 tpfd (9) where: CLK is the decimal value programmed in Register 5, Bits[5:4] CLK2 is the decimal value programmed in Register 7, Bits[7:6], while Register 7, Bits[5:4] = b tpfd is the PFD reference period (/fpfd) When a new frequency is programmed, the second sync pulse after the LE rising edge resynchronizes the output phase to the reference Program the tsync time to a value that is at least as long as the worst case lock time to guarantee that the phase resync occurs after the last cycle slip in the PLL settling transient In the example shown in Figure 35, tsync is set to 55 µs The second sync pulse and any later sync pulses are ignored LE SYNC (INTERNAL) FREQUENCY PHASE LAST CYCLE SLIP PLL SETTLES TO INCORRECT PHASE PLL SETTLES TO CORRECT PHASE AFTER RESYNC TIME (µs) Figure 35 Phase Resync Example Phase Programmability The phase word in Register 2 controls the RF output phase As this word is changed from to 2 2, the RF output phase changes over a 36 range in steps of Phase Value 36 / Rev PrL Page 32 of 33