Microwave Wideband Synthesizer with Integrated VCO ADF5355

Transcription

1 4 Microwave Wideband Synthesizer with Integrated VCO FEATURES RF output frequency range: 54 MHz to 3,6 MHz Fractional-N synthesizer and integer-n synthesizer High resolution 38-bit modulus Phase frequency detector (PFD) operation to 25 MHz Reference frequency operation to 6 MHz Maintains frequency lock over 4 C to +85 C Low phase noise, voltage controlled oscillator (VCO) Programmable divide by, 2, 4, 8, 6, 32, or 64 output Analog and digital power supplies: 3.3 V Charge pump and VCO power supplies: 5. V, typical Logic compatibility:.8 V Programmable dual modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function Analog and digital lock detect Supported in the ADIsimPLL design tool APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM CE AV DD AV DD DV DD GENERAL DESCRIPTION The allows implementation of fractional-n or integer-n phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 3.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 54 MHz to 68 MHz. V P The has an integrated VCO with a fundamental output frequency ranging from 34 MHz to 68 MHz. In addition, the VCO frequency is connected to divide by, 2, 4, 8, 6, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable. Control of all on-chip registers is through a simple 3-wire interface. The operates with analog and digital power supplies ranging from 3.5 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The also contains hardware and software power-down modes. R SET V VCO V RF REF IN A REF IN B 2 DOUBLER -BIT R COUNTER 2 DIVIDER LOCK DETECT MULTIPLEXER MUXOUT C REG C REG 2 CLK DATA LE DATA REGISTER FUNCTION LATCH CHARGE PUMP PHASE COMPARATOR CP OUT V TUNE V REF INTEGER REG FRACTION REG MODULUS REG VCO CORE 2 V BIAS V REGVCO THIRD-ORDER FRACTIONAL INTERPOLATOR OUTPUT STAGE RF OUT B PDB RF N COUNTER /2/4/8/ 6/32/64 OUTPUT STAGE RF OUT A+ RF OUT A MULTIPLEXER A GND CP GND A GNDRF SD GND A GNDVCO Figure Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 * Product Page Quick Links Last Content Update: //27 Comparable Parts View a parametric search of comparable parts Evaluation Kits Evaluation Board Documentation : Microwave Wideband Synthesizer with Integrated VCO User Guides UG-82: Evaluating the Frequency Synthesizer for Phase-Locked Loops Tools and Simulations ADIsimFrequency Planner Tool ADIsimPLL Reference Materials Technical Articles Low Cost PLL with Integrated VCO Enables Compact LO Solutions Design Resources Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

3 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History...3 Specifications...4 Timing Characteristics...7 Absolute Maximum Ratings...8 Transistor Count...8 ESD Caution...8 Pin Configuration and Function Descriptions...9 Typical Performance Characteristics... Circuit Description...6 Reference Input...6 RF N Divider...6 Phase Frequency Detector (PFD) and Charge Pump...7 MUXOUT and Lock Detect...7 Input Shift Registers...7 Program Modes...8 VCO...8 Output Stage...8 Register Maps...2 Register...22 Register...23 Register Register Register Register Register Register Register Register Register Register Register Register Initialization Sequence Frequency Update Sequence RF Synthesizer A Worked Example Reference Doubler and Reference Divider Spurious Optimization and Fast Lock Optimizing Jitter Spur Mechanisms Lock Time Applications Information Power Supplies Printed Circuit Board (PCB) Design Guidelines for a Chip- Scale Package Output Matching Outline Dimensions Ordering Guide Rev. B Page 2 of 38

4 REVISION HISTORY /27 Rev. A to Rev B Change to Features Section... Changes to Doubler Enabled Parameter and Endnote 3, Table... 4 Changes to Table Changes to Table Changes to Table Changes to Reference Input Section and Figure 32 Caption... 6 Changes to Table Changes to Phase Resync Section Change to Reference Doubler Section Changes to Power-Down Section Changes to Negative Bleed Section Changes to Loss of Lock (LOL) Mode Section... 3 Changes to Register Initialization Sequence Section and Frequency Update Sequence Section Changes to Power Supplies Section and Figure /25 Rev. to Rev. A Changed Register 5, Bit DB5 Value from to...throughout Changed Register 5 Default Value from x85 to x825...throughout Changed Register 8 Default Value from x2d428 to x2d428...throughout Changes to Table... 4 Changed Timing Diagram Section to Write Timing Diagram Section... 7 Changes to Table 4... Changes to Figure 4 to Figure 6... Added Figure 7 to Figure 9; Renumbered Sequentially... Changes to Figure to Figure Changes to Figure Changes to Figure 23 and Figure Changes to Figure 28 to Figure 3 and Figure 3 Caption... 5 Changes to Reference Input Section and INT, FRAC, MOD, and R Counter Relationship Section... 6 Changes to Phase Frequency Detector (PFD) and Charge Pump Section... 7 Changes to VCO Section and Output Stage Section... 8 Changes to Automatic Calibration (AUTOCAL) Section Changes to Figure Changes to MUXOUT Section Changes to Reference Mode Section and Counter Reset Section Changes to Negative Bleed Section Changes to Charge Pump Bleed Current Section Changes to Register 9 Section, VCO Band Division Section, Timeout Section, Automatic Level Calibration Timeout Section, and Synthesizer Lock Timeout Section... 3 Changes to ADC Conversion Clock (ADC_CLK_DIV) Section Changes to Phase Resync Clock Divider Value Section and Frequency Update Sequence Section Changes to RF Synthesizer A Worked Example Section Changes to Lock Time Section and Automatic Level Calibration Timeout Section Added Lock Time A Worked Example Section /24 Revision : Initial Version Rev. B Page 3 of 38

5 SPECIFICATIONS AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = V, R SET = 5. kω, dbm referred to 5 Ω, TA = TMIN to TMAX, unless otherwise noted. Table. Parameter Symbol Min Typ Max Unit Test Conditions/Comments REFINA/REFINB CHARACTERISTICS Input Frequency For f < MHz, ensure slew rate > 2 V/µs Single-Ended Mode 25 MHz Differential Mode 6 MHz Doubler Enabled MHz Doubler is set in Register 4, Bit DB26 Input Sensitivity Single-Ended Mode.4 AVDD V p-p REFINA biased at AVDD/2; ac coupling ensures AVDD/2 bias Differential Mode.4.8 V p-p LVDS and LVPECL compatible, REFINA/REFINB biased at 2. V; ac coupling ensures 2. V bias Input Capacitance Single-Ended Mode 6.9 pf Differential Mode.4 pf Input Current ±6 µa Single-ended reference programmed ±25 µa Differential reference programmed Phase Detector Frequency 25 MHz CHARGE PUMP (CP) Charge Pump Current, Sink/Source ICP RSET = 5. kω High Value 4.8 ma Low Value.3 ma RSET Range 5. kω Fixed Current Matching 3 %.5 V VCP VP.5 V ICP vs. VCP 3 %.5 V VCP VP.5 V ICP vs. Temperature.5 % VCP = 2.5 V LOGIC INPUTS Input High Voltage VINH.5 V Input Low Voltage VINL.6 V Input Current IINH/IINL ± µa Input Capacitance CIN 3. pf LOGIC OUTPUTS Output High Voltage VOH DVDD.4 V.5.8 V.8 V output selected Output High Current IOH 5 µa Output Low Voltage VOL.4 V IOL 2 = 5 µa POWER SUPPLIES See Table 6 Analog Power AVDD V Digital Power and RF Supply Voltage DVDD, VRF AVDD Voltages must equal AVDD Charge Pump and VCO Supply Voltage VP, VVCO V VP must equal VVCO Charge Pump Supply Power Current IP 8 9 DIDD + AIDD ma Output Dividers 6 to 36 ma Each output divide by 2 consumes 6 ma Supply Current IVCO 7 85 ma Rev. B Page 4 of 38

6 Parameter Symbol Min Typ Max Unit Test Conditions/Comments RFOUTA±/RFOUTB Supply Current IRF OUT x± RFOUTA± output stage is programmable; enabling RFOUTB draws negligible extra current 6 2 ma 4 dbm setting 3 35 ma dbm setting 42 5 ma 2 dbm setting 55 7 ma 5 dbm setting Low Power Sleep Mode 5 µa Hardware power-down selected µa Software power-down selected RF OUTPUT CHARACTERISTICS VCO Frequency Range MHz Fundamental VCO range RFOUTB Output Frequency MHz 2 VCO output (RFOUTB) RFOUTA+/RFOUTA Output Frequency MHz VCO Sensitivity KV 5 MHz/V Frequency Pushing (Open-Loop) 5 MHz/V Frequency Pulling (Open-Loop).5 MHz Voltage standing wave ratio (VSWR) = 2: RFOUTA+/RFOUTA 3 MHz VSWR = 2: RFOUTB Harmonic Content Second 27 dbc Fundamental VCO output (RFOUTA+) 22 dbc Divided VCO output (RFOUTA+) Third 2 dbc Fundamental VCO output (RFOUTA+) 2 dbc Divided VCO output (RFOUTA+) Fundamental VCO Feedthrough 8 dbm RFOUTB = GHz 55 dbc RFOUTA+/RFOUTA = GHz; VCO frequency = 4 GHz RF Output Power 4 +8 dbm RFOUTA+ = GHz; 7.5 nh inductor to VRF 3 dbm RFOUTA+/RFOUTA = 6.8 GHz; 7.5 nh inductor to VRF dbm RFOUTB = 6.8 GHz dbm RFOUTB = 3.6 GHz RF Output Power Variation ± db RFOUTA+/RFOUTA = 5 GHz ± db RFOUTB = GHz RF Output Power Variation (over Frequency) ±6 db RFOUTA+/RFOUTA = GHz to 6.8 GHz ±4 db RFOUTB = 6.8 GHz to 3.6 GHz Level of Signal with RF Output Disabled 6 dbm RFOUTA+/RFOUTA = GHz 3 dbm RFOUTA+/RFOUTA = 6.8 GHz 5 dbm RFOUTB = 6.8 GHz 7 dbm RFOUTB = 3.6 GHz NOISE CHARACTERISTICS Fundamental VCO Phase Noise Performance VCO noise in open-loop conditions 6 dbc/hz khz offset from 3.4 GHz carrier 36 dbc/hz 8 khz offset from 3.4 GHz carrier 38 dbc/hz MHz offset from 3.4 GHz carrier 55 dbc/hz MHz offset from 3.4 GHz carrier 3 dbc/hz khz offset from 5. GHz carrier 33 dbc/hz 8 khz offset from 5. GHz carrier 35 dbc/hz MHz offset from 5. GHz carrier 53 dbc/hz MHz offset from 5. GHz carrier dbc/hz khz offset from 6.8 GHz carrier 3 dbc/hz 8 khz offset from 6.8 GHz carrier 32 dbc/hz MHz offset from 6.8 GHz carrier 5 dbc/hz MHz offset from 6.8 GHz carrier Rev. B Page 5 of 38

7 Parameter Symbol Min Typ Max Unit Test Conditions/Comments VCO 2 Phase Noise Performance VCO noise in open-loop conditions dbc/hz khz offset from 6.8 GHz carrier 3 dbc/hz 8 khz offset from 6.8 GHz carrier 32 dbc/hz MHz offset from 6.8 GHz carrier 49 dbc/hz MHz offset from 6.8 GHz carrier 7 dbc/hz khz offset from GHz carrier 27 dbc/hz 8 khz offset from GHz carrier 29 dbc/hz MHz offset from GHz carrier 47 dbc/hz MHz offset from GHz carrier 3 dbc/hz khz offset from 3.6 GHz carrier 24 dbc/hz 8 khz offset from 3.6 GHz carrier 26 dbc/hz MHz offset from 3.6 GHz carrier 44 dbc/hz MHz offset from 3.6 GHz carrier Normalized In-Band Phase Noise Floor Fractional Channel 5 22 dbc/hz Integer Channel dbc/hz Normalized /f Noise, PN_f 7 6 dbc/hz khz offset; normalized to GHz Integrated RMS Jitter 5 fs Spurious Signals due to PFD Frequency 8 dbc V CP is the voltage at the CP OUT pin. 2 I OL is the output low current. 3 TA = 25 C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5. V; prescaler = 4/5; frefin = MHz; fpfd = 6.44 MHz; and frf = 65 MHz. For the nominal DIDD + AIDD (62 ma): DIDD = 5 ma (typical), AI DD (Pin 5) = 24 ma (typical), AI DD (Pin 6) = 23 ma (typical). 4 RF output power using the EV-SDZ evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins are terminated in 5 Ω. 5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: 22 + log(fpfd) + 2logN. The value given is the lowest noise mode for the fractional channel. 6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: log(fpfd) + 2logN. The value given is the lowest noise mode for the integer channel. 7 The PLL phase noise is composed of /f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the /f noise contribution at an RF frequency (frf) and at a frequency offset (f) is given by PN = P_f + log( khz/f) + 2log(fRF/ GHz). Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL design tool. Rev. B Page 6 of 38

8 TIMING CHARACTERISTICS AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V VP = VVCO 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = V, RSET = 5. kω, dbm referred to 5 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Write Timing Parameter Limit Unit Description fclk 5 MHz max Serial peripheral interface CLK frequency t ns min LE setup time t2 5 ns min DATA to CLK setup time t3 5 ns min DATA to CLK hold time t4 ns min CLK high duration t5 ns min CLK low duration t6 5 ns min CLK to LE setup time t7 2 (or 2/fPFD, whichever is longer) ns min LE pulse width Write Timing Diagram t 4 t 5 CLK t 2 t 3 DATA DB3 (MSB) DB3 DB3 ( BIT C4) DB2 ( BIT C3) DB ( BIT C2) DB (LSB) ( BIT C) t 7 LE t t Figure 2. Write Timing Diagram Rev. B Page 7 of 38

9 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter Rating VRF, DVDD, AVDD to GND, 2.3 V to +3.6 V AVDD to DVDD.3 V to +.3 V VP, VVCO to GND.3 V to +5.8 V CPOUT to GND.3 V to VP +.3 V Digital Input/Output Voltage to GND.3 V to DVDD +.3 V Analog Input/Output Voltage to GND.3 V to AVDD +.3 V REFINA, REFINB to GND.3 V to AVDD +.3 V REFINA to REFINB ±2. V Operating Temperature Range 4 C to +85 C Storage Temperature Range 65 C to +25 C Maximum Junction Temperature 5 C θja, Thermal Impedance Paddle 27.3 C/W Soldered to GND Reflow Soldering Peak Temperature 26 C Time at Peak Temperature 4 sec Electrostatic Discharge (ESD) Charged Device Model V Human Body Model 25 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The is a high performance RF integrated circuit with an ESD rating of 2.5 kv and is ESD sensitive. Take proper precautions for handling and assembly. TRANSISTOR COUNT The transistor count for the is 3,665 (CMOS) and 324 (bipolar). ESD CAUTION GND = A GND = SD GND = A GNDRF = A GNDVCO = CP GND = V. 2 Do not connect VRF to DVDD. Rev. B Page 8 of 38

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS C REG 2 SD GND MUXOUT REF IN A REF IN B DV DD PDB RF C REG CLK DATA LE CE AV DD 5 V P 6 CP OUT 7 CP GND 8 24 V BIAS 23 V REF 22 R SET 2 A GNDVCO 2 V TUNE 9 V REGVCO 8 A GNDVCO 7 V VCO A GND V RF RF OUT A+ RF OUT A A GNDRF RF OUT B A GNDRF AV DD TOP VIEW (Not to Scale) NOTES. THE EXPOSED PAD MUST BE CONNECTED TO A GND Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 2 DATA Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs) as the control bits. This input is a high impedance CMOS input. 3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the four LSBs. 4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the powerdown bits. Register contents are retained unless the supply voltages are removed. 5, 6 AVDD Analog Power Supply. This pin ranges from 3.5 V to 3.45 V. Connect decoupling capacitors to the analog ground plane as close to this pin as possible. AVDD must have the same value as DVDD. 6 VP Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground plane as close to this pin as possible. 7 CPOUT Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the internal VCO. 8 CPGND Charge Pump Ground. This output is the ground return pin for CPOUT. 9 AGND Analog Ground. Ground return pin for AVDD. VRF Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin as possible. VRF must have the same value as AVDD. Do not connect VRF to DVDD. RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin. 2 RFOUTA Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin. 3, 5 AGNDRF RF Output Stage Ground. Ground return pins for the RF output stage. 4 RFOUTB Auxiliary VCO Output. The 2 VCO output is available at this pin. 7 VVCO Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. For best performance, this supply must be clean and have low noise. 8, 2 AGNDVCO VCO Ground. Ground return path for the VCO. 9 VREGVCO VCO Compensation Node. Place decoupling capacitors to the ground plane as close to this pin as possible. Connect this pin directly to VVCO. 2 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT output voltage. The input capacitance of this pin is 9 pf. 22 RSET No Connection. Charge pump bias resistance is internal. Rev. B Page 9 of 38

11 Pin No. Mnemonic Description 23 VREF Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground plane as close to this pin as possible. 24 VBIAS Reference Voltage. Connect a nf decoupling capacitor to the ground plane as close to this pin as possible. 25, 32 CREG, CREG2 Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal voltage of.8 V. Decoupling capacitors of nf connected to AGND are required for these pins. 26 PDBRF RFOUTA Power-Down. A logic low on this pin powers down the RFOUTA± outputs only. This power-down function is also software controllable. Do not leave this pin floating. 27 DVDD Digital Power Supply. This pin must be at the same voltage as AVDD. Do not connect to VRF. Place decoupling capacitors to the ground plane as close to this pin as possible. 28 REFINB Complementary Reference Input. If unused, ac couple this pin to AGND. 29 REFINA Reference Input. 3 MUXOUT Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the scaled reference frequency to be externally accessible. 3 SDGND Digital Σ-Δ Modulator Ground. Pin 3 is the ground return path for the Σ-Δ modulator. EPAD Exposed Pad. The exposed pad must be connected to AGND. Rev. B Page of 38

12 TYPICAL PERFORMANCE CHARACTERISTICS PHASE NOISE (dbc/hz) 9 3 PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 7. Open-Loop VCO Phase Noise, 8. GHz PHASE NOISE (dbc/hz) 9 3 PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 5. Open-Loop VCO Phase Noise, 5. GHz Figure 8. Open-Loop VCO Phase Noise,. GHz PHASE NOISE (dbc/hz) 9 3 PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 9. Open-Loop VCO Phase Noise, 3.6 GHz Rev. B Page of 38

13 PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers, VCO = 3.4 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 3. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Divide by 2, VCO = 3.4 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz 274- PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers, VCO = 5. GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 4. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Divide by 2, VCO = 5. GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz 274- PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 2. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers, VCO = 6.8 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 5. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Divide by 2, VCO = 6.8 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz Rev. B Page 2 of 38

14 PHASE NOISE (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 6. Closed-Loop Phase Noise, RFOUTB = 6.8 GHz, 2 VCO, VCO = 3.4 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz OUTPUT POWER (dbm) FREQUENCY (GHz) 4 C +25 C +85 C Figure 9. Output Power vs. Frequency, RFOUTA+/RFOUTA (7.5 nh Inductors, pf Bypass Capacitors, Board Losses De-Embedded) SECOND HARMONIC (RF OUT A 2) THIRD HARMONIC (RF OUT A 3) PHASE NOISE (dbc/hz) 9 3 POWER (dbc) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 7. Closed-Loop Phase Noise, RFOUTB = GHz, 2 VCO, VCO = 5. GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz Figure 2. RFOUTA+/RFOUTA Harmonics vs. Frequency (7.5 nh Inductors, pf Bypass Capacitors, Board Losses De-Embedded) 8 6 RF OUT A FREQUENCY (GHz) PHASE NOISE (dbc/hz) 9 3 POWER (dbm) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 8. Closed-Loop Phase Noise, RFOUTB = 3.6 GHz, 2 VCO, VCO = 6.8 GHz, fpfd = 6.44 MHz, Loop Bandwidth = 2 khz FREQUENCY (GHz) Figure 2. RFOUTA+/RFOUTA Power vs. Frequency ( nh Inductors, pf Bypass Capacitors, Board Measurement) Rev. B Page 3 of 38

15 8 4 C +25 C +85 C.5.45 RMS JITTER (ps) khz TO 2MHz RMS JITTER (ps) 2kHz TO 2MHz 6.4 OUTPUT POWER (dbm) RMS JITTER (ps) FREQUENCY (GHz) Figure 22. Output Power vs. Frequency, RFOUTB ( pf Bypass Capacitor De-Embedded) VCO FEEDTHROUGH (dbm) 4 C +25 C C FREQUENCY (GHz) Figure 23. VCO Feedthrough at RFOUTB (De-Embedded) vs. Fundamental VCO Frequency POWER (dbm) FREQUENCY (GHz) Figure 24. Wideband Spectrum, RFOUTB, VCO = 6.8 GHz, RFOUTB Enabled, RFOUTA+/RFOUTA Disabled (Board Measurement) OUTPUT FREQUENCY (GHz) Figure 25. RMS Jitter vs. Output Frequency, fpfd = 6.44 MHz, Loop Filter = 2 khz Figure 26. PFD Spur Amplitude vs. RFOUTA+/RFOUTA Output Frequency; fpfd = 6.44 MHz, fpfd = 3.72 MHz, and fpfd = 5.36 MHz; Loop Filter = 2 khz NOISE AND SPUR POWER (dbc/hz) PFD SPUR AMPLITUDE (dbc) PFD = 5.36MHz PFD = 3.72MHz PFD = 6.44MHz RF OUT A+/RF OUT A OUTPUT FREQUENCY(GHz) 7 k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 27. Fractional-N Spur Performance, GSM8 Band, RFOUTA+ = 55.2 MHz, REFIN = MHz, fpfd = 6.44 MHz, Output Divide by 4 Selected, Loop Filter Bandwidth = 2 khz, Channel Spacing = 2 khz Rev. B Page 4 of 38

16 NOISE AND SPUR POWER (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 28. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ = 23.5 MHz, REFIN = MHz, fpfd = 6.44 MHz, Output Divide by 2 Selected, Loop Filter Bandwidth = 2 khz, Channel Spacing = 2 khz NOISE AND SPUR POWER (dbc/hz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 3. Fractional-N Spur Performance, RFOUTA+ = 5.8 GHz, REFIN = MHz, fpfd = 6.44 MHz, Output Divide by 2 Selected, Loop Filter Bandwidth = 2 khz, Channel Spacing = 2 khz NOISE AND SPUR POWER (dbc/hz) FREQUENCY (GHz) k k k M M M FREQUENCY OFFSET FROM CARRIER (Hz) Figure 29. Fractional-N Spur Performance, RFOUTA+ = 2.59 GHz, REFIN = MHz, fpfd = 6.44 MHz, Output Divide by 2 Selected, Loop Filter Bandwidth = 2 khz, Channel Spacing = 2 khz TIME (ms) Figure 3. Lock Time for 25 MHz Jump from 45 MHz to 44 MHz, Loop Bandwidth = 2 khz Rev. B Page 5 of 38

17 CIRCUIT DESCRIPTION REFERENCE INPUT Figure 32 shows the reference input stage. The reference input can accept both single-ended and differential signals. Use the reference mode bit (Register 4, DB9) to select the signal. To use a differential signal on the reference input, program this bit high. In this case, SW and SW2 are open, SW3 and SW4 are closed, and the current source that drives the differential pair of transistors switches on (see Figure 32). The differential signal is buffered, and it is provided to an emitter coupled logic (ECL) to CMOS converter. When a single-ended signal is used as the reference, connect the reference signal to REFINA and program Bit DB9 in Register 4 to. In this case, SW and SW2 are closed, SW3 and SW4 are open, and the current source that drives the differential pair of transistors switches off. Singleended mode results in lower integer boundary spurs. REF IN A REF IN B BIAS GENERATOR 2.5kΩ 2.5kΩ Figure 32. Reference Input Stage RF N DIVIDER The RF N divider allows a division ratio in the PLL feedback path. Determine the division ratio by the INT, FRAC, FRAC2, and MOD2 values that this divider comprises. FROM VCO OUTPUT/ OUTPUT DIVIDERS SW4 REFERENCE INPUT MODE RF N COUNTER N = INT + N COUNTER INT REG SW FRAC REG 85kΩ SW2 AV DD Figure 33. RF N Divider BUFFER SW3 TO R COUNTER MULTIPLEXER ECL TO CMOS BUFFER FRAC + MOD THIRD-ORDER FRACTIONAL INTERPOLATOR FRAC2 VALUE FRAC2 MOD2 MOD2 VALUE TO PFD Rev. B Page 6 of 38 INT, FRAC, MOD, and R Counter Relationship The INT, FRAC, FRAC2, MOD, and MOD2 values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the PFD frequency (fpfd). For more information, see the RF Synthesizer A Worked Example section. Calculate the VCO output frequency (VCOOUT) by VCOOUT = fpfd N () where: VCOOUT is the output frequency of the external VCO voltage controlled oscillator (without using the output divider). fpfd is the frequency of the phase frequency detector. N is the desired value of the feedback counter, N. Calculate fpfd by fpfd = REFIN [( + D)/(R ( + T))] (2) where: REFIN is the reference input frequency. D is the REFIN doubler bit. R is the preset divide ratio of the binary -bit programmable reference counter ( to 23). T is the REFIN divide by 2 bit ( or ) N comprises FRAC2 FRAC N INT MOD2 MOD (3) where: INT is the 6-bit integer value (23 to 32,767 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler). FRAC is the numerator of the primary modulus ( to 6,777,25). FRAC2 is the numerator of the 4-bit auxiliary modulus ( to 6,383). MOD2 is the programmable, 4-bit auxiliary fractional modulus (2 to 6,383). MOD is a 24-bit primary modulus with a fixed value of 2 24 = 6,777,26. This calculation results in a very fine frequency resolution with no residual frequency error. To apply this formula, take the following steps:. Calculate N by dividing VCOOUT/fPFD. 2. The integer value of this number forms INT. 3. Subtract this value from the full N value. 4. Multiply the remainder by The integer value of this number forms FRAC. 6. Calculate MOD2 based on the channel spacing (fchsp) by MOD2 = fpfd/gcd(fpfd, fchsp) (4) where: fchsp is the desired channel spacing frequency. GCD(fPFD, fchsp) is the greatest common divisor of the PFD frequency and the channel spacing frequency.

18 7. Calculate FRAC2 by the following equation: FRAC2 = [(N INT) 2 24 FRAC)] MOD2 (5) The FRAC2 and MOD2 fraction result in outputs with zero frequency error for channel spacings when fpfd/gcd(fpfd, fchsp) = MOD2 < 6,383 (6) where: fpfd is the frequency of the phase frequency detector. fchsp is the desired channel spacing. GCD is a greatest common divisor function. If zero frequency error is not required, the MOD and MOD2 denominators operate together to create a 38-bit resolution modulus. INT N Mode When FRAC and FRAC2 are, the synthesizer operates in integer-n mode. R Counter The -bit R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from to 23 are allowed. PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 34 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element (INT =.6 ns, FRAC = 2.6 ns) that sets the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and provides a consistent reference spur level. Set the phase detector polarity to positive on this device because of the positive tuning of the VCO. HIGH +IN HIGH IN D U CLR Q CLR2 D2 Q2 U2 UP DELAY DOWN U3 CHARGE PUMP Figure 34. PFD Simplified Schematic CP MUXOUT AND LOCK DETECT The output multiplexer on the allows the user to access various internal points on the chip. The M3, M2, and M bits in Register 4 control the state of MUXOUT. Figure 35 shows the MUXOUT section in block diagram form. THREE-STATE OUTPUT DV DD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT MUX Figure 35. MUXOUT Schematic DV DD DGND MUXOUT INPUT SHIFT REGISTERS The digital section includes a -bit R counter, a 6-bit RF integer-n counter, a 24-bit FRAC counter, a 4-bit auxiliary fractional counter, and a 4-bit auxiliary modulus counter. Data clocks into the 32-bit shift register on each rising edge of CLK. The data clocks in MSB first. Data transfers from the shift register to one of 3 latches on the rising edge of LE. The state of the four control bits (C4, C3, C2, and C) in the shift register determines the destination latch. As shown in Figure 2, the four LSBs are DB3, DB2, DB, and DB. The truth table for these bits is shown in Table 5. Figure 39 and Figure 4 summarize the programming of the latches. Table 5. Truth Table for the C4, C3, C2, and C Control Bits Control Bits C4 C3 C2 C Register Register Register Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register Register Register Rev. B Page 7 of 38

19 PROGRAM MODES Table 5 and Figure 39 through Figure 53 show how the program modes must be set up in the. The following settings in the are double buffered: main fractional value (FRAC), auxiliary modulus value (MOD2), auxiliary fractional value (FRAC2), reference doubler, reference divide by 2 (RDIV2), R counter value, and charge pump current setting. Two events must occur before the uses a new value for any of the double buffered settings. First, the new value must latch into the device by writing to the appropriate register, and second, a new write to Register must be performed. For example, to ensure that the modulus value loads correctly, every time that the modulus value updates, Register must be written to. The RF divider select in Register 6 is also double buffered, but only if DB4 of Register 4 is high. VCO The VCO core in the consists of four separate VCOs, each of which uses 256 overlapping bands, which allows the device to cover a wide frequency range without large VCO sensitivity (KV) and without resultant poor phase noise and spurious performance. The correct VCO and band are chosen automatically by the VCO and band select logic whenever Register is updated and automatic calibration is enabled. The VCO VTUNE is disconnected from the output of the loop filter and is connected to an internal reference voltage. The R counter output is used as the clock for the band select logic. After band selection, normal PLL action resumes. The nominal value of KV is 5 MHz/V when the N divider is driven from the VCO output, or the KV value is divided by D. D is the output divider value if the N divider is driven from the RF output divider (chosen by programming Bits[D23:D2] in Register 6). The VCO shows variation of KV as the tuning voltage, VTUNE, varies within the band and from band to band. For wideband applications covering a wide frequency range (and changing output dividers), a value of 5 MHz/V provides the most accurate KV, because this value is closest to the average value. Figure 36 shows how KV varies with fundamental VCO frequency along with an average value for the frequency band. Users may prefer this figure when using narrow-band designs. VCO SENSITIVITY, K V (MHz/V) FREQUENCY (GHz) Figure 36. VCO Sensitivity, KV vs. Frequency OUTPUT STAGE The RFOUTA+ and RFOUTA pins of the connect to the collectors of an NPN differential pair driven by buffered outputs of the VCO, as shown in Figure 37. In this scheme, the contains internal 5 Ω resistors connected to the VRF pin. To optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable using Bits[D2:D] in Register 6. Four current levels can be set. These levels give approximate output power levels of 4 dbm, dbm, +2 dbm, and +5 dbm, respectively. Levels of 4 dbm, dbm, +2 dbm can be achieved using a 5 Ω resistor to VRF and ac coupling into a 5 Ω load. A +5 dbm level requires an external shunt inductor to VRF. Note that an inductor has a narrower operating frequency than a 5 Ω resistor. For accurate power levels, refer to the Typical Performance Characteristics section. Add an external shunt inductor to provide higher power levels; however, this is less wideband than the internal bias only. Terminate the unused complementary output with a circuit similar to the used output. VCO AVERAGE VCO SENSITIVITY BUFFER/ DIVIDE BY /2/4/8/ 6/32/64 Figure 37. Output Stage LINEAR TREND LINE The doubled VCO output (6.8 GHz to 3.6 GHz) is available on the RFOUTB pin, which can be ac-coupled to the next circuit. 5Ω V RF V RF 5Ω RF OUT A+ RF OUT A VCO MUX RF OUT B Figure 38. Output Stage Rev. B Page 8 of 38

20 Another feature of the is that the supply current to the RFOUTA+/RFOUTA output stage can shut down until the achieves lock as measured by the digital lock detect circuitry. The mute till lock detect (MTLD) bit (Bit DB) in Register 6 enables this function. RFOUTB directly connects to the VCO, and it can be muted but only by using the RFOUTB bit (Bit DB) in Register 6. Table 6. Total IDD (RFOUTA± Refers to RFOUTA+/RFOUTA ) Divide By RFOUTA± Off RFOUTA± = 4 dbm RFOUTA± = dbm RFOUTA± = +2 dbm RFOUTA± = +5 dbm 5. V Supply (IVCO and IP) 78 ma 78 ma 78 ma 78 ma 78 ma 3.3 V Supply (AIDD, DIDD, IRF) 79.8 ma.3 ma.9 ma 22.7 ma 32.8 ma ma. ma 2.6 ma 3.9 ma 4.9 ma ma 9.3 ma 3. ma 4.6 ma 52. ma ma 27. ma 37.8 ma 49.2 ma 59.7 ma ma 3.8 ma 42.7 ma 54. ma 64.6 ma ma 35.5 ma 46.5 ma 57.8 ma 68.4 ma ma 37.8 ma 48.9 ma 6. ma 7.8 ma For DI DD + AI DD (nominal 62 ma): DI DD = 5 ma (typical), AI DD (Pin 5) = 24 ma (typical), AI DD (Pin 6) = 23 ma (typical). Rev. B Page 9 of 38

21 REGISTER MAPS REGISTER AUTOCAL PRESCALER 6-BIT INTEGER VALUE (INT) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC PR N6 N5 N4 N3 N2 N N N9 N8 N7 N6 N5 N4 N3 N2 N C4() C3() C2() C() REGISTER 24-BIT MAIN FRACTIONAL VALUE (FRAC) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() REGISTER 2 4-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR 4-BIT AUXILIARY MODULUS VALUE (MOD2) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F M4 M3 M2 M M M9 M8 M7 M6 M5 M4 M3 M2 M C4() C3() C2() C() REGISTER 3 SD LOAD RESET PHASE RESYNC PHASE ADJUST 24-BIT PHASE VALUE (PHASE) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB SD PR PA P24 P23 P22 P2 P2 P9 P8 P7 P6 P5 P4 P3 P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P C4() C3() C2() C() REGISTER 4 MUXOUT DBR REFERENCE DOUBLER DBR RDIV2 -BIT R COUNTER DBR DOUBLE BUFF CURRENT SETTING DBR REF MODE MUX LOGIC PD POLARIT Y PD CP THREE- STATE COUNTER RESET DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M3 M2 M RD2 RD R R9 R8 R7 R6 R5 R4 R3 R2 R D CP4 CP3 CP2 CP U6 U5 U4 U3 U2 U C4() C3() C2() C() REGISTER 5 DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() REGISTER 6 GATED BLEED NEGATIVE BLEED FEEDBACK SELECT RF DIVIDER SELECT 2 CHARGE PUMP BLEED CURRENT MTLD RF OUT B RF OUT A+/ RF OUT A RF OUTPUT POWER DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB BL BL9 D3 D2 D D BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL D8 D7 D3 D2 D C4() C3() C2() C() DBR = DOUBLE BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER. 2DBB = DOUBLE BUFFERED BUFFERED BY A WRITE TO REGISTER WHEN BIT DB4 OF REGISTER 4 IS HIGH. Figure 39. Register Summary (Register to Register 6) Rev. B Page 2 of

22 REGISTER 7 LE SYNC LD CYCLE COUNT LOL MODE FRAC-N LD PRECISION LD MODE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB LE LD5 LD4 LOL LD3 LD2 LD C4() C3() C2() C() REGISTER 8 DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() REGISTER 9 VCO BAND DIVISION TIMEOUT AUTOMATIC LEVEL TIMEOUT SYNTHESIZER LOCK TIMEOUT DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC TL TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL AL5 AL4 AL3 AL2 AL SL5 SL4 SL3 SL2 SL C4() C3() C2() C() REGISTER ADC CLOCK DIVIDER ADC CONVERSION ADC ENABLE DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD AE2 AE C4() C3() C2() C() REGISTER DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB C4() C3() C2() C() REGISTER 2 RESYNC CLOCK DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB P6 P5 P4 P3 P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P C4() C3() C2() C() Figure 4. Register Summary (Register 7 to Register 2) Rev. B Page 2 of 38

23 AUTOCAL PRESCALER 6-BIT INTEGER VALUE (INT) DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB AC PR N6 N5 N4 N3 N2 N N N9 N8 N7 N6 N5 N4 N3 N2 N C4() C3() C2() C() AC PR PRESCALER 4/5 8/9 VCO AUTOCAL DISABLED ENABLED N6 N5... N5 N4 N3 N2 N INTEGER VALUE (INT)... NOT ALLOWED... NOT ALLOWED... NOT ALLOWED NOT ALLOWED Figure 4. Register INT MIN = 75 WITH PRESCALER = 8/ REGISTER Control Bits With Bits[C4:C] set to, Register is programmed. Figure 4 shows the input data format for programming this register. Reserved Bits[DB3:DB22] are reserved and must be set to. Automatic Calibration (AUTOCAL) Write to Register to enact (by default) the VCO automatic calibration, and to choose the appropriate VCO and VCO subband. Write to the AC bit (Bit DB2) to enable the automatic calibration, which is the recommended mode of operation. Set the AC bit (Bit DB2) to to disable the automatic calibration, which leaves the in the same band it was already in when Register is updated. Disable the automatic calibration only for fixed frequency applications, phase adjust applications, or very small (< khz) frequency jumps. Toggling automatic calibration (AUTOCAL) is also required when changing frequency. See the Frequency Update Sequence section for more information. Prescaler Value The dual modulus prescaler (P/P + ), along with the INT, FRACx, and MODx counters, determines the overall division ratio from the VCO output to the PFD input. The PR bit (Bit DB2) in Register sets the prescaler value. Operating at CML levels, the prescaler takes the clock from the VCO output and divides it down for the counters. It is based on a synchronous 4/5 core. When the prescaler is set to 4/5, the maximum RF frequency allowed is 7 GHz. The prescaler limits the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9, NMIN is Bit Integer Value The 6 INT bits (Bits[DB9:DB4]) set the INT value, which determines the integer part of the feedback division factor. The INT value is used in Equation 3 (see the INT, FRAC, MOD, and R Counter Relationship section). All integer values from 23 to 32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler, the minimum integer value is 75, and the maximum value is 65,535. Rev. B Page 22 of 38

24 24-BIT MAIN FRACTIONAL VALUE (FRAC) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F24 F23 F22 F2 F2 F9 F8 F7 F6 F5 F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F C4() C3() C2() C() F24 F23... F2 F MAIN FRACTIONAL VALUE (FRAC) DBR = DOUBLE BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER Figure 42. Register REGISTER Control Bits With Bits[C4:C] set to, Register is programmed. Figure 42 shows the input data format for programming this register. Reserved Bits[DB3:DB28] are reserved and must be set to. 24-Bit Main Fractional Value The 24 FRAC bits (Bits[DB27:DB4]) set the numerator of the fraction that is input to the Σ-Δ modulator. This fraction, along with the INT value, specifies the new frequency channel that the synthesizer locks to, as shown in the RF Synthesizer A Worked Example section. FRAC values from to (MOD ) cover channels over a frequency range equal to the PFD reference frequency. Rev. B Page 23 of 38

25 4-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR 4-BIT AUXILIARY MODULUS VALUE (MOD2) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB F4 F3 F2 F F F9 F8 F7 F6 F5 F4 F3 F2 F M4 M3 M2 M M M9 M8 M7 M6 M5 M4 M3 M2 M C4() C3() C2() C() F4 F3... F2 F FRAC2 WORD M4 M3... M2 M MODULUS VALUE (MOD2)... NOT ALLOWED... NOT ALLOWED DBR = DOUBLE BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER. Figure 43. Register 2 REGISTER 2 Control Bits With Bits[C4:C] set to, Register 2 is programmed. Figure 43 shows the input data format for programming this register. 4-Bit Auxiliary Fractional Value (FRAC2) The 4-bit auxiliary fractional value (Bits[DB3:DB8]) controls the auxiliary fractional word. FRAC2 must be less than the MOD2 value programmed in Register 2. 4-Bit Auxiliary Modulus Value (MOD2) The 4-bit auxiliary modulus value (Bits[DB7:DB4]) sets the auxiliary fractional modulus. Use MOD2 to correct any residual error due to the main fractional modulus. Rev. B Page 24 of 38

26 SD LOAD RESET PHASE RESYNC PHASE ADJUST 24-BIT PHASE VALUE (PHASE) DBR DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB SD PR PA P24 P23 P22 P2 P2 P9 P8 P7 P6 P5 P4 P3 P2 P P P9 P8 P7 P6 P5 P4 P3 P2 P C4() C3() C2() C() SD PR PA PHASE ADJUST DISABLED ENABLED PHASE RESYNC DISABLED ENABLED SD LOAD RESET P24 P23... P2 P PHASE VALUE (PHASE) ON REGISTER UPDATE DISABLED DBR = DOUBLE BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER. Figure 44. Register REGISTER 3 Control Bits With Bits[C4:C] set to, Register 3 is programmed. Figure 44 shows the input data format for programming this register. Reserved Bit DB3 is reserved and must be set to. SD Load Reset When writing to Register, the Σ-Δ modulator resets. For applications in which the phase is continually adjusted, this may not be desirable; therefore, in these cases, the Σ-Δ reset can be disabled by writing a to the SD bit (Bit DB3). Phase Resync To use the phase resynchronization feature, the PR bit (Bit DB29) must be set to. If unused, the bit can be programmed to. The phase resync timer must also be used in Register 2 to ensure that the resynchronization feature is applied after PLL has settled to the final frequency. If the PLL has not settled to the final frequency, phase resync may not function correctly. Resynchronization is useful in phased array and beam forming applications. It ensures repeatability of output phase when programming the same frequency. In phase critical applications that use frequencies requiring the output divider (<34 MHz), it is necessary to feed the N divider with the divided VCO frequency as distinct from the fundamental VCO frequency. This is achieved by programming the D3 bit (Bit DB24) in Register 6 to, which ensures divided feedback to the N divider. Phase resynchronization operates only when FRAC2 =. For resync applications, enable the SD load reset in Register 3 by setting DB3 to. Phase Adjust To adjust the relative output phase of the on each Register update, set the PA bit (Bit DB28) to. This feature differs from the resynchronization feature in that it is useful when adjustments to phase are made continually in an application. For this function, disable the VCO automatic calibration by setting the AC bit (Bit DB2) in Register to, and disable the SD load reset by setting the SD bit (Bit DB3) in Register 3 to. Note that phase resync and phase adjust cannot be used simultaneously. 24-Bit Phase Value The phase of the RF output frequency can adjust in 24-bit steps, from () to 36 (2 24 ). For phase adjust applications, the phase is set by (Phase Value/6,777,26) 36 When the phase value is programmed to Register 3, each subsequent adjustment of Register increments the phase by the value in this equation. Rev. B Page 25 of 38

27 MUXOUT DBR REFERENCE DOUBLER DBR RDIV2 -BIT R COUNTER DOUBLE BUFF CURRENT DBR SETTING DBR REF MODE MUX LOGIC PD POLARITY PD CP THREE- STATE COUNTER RESET DB3 DB3 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB2 DB2 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB DB M3 M2 M RD2 RD R R9 R8 R7 R6 R5 R4 R3 R2 R D CP4 CP3 CP2 CP U6 U5 U4 U3 U2 U C4() C3() C2() C() RD2 REFERENCE DOUBLER DISABLED ENABLED D DOUBLE BUFFERED REGISTER 6, [DB23:DB2] DISABLED ENABLED U6 REFIN SINGLE DIFF U COUNTER RESET DISABLED ENABLED REGISTER 4 Control Bits RD REFERENCE DIVIDE BY 2 DISABLED ENABLED R R9... R2 R R DIVIDER (R) M3 M2 M OUTPUT THREE-STATE OUTPUT DV DD DGND R DIVIDER OUTPUT N DIVIDER OUTPUT ANALOG LOCK DETECT DIGITAL LOCK DETECT DBR = DOUBLE BUFFERED REGISTER BUFFERED BY THE WRITE TO REGISTER. With Bits[C4:C] set to, Register 4 is programmed. Figure 45 shows the input data format for programming this register. Reserved Bits[DB3:DB3] are reserved and must be set to. MUXOUT The on-chip multiplexer (MUXOUT) is controlled by Bits[DB29:DB27]. For additional details, see Figure 45. When changing frequency, that is, writing Register, MUXOUT must not be set to N divider output or R divider output. If needed, enable these functions after locking to the new frequency. Reference Doubler Setting the RD2 bit (Bit DB26) to feeds the reference frequency signal directly to the -bit R counter, disabling the doubler. Setting this bit to multiplies the reference frequency by a factor of 2 before feeding it into the -bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of the reference frequency become active edges at the PFD input. CP4 CP3 CP2 CP I CP (ma) 5.kΩ Figure 45. Register 4 U4 U5 LDP.8V 3.3V PD POLARITY NEGATIVE POSITIVE The maximum allowable reference frequency when the doubler is enabled is MHz. RDIV2 Setting the RDIV2 bit (Bit DB25) to inserts a divide by 2, toggle flip-flop between the R counter and PFD, which extends the maximum reference frequency input rate. This function provides a 5% duty cycle signal at the PFD input. -Bit R Counter The -bit R counter divides the input reference frequency (REFIN) to produce the reference clock to the PFD. Division ratios range from to 23. Double Buffer The D bit (Bit DB4) enables or disables double buffering of the RF divider select bits (Bits[DB23:DB2]) in Register 6. The Program Modes section explains how double buffering works. Charge Pump Current Setting The CP4 to CP bits (Bits[DB3:DB]) set the charge pump current. Set this value to the charge pump current that the loop filter is designed with (see Figure 45). For the lowest spurs, the.9 ma setting is recommended. U3 U2 CP THREE-STATE DISABLED ENABLED POWER DOWN DISABLED ENABLED Rev. B Page 26 of 38