Phase frequency detector and charge pump SPECIFICATION
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1 Phase frequency detector and charge pump SPECIFICATION 1 FEATURES TSMC018 SiGe BiCMOS Input signals with low amplitude Low disbalance of output current High accuracy Supported foundries: TSMC, UMC, Global Foundries, SMIC, ihp, AMS, Vanguard, SilTerra 2 APPLICATION Phase-locked loop synthesizer 3 FUNCTIONAL DESCRIPTION Phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided erence oscillator signal and detects phase difference. Charge pump (CP) generates pulses for the loop filter. The structure consists of two types of PFD with CP: ECL and CMOS choosing by a bit PFD_TP. The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and erence oscillator signal with required value. LD_MP<1:0> and LD_ACR outputs set the lock monitoring period and the lock detector accuracy, respectively. The block is fabricated on TSMC018 SiGe BiCMOS technology. 4 STRUCTURE Figure 1: Phase frequency detector and charge pump structure. Ver. 1.1 August
2 Figure 2: ECL PFD and CP structure. Figure 3: ECL PFD and CP structure. Figure 4: Lock detector structure. Ver. 1.1 page 2 of 7
3 5 PIN DESCRIPTION Name Direction Description PFD ECL _i10u I PFD erence current 10 µa CP ECL _i10u I Charge pump erence current 10 µa CP CMOS _i20u I Charge pump erence current 20 µa ECT_to_CMOS_i10u I ECL/CMOS converter erence current 10 µa IN_N p IN_N n I PLL VCO divided signal differential input IN_R p IN_R n I PLL erence oscillator signal differential input PFD_EN I PFD enable/disable CP_EN I Charge pump enable/disable LD_EN I Lock detector enable/disable PFD_PLR I PFD polarity PFD_CC I PFD current consumption control PFD_TP I Charge pump type select: ECL/CMOS CP_OC<1:0> I Charge pump output current control PFD_MD<2:0> I Phase detector reset circuit control E2C_CC I ECL/CMOS converter current consumption control LD_MP<1:0> I Lock monitoring period control LD_ACR I Lock detector accuracy control CP_OUT O Charge pump output LI O Lock indicator output GND IO Ground VCC IO Supply voltage Ver. 1.1 page 3 of 7
4 6 LAYOUT DESCRIPTION Frequency-phase detector and charge pump dimensions are given in the table 1. Table 1: Blocks dimensions. Dimension Value Unit Height 270 µm Width 350 µm Figure 5: PFD and CP layout view. 1. Ground bus 2. Supply voltage bus 3. ECL PFD with filter capacitors 4. ECL CP with filter capacitors 5. CMOS PFD with filter capacitors 6. ECL CP with filter capacitors 7. ECL/CMOS converter of a erence oscillator signal 8. ECL/CMOS converter of VCO divided signal 9. Lock detector 10. ECL/CMOS converter of erence current source 11. Filter capacitors Ver. 1.1 page 4 of 7
5 7 OPERATING CHARACTERISTICS 7.1 TECHNICAL CHARACTERISTICS Technology TSMC018 SiGe Status Silicon proven Area mm ELECTRICAL CHARACTERISTICS CHARACTERISTICS IN ECL PFD&CP OPERATING MODE The values of electrical characteristics are specified for V cc = V и T = C. Typical values are at V сс = 3.15 V, T = +27 C, unless otherwise specified. Output current I out Parameter Symbol Condition Value min typ max Unit Supply voltage V CC V Operating temperature range T C Reference frequency F MHz Peak-to-peak voltage at For inputs IN A p, the differential input in p-p IN_N n, IN_R p, mv DC operating point V op IN_R n V сс 1.2 V сс V сс -0.4 V Preset Preset mа Preset Preset PFD reset time t rst Preset ns Lock monitoring period MP Preset T 1 = 64 T T µs F Supply current I Lock detector accuracy ACR Preset Preset ns Preset ma Preset cc Preset Stand-by current I stb na Input logic-level high V IH V 0.7V сс - сс For digital inputs 5 V Input logic-level low V IL V Note: Control signal PFD_TP is set to 0 in ECL PFD&CP operating mode. CP output current is set by the control signals PFD_TP and CP_OC. Table 2: Presets description Presets name Control signal values Notes Preset 1 PFD_TP = 0 CP_OC<1:0> = 00 Preset 2 PFD_TP = 0 CP_OC<1:0> = 01 Preset 3 PFD_TP = 0 CP_OC<1:0> = 10 Preset 4 PFD_TP = 0 CP_OC<1:0> = 11 CP output current control Ver. 1.1 page 5 of 7
6 Table 2 (continue) Presets name Control signal values Notes Preset 5 PFD_TP = 0 PFD_MD<2:0> = 0XX Preset 6 PFD_TP = 0 PFD_MD<2:0> = 1XX Preset 7 PFD_TP = 0 PFD_CC = 0 LD_EN = 0 Preset 8 PFD_TP = 0 PFD_CC = 1 LD_EN = 0 Preset 9 PFD_TP = 0 PFD_CC = 0 LD_EN = 1 Preset 10 LD_ACR = 0 Preset 11 LD_ACR = 1 PFD reset time control Operation mode when ECL PFD and CP extra current is disabled Operation mode when ECL PFD and CP extra current is enabled. Operation mode when ECL PFD and CP extra current is enabled. LD is enabled. Lock detector accuracy control CHARACTERISTICS IN CMOS PFD&CP OPERATING MODE The values of electrical characteristics are specified for V cc = V and T = C. Typical values are at V сс = 3.15 V, T = +27 C, unless otherwise specified. Parameter Symbol Condition Value min typ max Unit Supply voltage V CC V Operating temperature range T C Reference frequency F MHz Peak-to-peak voltage at A the differential input in p-p For inputs IN p, IN_N n, mv IN_R p, IN_R n DC operating point V op V сс 1.2 V сс V сс -0.4 V Preset Output current I out Preset Preset mа Preset PFD reset time t rst ns Lock monitoring period MP T 1 = 64 T T µs F Preset Lock detector accuracy ACR ns Preset Preset Supply current I cc ma Preset Stand-by current I stb na Input logic-level high V IH 0.7V сс - V сс V For digital inputs Input logic-level low V IL V Note: Control signal PFD_TP is set to 1 in CMOS PFD&CP operating mode. CP output current is set by the control signals CP_OC <1:0>. Ver. 1.1 page 6 of 7
7 Table 3: Presets description. Presets name Control signal values Notes Preset 1 PFD_TP = 0 CP_OC<1:0> = 00 Preset 2 Preset 3 PFD_TP = 0 PFD_TP = 0 CP_OC<1:0> = 01 CP_OC<1:0> = 10 CP output current control Preset 4 PFD_TP = 0 CP_OC<1:0> = 11 Preset 5 PFD_TP = 0 LD_EN = 0 Operation mode when a lock detector is disabled Preset 6 PFD_TP = 0 LD_EN = 1 Operation mode when a lock detector is enabled Preset 7 LD_ACR = 0 Preset 8 LD_ACR = 1 Lock detector accuracy control 8 DELIVERABLES IP contents: Schematic or NetList Layout or blackbox Extracted view (optional) GDSII DRC, LVS, antenna report Test bench with saved configurations (optional) Documentation Ver. 1.1 page 7 of 7
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2.5V LV-PECL Output Oscillator ICs OVERVIEW The 5036 series are 2.5V operation, differential LV-PECL output oscillator ICs. They support 50MHz to 400MHz 3rd overtone oscillation and 50MHz to 600MHz fundamental
PI6CX201A. 25MHz Jitter Attenuator. Features
Features PLL with quartz stabilized XO Optimized for MHz input/output frequency Other frequencies available Low phase jitter less than 30fs typical Free run mode ±100ppm Single ended input and outputs
IDT82V3010 FEATURES FUNCTIONAL BLOCK DIAGRAM T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS
T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS IDT82V3010 FEATURES Supports AT&T TR62411 Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interface Selectable reference inputs:
CLK1 GND. Phase Detector F VCO = F REF * (2 * M/R) VCO. P-Counter (14-bit) F OUT = F VCO / (2 * P) Programming Logic
PL611s-19 PL611s-19 FEATURES Designed for Very Low-Power applications Input Frequency, AC Coupled: o Reference Input: 1MHz to 125MHz o Accepts >0.1V input signal voltage Output Frequency up to 125MHz LVCMOS
Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED
Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com THIS PAGE INTENTIONALLY LEFT BLANK Features RF Bandwidth: 9.05 GHz to
CD74HC7046A, CD74HCT7046A
Data sheet acquired from Harris Semiconductor SCHS February 99 CD7HC706A, CD7HCT706A Phase-Locked Loop with VCO and Lock Detector [ /Title (CD7 HC70 6A, CD7 HCT70 6A) /Subject Phaseocked oop Features Center
T1/E1/OC3 WAN PLL WITH DUAL
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS IDT82V3012 FEATURES Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Supports ITU-T G.813
3V 10-Tap Silicon Delay Line DS1110L
XX-XXXX; Rev 1; 11/3 3V 1-Tap Silicon Delay Line General Description The 1-tap delay line is a 3V version of the DS111. It has 1 equally spaced taps providing delays from 1ns to ns. The series delay lines
MAPS Digital Phase Shifter 4-Bit, GHz. Features. Functional Schematic. Description. Pin Configuration 2. Ordering Information 1
MAPS-1146 4-Bit, 8. - 12. GHz Features 4 Bit 36 Coverage with LSB = 22.5 Integrated CMOS Driver Serial or Parallel Control Low DC Power Consumption Minimal Attenuation Variation over Phase Shift Range
Spread Spectrum Frequency Timing Generator
Spread Spectrum Frequency Timing Generator Features Maximized EMI suppression using Cypress s Spread Spectrum technology Generates a spread spectrum copy of the provided input Selectable spreading characteristics
SCG4540 Synchronous Clock Generators
SCG4540 Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features Phase Locked Output Frequency Control Intrinsically
74VHC4046 CMOS Phase Lock Loop
74VHC4046 CMOS Phase Lock Loop General Description The 74VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator
Recommended crystal unit/ resonator. Fundamental, Fundamental, 3rd overtone, SAW. 80 to A1N No 2.5. SAW 110 to B1N
2.5V LVDS Output Oscillator ICs OVERVIEW The 5037 series are 2.5V operation, LVDS output oscillator ICs. They support 80MHz to 400MHz 3rd overtone oscillation and 80MHz to 600MHz fundamental oscillation.
Features. n Ultra low current consumption n 2.7V to 5.5V operation n Selectable synchronous or asynchronous powerdown mode: I CC.
LMX2330L/LMX2331L/LMX2332L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2330L LMX2331L LMX2332L 2.5 GHz/510 MHz 2.0 GHz/510 MHz 1.2 GHz/510 MHz General Description The
ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET ICS663 Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled
HMC4069LP4E FREQUENCY DIVIDERS AND DETECTORS - SMT. Typical Applications. General Description. Functional Diagram
Typical Applications The HMC4069LPE is ideal for: Point-to-Point Radios Satellite Communication Systems Military Applications Sonet Clock Generation General Description Functional Diagram Features Ultra
DS Tap High Speed Silicon Delay Line
www.dalsemi.com FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances
DC PIR Controller Features Low stand-by current :