4-Channel GPS/GLONASS/Galileo/BeiDou/IRNSS/QZSS L1/L2/L3/L5 band RF Front End

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1 SPECIFICATION 1. FEATURES Single conversion super heterodyne receiver Four independent configurable channels, each includes preamplifier, image rejection mixer, IF filter, IFA, 2-bit ADC Signal bandwidth up to 31MHz supports GNSS high precision codes such as P-code in GPS or wideband E5 Galileo Dual adoptable AGC system (RF + IF) or programmable gain High dynamic range with 1dB compression point more than -3dBm Analog differential output with two options of voltage swing.2/.47vp-p and.4/.98vp-p (sine wave/noise) or 2-bit ADC digital output data Two independent fully integrated synthesizers with flexible LO and CLK frequencies selection ( A and B ) Embedded temperature sensor SPI interface with easy-to-use register map Individual status indicators of main subsystems (available in SPI registers) and cumulative status indicator (AOK, available both as a separate pin and in SPI registers) 2. APPLICATIONS GNSS based positioning systems GNSS based goniometric systems In-vehicle navigation systems GNSS based driverless car systems 3. OVERVIEW NT165 is a four-channel RF front end for a simultaneous reception of GPS/GLONASS/Galileo/BeiDou/IRNSS/QZSS Global Navigation Satellite System signals (GNSS) of various frequency bands L1, L2, L3, L5, E1, E5a, E5b, E6, B1, B2, B3. Galileo E5 band as well as BeiDou B1, B2, B3 (phase 3) band can be obtained as entire signal with two channels fed by the same LO and then restored in digital domain to true complex data. As a benefit one can discover wide possibilities of improving the positioning accuracy down to centimeter range without taking RTK technique. Each setting, including output signal frequency bandwidth, AGC options, mirror channel suppression option, etc., can be set for every channel individually. NT165 includes two fully independent frequency synthesizers. Channel#1 and channel#2 are supplied with LO signal generated in PLL A while PLL B is assigned for channels #3 and #4. For specific applications there is an option to feed all four channels with single LO source from PLL A. This powerful toolkit is accompanied with very simple and easy-to-use register map. All the functionality allows application of NT165 in high precision GNSS based positioning, goniometric, driverless car systems and related branches. Ver. 2. June 216

2 4. PINS DESCRIPTION # Name Description 1 GND Ground 2 GND Ground 3 RF2_GND 2 nd channel RF ground 4 5 RF2_GND 2 nd channel RF ground 6 RF2_IN 2 nd channel RF input 7 8 RF2_GND 2 nd channel RF ground 9 RF2_VCC 2 nd channel RF2 LDO output voltage 2.7V 1 MIX2_VCC 2 nd channel MIX2 LDO output voltage 2.7V 11 RS_GND Voltage and current reference source ground PLLA_GND A PLL ground 14 PLLA_VCC PLLA LDO output voltage 2.7V 15 PLLB_VCC PLLB LDO output voltage 2.7V PLLB_GND B PLL ground 18 REF_CUR External high-precision resistor connection 19 MIX3_VCC 3 rd channel MIX4 LDO output voltage 2.7V 2 RF3_VCC 3 rd channel RF3 LDO output voltage 2.7V RF3_GND 3 rd channel RF ground 23 RF3_IN 3 rd channel RF input RF3_GND 3 rd channel RF ground 26 RF3_GND 3 rd channel RF ground 27 GND Ground 28 GND Ground 29 GND Ground 3 GND Ground 31 RF4_GND 4 th channel RF ground RF4_GND 4 th channel RF ground 34 RF4_IN 4 th channel RF input RF4_GND 4 th channel RF ground 37 RF4_VCC 4 th channel RF4 LDO output voltage 2.7V 38 MIX4_VCC 4 th channel MIX4 LDO output voltage 2.7V 39 RF4_GND 4 th channel RF ground 4 TEST Test output; should be opened RO_GND Reference oscillator ground 43 REF_IN Reference frequency input 44 RO_VCC RO LDO output voltage 2.7V V_VCC Supply voltage 3V Ver. 2. page 2 of 18

3 # Name Description IFA4_GND 4 th channel IFA ground 49 IFA4_VCC 4 th channel IFA4 LDO output voltage 2.7V 5 51 IFB4_GND 4 th channel IF buffer & ADC ground 52 IF4_OUTp/MAGN 4 th channel analog output true; 2-bit ADC digital output data MAGN 53 IF4_OUTn/SIGN 4 th channel analog output complement; 2-bit ADC digital output data SIGN 54 IFB4_VCC 4 th channel IFB4 LDO output supply 2.7V 55 IFB4_GND 4 th channel IF buffer & ADC ground 56 GND Ground 57 GND Ground 58 IFB3_GND 3 rd channel IF buffer & ADC ground 59 IFB3_VCC 3 rd channel IFB3 LDO output supply 2.7V 6 IF3_OUTn/SIGN 3 rd channel analog output complement; 2-bit ADC digital output data SIGN 61 IF3_OUTp/MAGN 3 rd channel analog output true; 2-bit ADC digital output data MAGN IFB3_GND 3 rd channel IF buffer & ADC ground 64 IFA3_VCC 3 rd channel IFA3 LDO output voltage 2.7V IFA3_GND 3 rd channel IFA ground 67 CLK_GND CLK management unit ground CLK_VCC CLK LDO output voltage 2.7V 7 CLK_OUT1 Clock frequency analog output true; CMOS output 71 CLK_OUT2 Clock frequency analog output complement CLK_GND CLK management unit ground 74 CLK_GND CLK management unit ground IFA2_GND 2 nd channel IFA ground 77 IFA2_VCC 2 nd channel IFA2 LDO output voltage 2.7V IFB2_GND 2 nd channel IF buffer & ADC ground 8 IF2_OUTp/MAGN 2 nd channel analog output true; 2-bit ADC digital output data MAGN 81 IF2_OUTn/SIGN 2 nd channel analog output complement; 2-bit ADC digital output data SIGN 82 IFB2_VCC 2 nd channel IFB2 LDO output voltage 2.7V 83 IFB2_GND 2 rd channel IF buffer & ADC ground 84 GND Ground 85 GND Ground 86 IFB1_GND 1 st channel IF buffer & ADC ground 87 IFB1_VCC 1 st channel IFB1 LDO output voltage 2.7V 88 IF1_OUTn/SIGN 1 st channel analog output complement; 2-bit ADC digital output data SIGN Ver. 2. page 3 of 18

4 # Name Description 89 IF1_OUTp/MAGN 1 st channel analog output true; 2-bit ADC digital output data MAGN 9 91 IFB1_GND 1 st channel IF buffer & ADC ground 92 IFA1_VCC 1 st channel IFA1 LDO output voltage 2.7V IFA1_GND 1 st channel IFA ground 95 CSN SPI chip select (active low) 96 SCLK SPI clock input 97 MOSI SPI data input 98 MISO SPI data output 99 AOK Cumulative status indicator: 1 valid fail 1 RF1_GND 1 st channel down converter ground 11 MIX1_VCC 1 st channel MIX1 LDO output voltage 2.7V 12 RF1_VCC 1 st channel RF1 LDO output voltage 2.7V RF1_GND 1 st channel RF ground 15 RF1_IN 1 st channel RF input RF1_GND 1 st channel RF ground 18 RF1_GND 1 st channel RF ground 19 GND Ground 11 GND Ground Ver. 2. page 4 of 18

5 5. APPLICATION SCHEMATIC Figure 1: NT165 Application schematic Table 1: External component description Component Nominal value Tolerance Notes С1 1.5 pf Matching network capacitor for L1 band ±5% -- pf Matching network capacitor for L2 band С2 1µF ±2% Supply voltage filter capacitor С3 1µF ±2% Supply voltage filter capacitor С4 1µF ±2% Supply voltage filter capacitor С5 1µF ±2% Supply voltage filter capacitor С6 1µF ±2% Supply voltage filter capacitor С7 1µF ±2% Supply voltage filter capacitor С8 1.5 pf Matching network capacitor for L1 band ±5% -- pf Matching network capacitor for L2 band С9 1.5 pf Matching network capacitor for L1 band ±5% -- pf Matching network capacitor for L2 band Ver. 2. page 5 of 18

6 Component Nominal value Tolerance Notes C1 1µF ±2% Supply voltage filter capacitor С11 1µF ±2% Supply voltage filter capacitor С12* 33pF ±2% Blocking capacitor С13 1µF ±2% Supply voltage filter capacitor C14 1nF ±2% Supply voltage filter capacitor С15 1µF ±2% Supply voltage filter capacitor С16 1µF ±2% Supply voltage filter capacitor С17 1µF ±2% Supply voltage filter capacitor С18 1µF ±2% Supply voltage filter capacitor С19 1µF ±2% Supply voltage filter capacitor С2 1µF ±2% Supply voltage filter capacitor С21 1µF ±2% Supply voltage filter capacitor C22 1µF ±2% Supply voltage filter capacitor C23 1µF ±2% Supply voltage filter capacitor C24 1µF ±2% Supply voltage filter capacitor C25 1µF ±2% Supply voltage filter capacitor C26 1µF ±2% Supply voltage filter capacitor C pf Matching network capacitor for L1 band ±5% -- pf Matching network capacitor for L2 band L1 8.2 nh (Q 4) Matching network inductor for L1 band ±2% 1 nh (Q 4) Matching network inductor for L2 band L2 8.2 nh (Q 4) Matching network inductor for L1 band ±2% 1 nh (Q 4) Matching network inductor for L2 band L3 8.2 nh (Q 4) Matching network inductor for L1 band ±2% 1 nh (Q 4) Matching network inductor for L2 band L4 12 Ω / 1 MHz ±2% Supply voltage filter inductor L5 8.2 nh (Q 4) Matching network inductor for L1 band ±2% 1 nh (Q 4) Matching network inductor for L2 band R kω ±1% High precision resistor R2* 2 Ω ±5% Load resistor R3* 2 Ω ±5% Load resistor R4* 2 Ω ±5% Load resistor R5* 2 Ω ±5% Load resistor Note: * defined depending on PCB construction and purpose 5.1 SERIAL INTERFACE DESCRIPTION NT165 can be configured with standard 4-wire SPI. In addition special pin "AOK" (cumulative status indicator) for tracking unexpected system failure is available. User register map is split up into five parts according to functionality: System Info General settings and status CLK settings Channel settings and status (separate for each channel) PLL settings and status (separate for each PLL) Available settings and statuses are listed below. Full register map or/and special firmware may be provided by NTLab if requested. Ver. 2. page 6 of 18

7 5.1.1 SYSTEM INFO ID number, release GENERAL SETTINGS AND STATUS Mode (standby, synthesizer only, active) TCXO frequency setting (1MHz, 24.84MHz). If other frequency is used, please, contact to NTLab for a solution. LO source (PLL A for channels#1&2 + PLL B for channels#3&4; PLL A for all channels) LPF auto-calibration system execute and status Channel# to be monitored for status (ch#1, ch#2, ch#3, ch#4) Temperature measurement mode (single, continuous) Temperature measurement system execute AOK indicator configuration General Status (AOK, temperature) Selected channel status (RF AGC indicator, RF Gain, IF Gain) CLK SETTINGS CLK C divider ratio (:8, :9 :31) CLK frequency source (PLL A, PLL B ) CLK type (LVDS, CMOS) CLK amplitude (23mV, 34mV, 46mV, 57mV if LVDS type; 1.8V, 2.4V, 2.7V, VCC if CMOS type) CLK output DC level if LVDS type (1.55V, 2.1V, 2.4V, 2.7V) CHANNEL SETTINGS Channel enable Channel GNSS (LSB or USB) IF pass band (7bits, 15.MHz 31.MHz) Output data interface (analog differential output, 2-bit ADC output) IFA output DC level (1.5V, 1.7V, 1.9V, 2V) RF GC mode (manual, auto) IFA GC mode (manual, auto) RF AGC thresholds (3 bits for upper threshold, 3 bits for lower threshold) IF AGC threshold (2mV, 4mV) RF gain in manual mode (4 bits) IF gain in manual mode (1 bits) Channel output load 2 Ohm external resistor (yes, no) ADC output logic-level high (1.8V, 2.4V, 2.7V, VCC) ADC type (asynchronous, clocked by rising edge, clocked by falling edge) PLL SETTINGS AND STATUS PLL enable Frequency band (L1 or L2/L3/L5) N divider ratio (N<8:>) R divider ratio (R<3:>) PLL tuning system execute Status (VCO input voltage comparator, Lock indicator) Ver. 2. page 7 of 18

8 6. OPERATING CHARACTERISTICS 6.1 TECHNICAL CHARACTERISTICS Technology AMS CMOS.35 um Status silicon proven Area 37.5 mm DC ELECTRICAL CHARACTERISTICS The values of electrical characteristics are specified for V cc = 2.85 V to 3.3 V, T A = C. Typical values are at V cc = 3. V, T A =+25 C, unless otherwise specified. Parameter Symbol Condition Value min typ. max Unit Supply voltage V cc V Die temperature measurement range T j C Die temperature measurement accuracy T j - - ±5 - C Mode 1.1/Mode / Mode 2.1/Mode /49. - Current consumption I cc Mode 3.1/Mode /56. - ma Mode 4.1/Mode / Mode 5.1/Mode / Shutdown mode ua Input logic-level low V IL V Input logic-level high V IH -.8V cc - V cc V Output logic-level low V OL I LOAD = 1uA -.4 V Output logic-level high V OH I LOAD = 1uA V cc V cc V Preset 1-1.8/1.7 - Output logic-level high Preset 2-2.4/2.3 - V (ADC output) OH_ADC I LOAD = ma/2ma Preset 3-2.7/2.6 - V Preset 4 - V cc /V cc Output logic-level low (ADC output) V OL_ADC I LOAD =2mA -.4 V Preset IFA output DC level V DC_IFA Preset Preset V Preset Preset Clock output DC level V DC_CLK Preset Preset V Preset Modes: 1. 1 channel (L1 or L2/L3/L5 PLL "A") 2. 2 channels (2 L1 band or 2 L2/L3/L5 PLL "A") 3. 2 channels (1 L1 PLL "A" + 1 L2/L3/L5 PLL "B") 4. 4 channels (4 L1 or L2/L3/L5 PLL "A") 5. 4 channels (2 L1 PLL "A" + 2 L2/L3/L5 PLL "B") *.1. analog differential output, IF AGC threshold = 2mV *.2. 2-bit ADC output, V OH_ADC = 2.7V, C LOAD = 5pF Ver. 2. page 8 of 18

9 6.3 AC ELECTRICAL CHARACTERISTICS The values of electrical characteristics are specified for V cc = 2.85 V to 3.3 V, T A = C. Typical values are at V cc = 3. V, T A =+25 C, unless otherwise specified. Parameter Symbol Condition Value min typ. max Unit Overall Input frequency range F IN L1 band L2/L3/L5 band MHz Reference frequency range F REF - 5 1/ MHz Noise figure NF RF_IN Note 3 L1 band L2/L3/L5 band db 1 db compression point P 1dB_RF_IN Note Note dbm Total gain G MAX db Channel Isolation Ch ISO db Input VSWR VSRW RF_IN 5 Ω L1 band L2/L3/L5 band RF AGC range G RF db IF AGC range G IF db Preamp&MIX Image rejection IR db RF (Preamp&Mixer) max gain G MAX_RF db RF (Preamp&Mixer) min gain G MIN_RF db Preamp gain step G STEP_MIX db LPF&IFA Output frequency range F IF Tunable, assured/not guaranteed 3-31/4 MHz LPF 3dB cut-off frequency F cut_lpf Tunable, assured/not guaranteed 15/11-31/4 MHz IF (LPF&IFA) max gain G MAX_IF db IF (LPF&IFA) min gain G MIN_IF db Sinusoidal/noise signal peakto-peak voltage at the V m Note 4 Preset 1-2/47 - differential linear outputs Preset 2-4/98 - mv Output resistance R out Analog differential output Ohm Group time delay ripple ΔT GD F IF = 3 9MHz, F cut_lpf = 18 MHz - <2 - F IF = 6 18MHz, F cut_lpf = 25 MHz - <15 - ns LPF 3dB cut-off frequency Gain ripple G IR excluded db ADC Resolution R ADC bit Preset 1-1.8/1.7 - ADC output signal level V OH_ADC I LOAD = ma/2ma Preset 2-2.4/2.3 - Preset 3-2.7/2.6 - V Preset 4 - V cc /V cc Synthesizer Reference frequency F REF - 5 1/ MHz Reference input level REF IN Sine or triangle wave Vp-p LO frequency range F LO L1 band L2/L3/L5 band MHz Ver. 2. page 9 of 18

10 Parameter Symbol Condition Value min typ. max Unit VCO frequency range F VCO L1 band L2/L3/L5 band MHz VCO to PFD frequency integer-valued division ratio N Multiple of VCO to CLK frequency integer-valued division ratio C Multiple of Reference frequency to PFD frequency integer-valued R division ratio F PFD= khz F LO = MHz F PFD= 8.28 khz LO phase noise PN LO F LO = MHz F PFD= 1 khz dbc/hz F LO = 159 MHz F PFD= 5 khz F LO = 1235 MHz LO RMS jitter J RMS Integrated BW = 25 MHz ps F LO = MHz Clock frequency range (tunable) Peak-to-peak voltage at the differential clock outputs F CLK V CLK F LO = MHz F LO = 159 MHz F LO = 1235 MHz Preset 1-23/46 - R LOAD = 2/-- Ohm, F CLK < 5 MHz, C load < 1pF Preset 2-34/69 - Preset 3-45/92 - Preset 4-56/113 - PFD frequency range F CMP - 1 1/ MHz Note 1: RFAGC = min gain, IFAGC = min gain Note 2: RFAGC = max gain, IFAGC = min gain Note 3: RFAGC = max gain, IFAGC gain > 3 db Note 4: RMS value measured. V p-p sin = V RMS *2 2; V p-p noise = V RMS *6.6 MHz mv Ver. 2. page 1 of 18

11 Gain, db Gain, db Noise figure, db Noise figure, db VSWR VSWR 7. TYPICAL CHARACTERISTICS C 85 C 6 C C -2 C -4 C C 85 C 6 C C -2 C -4 C Input frequency, MHz Figure 2: Input L1 band Input frequency, MHz Figure 3: Input L2 band C -2 C C 25 C 6 C 85 C C -2 C C 25 C 6 C 85 C Output frequency, MHz Figure 4: Noise L1 band Output frequency, MHz Figure 5: Noise L2 band C 6 C 25 C C -2 C -4 C C 6 C 25 C C -2 C -4 C RF gain code Figure 6: RF gain vs. code Condition: IF gain code 4/ (13 db) /31 IF gain code Figure 7: IF gain vs. code Condition: RF gain code 5 (16 db) Ver. 2. page 11 of 18

12 Gain, db P1dB, dbm Pin, IM3 = 7 db Noise figure, db Noise figure, db NF, db 35 RF gain code 3 RF gain code 5 25 RF gain code 1 RF gain code IF gain code Figure 8: Noise figure vs. IF gain code -5 RF gain code 15-6 RF gain code 1-7 RF gain code 5 RF gain code IF gain code Figure 1: P IM3 = 7 db vs. IF gain code RF gain code 15 RF gain code 1 RF gain code 5 RF gain code Gain, db Figure 9: Noise figure vs. gain Input power, dbm Figure 11: Inband noise figure vs. input power Condition: RF and IF AGC enabled 4 RF gain code RF gain code 1 RF gain code 5 RF gain code RF gain code Rf gain code 15 IF gain code Figure 12: Gain vs. IF gain code IF gain code Figure 13: P1dB vs. IF gain code Ver. 2. page 12 of 18

13 Amplitude, db P1dB, dbm IIP3, dbm Jammer power, dbm L1 band L2 band Jammer frequency, MHz Figure 14: 1dB noise figure desensitization vs. jammer frequency RF AGC = min, IF AGC = min RF AGC = max, IF AGC = min RF AGC = min, IF AGC = min RF AGC = max, IF AGC = min Temperature, C Figure 15: P1dB vs. temperature Temperature, C Figure 16: IIP3 vs. temperature -5-1 LSB USB Output frequency, MHz Figure 17: Frequency response (normalized, typical) Ver. 2. page 13 of 18

14 Amplitude, db Amplitude, db Amplitude, db -2-4 LSB USB Output frequency, MHz Figure 18: Frequency response (normalized) Code (not guaranteed) Code 22; F = 15.1 MHz Code 32; F = 18.1 MHz Code 55; F = 25.1 MHz Code 62; F = 27.1 MHz Code 72; F = 29.6 MHz Code 76; F = 3.8 MHz Code 82; F = 32.4 MHz Code 127 (not guaranteed) Output frequency, MHz -4 C -2 C C 25 C 6 C 85 C Figure 19: Frequency response (normalized) Output frequency, MHz Figure 2: Frequency response (normalized) Condition: LPF cut-off control code 57, F pass band = 25.1 MHz Ver. 2. page 14 of 18

15 6 Channel 1 Channel 2 5 Channel 3 Image rejection, db Channel Output frequency, MHz Figure 21: Typical image rejection characteristic -7-8 PN, dbc/hz Flo = 159 MHz, Fpfd = 1 MHz Flo = 1235 MHz, Fpfd = 5 MHz -12 Flo = MHz, Fpfd = MHz -13 Flo = MHz, Fpfd = 8.28 MHz E+2 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 Frequency, Hz PN, dbc/hz PN, dbc/hz Figure 22: Typical LO phase noise C 6 C 25 C C -2 C -4 C E+2 1.E+3 1.E+4 85 C 6 C 25 C C -2 C -4 C E+5 1.E+6 Frequency, Hz 1.E+7 1.E+8 Figure 23: LO phase noise Condition: FLO = 159 MHz; Fpfd = 1 MHz Ver E+2 1.E+3 1.E+4 1.E+5 1.E+6 Frequency, Hz 1.E+7 1.E+8 Figure 24: LO phase noise Condition: FLO = 1235 MHz; Fpfd = 5 MHz page 15 of 18

16 PN, dbc/hz PN, dbc/hz C 6 C 25 C C -2 C -4 C E+2 1.E E+4 1.E+5 1.E+6 Frequency, Hz 1.E E+2 1.E+8 1.E+3 1.E+4 1.E+5 1.E+6 Frequency, Hz 1.E+7 1.E+8 Figure 26: LO phase noise Condition: FLO = MHz; Fpfd = 8.28 MHz Voltage, 1V/div Voltage, 1mV/div Figure 25: LO phase noise Condition: FLO = MHz; Fpfd = MHz Time, 5ns/div Time, 2ns/div Figure 28: Typical 2-bit ADC output Condition: without RLOAD; CMOS output Voltage, 1.V/div Voltage, 1.V/div Figure 27: Typical clock output Condition: RLOAD = 2 Ohm; LVDS output; VCLK =.46 V; FCLK = 53 MHz Time, 2ns/div Time, 2ns/div Figure 29: ADC digital output time diagram Condition: LVDS CLK output type; CLK output amplitude.57 V; rising edge ADC clock type Ver C 6 C 25 C C -2 C -4 C -11 Figure 3: ADC digital output time diagram Condition: LVDS CLK output type; CLK output amplitude.57 V; falling edge ADC clock type page 16 of 18

17 Code occurrence, % Isolation, db Voltage, 1.5V/div Voltage, 1.5V/div Time, 2ns/div Figure 31: ADC digital output time diagram Condition: CMOS CLK output type; CLK output amplitude ext. (3. V); rising edge ADC clock type Time, 2ns/div Figure 32: ADC digital output time diagram Condition: CMOS CLK output type; CLK output amplitude ext. (3. V); falling edge ADC clock type Output code Figure 33: Typical channel histogram (2-bit ADC output) Temperature, C Figure 34: Channel isolation vs. temperature Ver. 2. page 17 of 18

18 8. DELIVERABLES Depending on license type IP may include: Datasheet Layout view (GDSII) or blackbox Evaluation kit based on packaged IC Characterization report Schematic or SPICE netlist (.cdl) Integration support REVISION HISTORY From version 1.: Section 3 updated Section 2 "Features" updated Minor changes in "AC/DC electrical characteristics". Ver. 2. page 18 of 18