120 to 950 MHz Phase-locked loop frequency synthesizer SPECIFICATION

Transcription

1 SPECFCATN 1 FEATURES ihp SiGe BiCMOS 0.25 um Wide frequency (120 to 950 MHz) Operating frequency selection using external components Built-in switched capacitor sections for VCO frequency adjustment Low noise figure High lock detector accuracy Charge pump low output current disbalance Built-in reference frequency oscillator Programmable clock frequency divider Small area Low current consumption Low power consumption Supported foundries: TSMC, UMC, Global Foundries, SMC, ihp, AMS, Vanguard, SilTerra 2 APPLCATN Portable transmitters Portable transceiver 3 OVERVEW The PLL is an automatic control system which can be used to implement local oscillators (LO) in wireless receivers and transmitters. This device consists of a voltage controlled oscillator (VCO) with external LC tanks, programmable feedback dividers, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with external loop filter, a quartz oscillator with external quartz resonator, programmable reference dividers, comparators of a VCO subband autoselect system and two voltage regulators. The block is fabricated on ihp SiGe BiCMOS 0.25 um technology. Ver. 1.2 October

2 250iHP_PLL_02 4 STRUCTURE 5 PN DESCRPTN Figure 1: Phase-locked loop system structure. Name Direction Description vref12 Voltage regulators reference voltage XO_i1uA Reference oscillator reference current (1µА) VCO_i5u VCO reference current (5µА) Div_i5u Dividers reference current (5µА) LDi1u Lock detector reference current (5µА) CPecl_i5u ECL charge pump reference current (5µА) CPcmos_i5u CMOS charge pump reference current (5µА) PA_buf1_i5u VCO buffer reference current (5µА) ldopll_i5u PLL voltage regulator reference current (5µА) ldovco_i5u VCO voltage regulator reference current(5µа) adjvco_i1u Comparator reference current, controlling VCO voltage LD_SelErr Detection accuracy adjustment LD_SelTime<1:0> Detection period adjustment LD_EN Lock detector enable/disable PFD_Polar PFD polarity CPcmos_EN CMOS charge pump enable/disable CP_out<1:0> Charge pump output current control CPeclEN ECL charge pump enable/disable PFD_EN PFD enable/disable Band<3:0> Subband select VCO_CC<2:0> VCO core current consumption control VCO_EN VCO enable/disable BUF_CC Buffer current enable Ver. 1.2 page 2 of 7

3 250iH_PLL_02 Phase-locked loop frequency system Table Pin Description (continue) Name Direction Description FMUL_EN Frequency multiplier enable/disable FM_mod_173M Frequency multiplier enable for frequency 140MHz Pabuf1_EN Power amplifier buffer enable/disable PA_buf1_CC<2:0> VCO buffer current control transmit_1x0 Modulation signal input mod_transmit Trimming capacitors adjustment enable cvar_0<7:0> cvar_1<7:0> Frequency-shift keying mode selection cvar_receiver<7:0> DAC_TCXO_EN External reference oscillator temperature compensation enable/disable CC_XO<3:0> Reference oscillator current control i_offset_xo<1:0> Reference oscillator offset current control EN_XO Reference oscillator enable/disable XO_Res_EN Reference current additional bias enable N<13:0> N-divider dividing ratio R<8:0> R-divider dividing ratio div_mod Divider type select EN_dividers Dividers enable/disable EN_Rdiv R-divider enable/disable Presc_CC Prescaler additional current enable/disable ThinGate_EN Fixed bounds mode enable ThinGate_Allow Voltage detector bounds type (VCO subband autoselect system) CompH<3:0> Voltage detector upper bound (VCO subband CompL<3:0> autoselect system) Voltage detector lower bound (VCO subband autoselect system) TuneClkRequest VCO subband autoselect system start EN_FLL Clock frequency divider enable/disable Ext_Clk_mod External reference frequency oscillator enable F<4:0> F-divider dividing ratio ldo_pll_vadj<1:0 PLL output voltage control > ldo_vco_vadj<1:0 > VCO output voltage control ldopll_en PLL voltage regulator enable/disable ldovco_en VCO voltage regulator enable/disable F_ADC O ADC clock frequency output F_FA O FA clock frequency output tank1 tank2 VCO core outputs CP_Out Charge pump current output OSC Crystal oscillator analog output OSB Analog output for crystal resonator connection Ver. 1.2 page 3 of 7

4 250iHP_PLL_02 Table Pin Description (continue) Name Direction Description OSE Oscillator core collector output VTCXO External reference oscillator temperature compensation Comp_out_H O VCO maximum allowable control voltage indicator Comp_out_L O VCO minimum allowable control voltage indicator Pa_buf1_outP VCO buffer analog differential output Pa_buf1_outN VCO_i5u_EN O VCO voltage source reference current enable/disable (5 µa) LD_out O Lock detector output F_DG O DSP clock frequency output Xtal_GND Crysral oscillator ground PLL_GND PLL ground VCO_GND VCO ground VCO_VCC VCO supply voltage VCC_h High level supply voltage PLL_VCC PLL supply voltage Ver. 1.2 page 4 of 7

5 250iH_PLL_02 Phase-locked loop frequency system 6 LAYOUT DESCRPTN The block dimensions are given in the table 1. Table 1: Block dimensions. Dimension Value Unit Height µm Width µm Figure 2: Device layout view. 1. Voltage detector (VCO subband autoselect system) 2. VCO voltage regulator 3. VCO 4. Tunable quartz oscillator 5. Crystal oscillator frequency divider 6. Dividers 7. Clock frequency dividers 8. PFD 9. PFD voltage regulator Ver. 1.2 page 5 of 7

6 250iHP_PLL_02 7 OPERATNG CHARACTERSTCS 7.1 TECHNCAL CHARACTERSTCS Technology ihp SGB25V Status silicon proven Area 0.93 mm ELECTRCAL CHARACTERSTCS The values of electrical characteristics are specified for V cc = V and T = C. Typical values are at V cc = 2.2 V and T = +27 C, unless otherwise specified. Parameter Symbol Condition Value min typ max Unit Supply voltage V cc V Operation temperature T С PLL division ratio N PLL For ADC MHz Clock frequency F clk For FA khz For SP MHz 26 Reference frequency Oscillation frequency Peak-to-peak output voltage Peak to-peak at clock frequency differential outputs R divider input frequency R divider programmable values F ref F Osc Depends on connected crystal; 1 st harmonic of oscillator MHz At VCO operating MHz At frequency multiplier operating MHz A VCO mv A cmos CMOS V F RO MHz R PLL Frequency tuning Comparison frequency Current consumption in an active mode Current consumption in a standby mode ΔF XO khz F PFD MHz cc Receive mode ma Transfer mode ma stb na Ver. 1.2 page 6 of 7

7 250iH_PLL_02 Phase-locked loop frequency system Table Electrical Characteristics (continue). Parameter Symbol Condition Value min typ max Unit F Oscillator phase noise PLL = 435 MHz spectral concentration s F PFD = 100 khz Tuning out 10kHz dbhz Lock monitoring time Sel_time ms Lock accuracy Prec_lock ns nput logic-high level V H 0.7V For digital inputs cc - V cc V nput logic-low level V L V 8 DELVERABLES P contents: Schematic or NetList Layout or blackbox Extracted view (optional) GDS DRC, LVS, antenna report Test bench with saved configurations (optional) Documentation REVSN HSTORY From version 1.1: Section 3 Subsection 7.2 update Ver. 1.2 page 7 of 7