A Low-Noise Frequency Synthesizer for Infrastructure Applications

Transcription

1 A Low-Noise Frequency Synthesizer for Infrastructure Applications Shayan Farahvash, William Roberts, Jake Easter, Rachel Wei, Dave Stegmeir, Li Jin RFMD, USA

2 Outline Motivation Design Challenges VCO Capacitor Array Charge Pump Calibration Conclusion

3 Motivation Why an integrated infrastructure-grade synthesizer? Semi-integrated solution with an external VCO is expensive Recent wireless standards (e.g., WCDMA) have a lax requirement on the phase noise compared to legacy ones (e.g., GSM) Power consumption requirements for infrastructure products are not as tight as those for handsets

4 Design Challenges Phase Noise Tuning Bandwidth Stability Kv Variation Design Stability Manufacturing variation Process variation Temperature Current Phase Noise Kv Layout Constraints Current Consumption Bandwidth

5 VCO Colpitts active core No tail current Linearization of the tuning curve using C3 and C4 Tuning sensitivity adjustment using C1 and C2 On-chip low-noise regulator

6 Simulated VCO Performance Similar to other Colpitts variations, there is an optimum n n C 5 C5 C 6 C 7 C7 C 8

7 Simulated VCO Performance Optimum n coincides with voltage-limited operation n C 5 C5 C 6 C 7 C7 C 8

8 Temperature Stability Variation in the VCO frequency as a function temperature is roughly 20MHz

9 Kv Variation The operating voltage of the VCO is selected such that Kv variation is minimized

10 Switch-Capacitor Array Segmented design to keep the area small while simultaneously providing monotonicity Frequency tuning resolution determined by the smallest MIM capacitor allowed Binary Weighted Elements Thermometer Coded Elements C 2C 4C 8C 16C 32C 32C 32C B0 B1 B2 B3 B4 B5 B6 B7

11 Unit Element of the Switch-Capacitor Array Drain of a switch transistor experiences a negative voltage swing

12 Unit Element of the Switch-Capacitor Array

13 Charge Pump The charge pump was required to work up to 6V The potential of each isolated P-well ( where M3 and M4 residing) was adjusted by a tracking circuit

14 Tracking Circuit Performance Bias voltage of each isolated P-well is a function of the output voltage of the charge pump. VVSS VVDD

15 Out of Loop Dividers VCO frequency can be scaled down using a collection of out-of-loop frequency dividers

16 Calibration During calibration, number of VCO cycles are counted in one PFD cycle

17 Measured Synthesizer Performance Calibration algorithm is virtually instantaneous

18 Measured Synthesizer Performance VCO Phase Noise : 600kHz Better phase noise using out-of-loop dividers

19 Performance of the Calibration Algorithm Calibration algorithm can maintain the Vtune within 100mV from what is set by the VC word

20 Die Micrograph

21 Performance Summary

22 Conclusion Fully integrated synthesizer fabricated in 0.18um SiGe BiCMOS process using a switch-capacitor array for wideband tuning VCO phase noise of -134dBc/Hz at 600kHz CP is capable of having an output voltage in excess of 6V albeit the breakdown voltage of MOS devices is only 4V Six out-of-loop dividers provide the means for frequency scaling Calibration algorithm with no delay overhead and less than 100mV error in setting the VCO tune voltage

23 Auxiliary: Tank Voltage and Current Voltage-limited operation with swing twice as large as supply

24 Auxiliary: Tank Voltage and Current Startup is guaranteed even without a tail current source

25 Auxiliary: VCO FOM FOM1: Bandwidth, Power Dissipation and Phase Noise FOM2: Frequency, Power Dissipation and Phase Noise FOM3: Bandwidth, Frequency, Phase Noise FOM1 10log BW f 2 kt P d L f FOM2 10log f0 f 2 kt P d L f FOM3 BW 10log f 2 f 0 L f This Work [3] [1] [2] [4] FOM1 (db) FOM2 (db) FOM3 (db)

26 Auxiliary: Out-of-loop Dividers CML logic based Design emphasis on low noise floor Large signal amplitudes and faster slew rates are necessary Dominant noise source are in clock buffering and output paths Critical to reduce the current reference bias noise