A 42 fj 8-bit 1.0-GS/s folding and interpolating ADC with 1 GHz signal bandwidth

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1 LETTER IEICE Electronics Express, Vol.11, No.2, 1 9 A 42 fj 8-bit 1.0-GS/s folding and interpolating ADC with 1 GHz signal bandwidth Mingshuo Wang a), Fan Ye, Wei Li, and Junyan Ren b) State Key Laboratory of ASIC and System, Fudan University, Shanghai , China a) @fudan.edu.cn b) jyren@fudan.edu.cn Abstract: A 1.0 GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42 fj/conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new fulldigital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the area of chip grandly. A new linear and continues offset voltages of dynamic comparator calibration method is presented. This ADC implemented in 65 nm CMOS technology achieves SNDR of 48.5 db and SFDR of 58.7 db for MHz input frequency at the rate of 1.0-GS/s. And the SNDR and SFDR maintain above 48 db and 55 db, respectively, up to MHz. The power consumption is only 17 mw with a supply voltage of. Keywords: analog-to-digital converter, folding and interpolating, averaging resistors, interpolating resistors, offset voltages, dynamic comparator Classification: Integrated circuits References [1] H. Yu and M.-C. F. Chang: IEEE Trans. Circuits Syst. II 55 [7] (2008) 668. [2] K. Ohhata, K. Uchino, Y. Shimizu, K. Oyama and K. Yamashita: IEEE J. Solid-State Circuits 44 [11] (2009) [3] E. Alpman, H. Lakdawala and L. R. Carley: ISSCC Dig. Tech. Papers (2009) 76. [4] Y. H. Chung and J. T. Wu: IEEE Symposium on VLSI Circuits Digest of Technical Papers (2011) 128. [5] J. Hwang, D. Lee and M. Song: IEEE International Conference on IC Design and Technology (2009) 241. [6] M. Wang and J. Ren: Radio-Frequency Integration Technology RFIT (2011)

2 [7] M. Wang and J. Ren: IEEE 55th International Midwest Symposium on Circuits and Systems (2012) 274. [8] H. Pan and A. A. Abidi: IEEE Trans. Circuits Syst. II 50 [8] (2003) Introduction Recently, the demand for high-speed analog-to-digital converters (ADCs) has increased drastically in the fields of software-defined radio, UWB communication system and high-speed hard disk drive read channels. Traditionally, high-speed ADCs have mainly been implemented using flash architecture [1]. However, the drawback of this kind of architecture is the large power consumption. Lately, sub-ranging [2] and successive approximation architecture (SAR) [3] have been focused as candidates for GHz sampling low-power ADCs. Now, more and more papers about these two types of ADCs are presented. But the conversion speed of sub-ranging ADCs is limited because of the long settling time of the reference voltage. While time interleaved architecture is usually adopted in SAR ADCs to reach high-speed sampling rate, which limits the bandwidth of this kind of ADCs. Meanwhile, complex calibration circuits are needed to cancel the mismatches among different channels and guarantee the performance of this kind of ADCs. In this paper, folding and interpolating architecture is adopted. The folding architecture has potentially nearly the same conversion speed as flash, without the long settling time of the reference voltage and the mismatches among different channels, this kind of ADCs can achieve a high-speed sampling rate and the low power. In previous work [6, 7], inter-switches are inserted into analog signal pre-processing paths to short the analog signal pre-processing time and reach GHz sampling rate. Active interpolating amplifiers are adopted to offer extra signal gain and decrease the effect due to offset voltages of comparators. Though, these methods can solve the sampling rate and the resolution problems, but the high power consumption of this kind of architecture is ignored. In this design, an improved folding and interpolating architecture is proposed. Inter-stage switches are saved and averaging resistors are shared to cancel active interpolating amplifiers. 2 Proposed ADC architecture As shown in Fig. 1, the ADC architecture consists of a group of sub-bootstrapped switches, a reference ladder, pre-amplifiers stage with averaging and interpolating resistors network, two folding and interpolating stages, an extra interpolating resistors array, a comparators array stage and an encoding block. The reference ladder generates 18 level voltages. The 18 level voltages generated by the former stage divide the whole quantified range into 18 sections for pre-amplifiers, which are composed by 18 overall differential N-MOS inputs amplifiers with resistive load including dummies. 18 initial zero-crossings are interpolated by the averaging and interpolating resistors 2

3 Fig. 1. ADC System Block network behind of the preamplifiers and become 36 zero-crossings. 12 folder signals with 36 zero-crossings are generated by the first folding stage, and they are averaged and interpolated by the resistors network. 12 folder signals become 24 interpolation signals. They go through the second folding and interpolating stage and become 16 interpolation signals. These signals are interpolated by the last interpolating resistors network and become 32 interpolation signals. Both 32 interpolation signals and 4 folder signals generated by the first folding stage are offered to comparators array. 36 digital logic signals generated by comparators are divided into two groups. One group is used to encode low 5-bit, which are encoded from cycle thermometer codes through gray codes to binary codes. The other one is used to encode high 3-bit, which are encoded from cycle thermometer codes to binary codes directly. This encoding method guarantees the precision of lower bits and the low power of higher bits [6]. In this design, a high linearity voltage buffer is saved to reduce the power consumption. As we all known, if the high linearity voltage buffer are not used, a kick-back noise will feed back to C S. Where C S is the single sampling capacitor of the single T/H block, and the value of the kick-back noise depends on the rate of C S and C P. C P is a sum of parasitic capacitors on inputs of pre-amplifiers, which is variable with different working modes of inputs transistors. And the working region of inputs MOSFETS is defined by the amplitude of signals. So the kick-back noise will be changed in different inputs, which equals to adding a variable capacitor on C S and will worsen the dynamic performance of the T/H block. In order to cancel the bad effect, there sub-bootstrapped switches are adopted to divided the preamplifiers into three part, It means that C P is divided into three parts, but sampling capacitors of each sub-bootstrapped switch is not changed. The rate between C P (1/3) and C S is reduced greatly and to ensure the performance of the ADC system. A traditional bootstrapped switch usually uses the MOM capacitance or the MIM capacitance as bootstrapping capacitances, but it takes up large chip area and is not suitable for the array application. In this paper, a new bootstrapped switch is proposed with I-MOS capacitance ad 3

4 bootstrapping capacitances. In order to reduce the ADC system power consumption, the averaging and interpolating resistors array is proposed. It means that the resistors array is used to average the nonlinearity and to reach the signal interpolation. The traditional averaging resistor is divided into two parts to reach the interpolation. In this design, the first averaging and interpolating network lies on the back of preamplifiers, which can reduce the number of the preamplifiers from 36 to 18 and reduce the power consumption. The second stage lies on the back of the first folding stage. The third one lies on the back of the second folding stage. Meanwhile, a extra interpolating resistors is used to reach the 8X interpolation. This interpolating method is not like the traditional active interpolator [6] and is suitable for low power design, but this interpolating method has no gain for the signal like the active interpolator. Therefore, the demand of offset voltages from the dynamic comparator is strict. In this paper, a dynamic comparator with offset voltages calibration using a controlled I-MOS capacitance is presented. what is more, the true single-phase clocked register (TSPCR) is adopted to reach the low digital power design in the encoding block. 3 Circuits design 3.1 A bootstrapped switch using I-MOS as bootstrapped capacitances The on-resistance of a bootstrapped switch is independent of the input signal amplitude, which can guarantee the analog signal held in the sampling capacitor high linear. Most kinds of ADCs need to adopt it to maintain the performance of the whole ADC system. In this design, a full digital T/H switch is proposed to meet with a array application. As is shown in Fig. 2, a MOSFET capacitance in inversion mode (I-MOS capacitor) is used to replace the MOM capacitance as a bootstrapped capacitor. The curve of a MOSFET capacitor depended different modes is shown in Fig. 2 (b). The horizontal axis shows a voltage difference between the gate and the source/drain of an I-MOS capacitance, and the longitudinal axis shows values of an I-MOS capacitance. As is known to all, the voltage difference between two sides of a bootstrapped capacitance is about VDD either in the reset mode or the bootstrapping mode. So the region marked by dotted lines is real working region as a bootstrapped capacitor in this design. The voltage difference between two sides of the bootstrapped capacitance is about from 0.95 V to 1.1 V, which leads the nonlinearity of an I-MOS capacitance change from pf to pf. The bad effect led by ΔC can be ignored. Furthermore, the chip area saved by this improvement is much considerable. Fig. 3 (c) shows the rate between one I-MOS capacitor area and one MOM capacitor area with a same capacitor value 1 pf adopted in this design. The former is about twenty five percent of the later. Whats more, the Vsb(Vdb) of M7 and M8 are varying with the change of the input signal amplitude. It means that the on-resistance is different in different 4

5 IEICE Electronics Express, Vol.11, No.2, 1 9 Fig. 2. (a) A Sub-Bootstrapped Switch With I-MOS as Bootstrapped Capacitance (b) I-MOS Capacitance versus Vg(s/d) (c) Comparing the area of MOM and I-MOS Capacitance as the same value signal amplitudes, which has bad effect on the signals linearity and leads to the resolution of the ADC system decline. In this paper, M13 and M14 are added to cancel the bias effect in the phase of tracking. Cc just is a decoupling capacitor to isolate the noise from ground. Besides, M10, M11 and M12 are added to assist M8 in turning off. 3.2 Averaging and interpolating resistors network The averaging and interpolating resistors network back of the second folder is shown in Fig. 3, which has two resistor networks. The first one is the averaging and interpolating resistors network, and the second one is the extra interpolating resistors network. Averaging and interpolating resistors networks back of the preamplifiers and the first folding stage are same as the first one. In this design, the wide bandwidth is demanded. So how to ensure that the networks have no bad effect on the system bandwidth is very important. According to the spatial filtering theory proposed in [8], the load of the node A and the node B is given as the equation (1). Combining the equations with the RC setting up theory, the value of R1 is made certain. In this design, the value of the averaging and interpolating resistors is shown in Table I, where R1 R2 and R3 are shown in Fig. 3. In Fig. 4, the final stage AC response result shows that the signal path 3 db bandwidth can reach 2.5 GHz and meets with the requirement of the ADC system completely. c IEICE 2014 RA = R2 + R22 + 2R1 R2 RB = R3 + R2 + 2RA R3 (1) 3 5

6 Fig. 3. Folders with Averaging and Interpolating Resistors Network Table I. Values of Folding and Interpolating Resistors Circuit Stages Pre-amplifiers 1 st Stage Folders 2 nd Stage Folders R1 5 kω 4 kω 2.4 kω R2 7 kω 1.5 kω 1 kω R3 N/A N/A 600 Ω Fig. 4. AC Response Curve of the Analog Signal Path 3.3 Dynamic comparator with offset voltages calibration Comparator is a critical part of the conversion from analog to digital. As is known to all, offset voltages from the inputs or outputs of comparators are main elements to affect the performance of them. In this design, comparators array is used. So either static offset voltage or dynamic offset voltage cannot be ignored. Meanwhile, the averaging and interpolating resistors offer no extra signal gain like the active interpolator, so it requires stricter for offset voltages of dynamic comparator. In this paper, a dynamic comparator with offset voltages calibration using I-MOS capacitance is presented as shown in Fig. 5 (a). Before the ADC system working, two inputs of the comparator are connected together. Because of the offset voltages, the outputs of the comparator go through the digital logic as shown in Fig. 5 (b) and generate a voltage to control the I- MOS capacitance connected to the output nodes. Until the outputs of the dynamic comparator are changed, the calibration is finished. After the offset voltages calibration, one sigma value of offset voltages is reduce from 30 mv 6

7 Fig. 5. (a) A Dynamic Comparator with Offset Voltages Calibration (b) Digital Control Logic of Offset Voltages Calibration (c) Monte Carol Simulation Results Before and After Calibration to 0.66 mv as shown in Fig. 5 (c). Meanwhile, dummy MOSFETs M8 and M10 are added to cancel the clock feed through and adopted half size of M7, M9. 4 Post simulation results A single-channel 1.0-GS/s 8-bit folding and interpolating ADC with 1.0-GHz bandwidth is designed in 65-nm CMOS technology. Fig. 6 (a) is the FFT frequency spectra with nyquist frequency input at the sampling rate 1.0 GS/s without considering noise and the mismatches of the electric component, and Fig. 6 (b) is the FFT frequency spectra with nyquist frequency input at the sampling rate 1.0 GS/s with considering noise and the mismatches of the electric component. The SNDR reduces by 0.5 db, and the SFDR reduces by 2 db. However, there are no bad effects on the performance with the low frequency input according to the post simulation results. Fig. 7 (a) shows the Post simulated SNDR and SFDR versus input signal frequency at 1.0 GS/s. SNDR and SFDR achieves 48.2 db/55.5 db at a 4.88 MHz input frequency and 48.5 db/58.7 db at a MHz input frequency. What is more, SNDR and SFDR also reach above 48 db/55 db, respectively, up to MHz. According to the post power simulation results, the total power consumption is only 17 mw at a supply voltage. The power consumption of each part is shown in Table II. Its FOM is 42 fj/conv-step compared with other measured results as shown in Fig. 7 (b). The Fig. 8 is the layout pattern of this design with the size. (Fom = P diss /(2 ENOB 2 ERBW)). 7

8 IEICE Electronics Express, Vol.11, No.2, 1 9 Fig. 6. FFT frequency spectra as Fin = MHz (a) Without Noise and Mismatches of the electric component (b) With Noise and Mismatches of the electric component Fig. 7. (a) Post Simulation results of SNDR/SFDR versus Fin (b) The Summary of Similar Performance ADCs Table II. Power Consumption of each Block Circuit Stages Bootstrapped Switches Pre-amplifiers st 1 Stage Folders 2nd Stage Folders Comparators Digital Encoder 5 c IEICE 2014 Supply Voltage Power Consumption 0.95 mw 4.1 mw 2.6 mw 3.8 mw 4.97 mw mw@4.88 MHz as input 1.08 mw@479.5 MHz as input Summary A 1.0-GS/s 8-bit single-channel folding and interpolating ADC with 1.0 GHz signal bandwidth is proposed in this paper. Optimizing the gain of preamplifiers and folding amplifiers to reach the 8-bit resolution and Optimizing the 8

9 IEICE Electronics Express, Vol.11, No.2, 1 9 Fig. 8. Layout Pattern of the ADC value of averaging and interpolating resistors to reach low power consumption and wide bandwidth. Post simulation results show that the ENOB is larger than 7.6 bits across the full sampling frequency range at 1.0-GS/s. Its Fom is the best one among similar performance designs as shown in Fig. 7 (b). Acknowledgements This work is sponsored by National Science and Technology Major Project with No.2009ZX , Special Research Funds for Doctoral Program of Higher Education of China with No and National Science and Technology Major Project of China with No.2012ZX c IEICE