Coherent Detection Gradient Descent Adaptive Control Chip

Transcription

1 MEP Research Program Test Report Coherent Detection Gradient Descent Adaptive Control Chip Requested Fabrication Technology: IBM SiGe 5AM Design No: Fabrication ID: T57WAD Design Name: GDPLC Technology Code: IBM_5AM Size: 9mm 2 Abstract The design and operation of a multi-dithering adaptive controller fabricated by MOSIS using the IBM SiGe 5AM technology is reported. The controller implements gradient descent of an external control objective by using multi-channel harmonic excitation and coherent detection, suitable for use in free-space laser communications. Testing of the building blocks was performed by building a PCB and developing accompanying software to control the inputs of the chip. Tests on the oscillators reveal wide operating range covering almost 7 decades of dithering frequencies with amplitude-controlled sinusoidal oscillation from 100Hz to 1GHz. Experiments interfacing the chip to a resistor-diode circuit implementing a 3-D metric confirm minimization of the metric by the chip at variable adaptation rate. Ph.D. Student: Dimitrios Loizos (dloizos@jhu.edu) Advisors: Prof. Paul Sotiriadis (pps@jhu.edu) Co-Advisor: Prof. Gert Cauwenberghs (gert@ucsd.edu) Johns Hopkins University Department of Electrical Engineering 3400 North Charles str., Barton Hall 105 Baltimore, MD, 21218

2 1. Background and Motivation Our basic motivation in implementing the chip was its direct application in optimizing the received power in laser communications, although its use can be expanded in many fields and, is, by no means, limited to the specific application. Free-space laser communication is a very efficient approach for ground wireless links. It allows for high data rates and doesn t suffer by bandwidth congestion as RF-based communications do. Several commercial products are available in the market e.g. [1,2]. Laser communication is also a promising future solution for earth to moon as well as ground-to-satellite, inter-satellite and deep space communication [3]. In many instances of free-space laser communication it is desirable to use more than one laser beams. This has significant advantages in terms of robustness in performance (not all beams are interrupted simultaneously), better safety (since the power is more distributed and therefore is less harmful), easier design and fabrication of stable laser sources and optics. For multi-laser beam transmitters to operate successfully it is critical that all laser beams hit the target point (optics and photo-diode of the receiver) coherently. A controller is therefore required to perform the necessary adjustments for the phase of each laser beam, either at the receiver or the transmitter. The two more prominent and widely used techniques for this purpose are wavefront reconstruction and model-free optimization [4]. Wavefront reconstruction can be achieved only at the receiver end, while model-free optimization at either end. Adaptation at the receiver can compensate only for first-order aberrations; for high-resolution phase compensation, adaptation at the transmitter is required. Taking this into consideration, the chip we designed has been intended for use at the transmitter end. An overall picture of the entire system is given in Fig. 1. The implemented phase-coherency controller is based on gradient descent optimization. The design is almost completely analog, so as to achieve fast adaptation rates. Similar designs have been implemented by our group in [5,6] where, instead of a deterministic, a stochastic gradient descent method was used to adjust micro-mirror arrays in MEMS. Transmitter Modulated High Power Laser Beam Amplifier Phase Shifter Amplifier Phase Shifter Receiver Photo-Diode and Amplifier Amplifier Phase Shifter Received power calculator Phase Controller Figure 1: Structure of the multi-beam free-space Laser communication system using the implemented phase controller circuit. 2. Architecture The implemented phase controller consisted of eight sub-controllers, one for every controlled parameter (in the case of laser beams that would be the phase). The structure of each sub-controller is shown in Fig. 2. The

3 main idea was to superimpose a small dither to signal G that controlled the k-th parameter. The dither was a sinusoidal signal of frequency f k and each sub-controller generated this dither at a different frequency. These small perturbations of the phases were reflected to the calculated metric (in the laser communication application that would be power) and associated with its gradient. By applying synchronous detection on the power signal at each of the sub-controllers, it was possible to retrieve the information of the gradient specific to each of the subcontrollers, namely the partial derivative of the metric with respect to signal G of the k-th controller. Once this information was retrieved, applying the gradient descent algorithm led to optimization of the metric with respect to signals G. More specifically, for each sub-controller, a 3-phase oscillator generated sinusoidal signals of 120 o phase difference at frequency f k. One of these phases, fixed and the same for all channels, was superimposed through a capacitor array to signal G. Purpose of the capacitor array was to control the amplitude of the dither signal that would propagate to the output. The amplitude had to be low enough not to cause major shifts of the phase of the laser beam, but also high enough so as to be detectable by synchronous detection. Perturbations were applied to the outputs of the controllers for all parameters. The metric was calculated, and the information was fed back and provided to each of the sub-controllers. For each of them, the appropriate phase of the oscillator was chosen and multiplied with the metric information. This phase could be different than the one being superimposed to the signal at the output, since there was some phase delay added to the perturbation signal from the moment it was applied at the output of the controller until the information of the calculated metric was received and provided to the controllers. The output of the multiplier, B, was low-pass filtered and only the information of the partial derivative of the metric with respect to G (or H) was retained. This information was quantized (signal D) and applied to a charge pump. The sign selection block provided flexibility to the whole design by allowing adaptation for metrics other than power, where minimization was needed instead of maximization. Purpose of the charge pump was to control the rate at which maximization (or minimization) was performed, i.e. how fast the adaptation would be. The overall architecture had been designed in a way so that most of its parameters are tunable. The frequencies generated by the oscillator could be tuned in a wide range, the cut-off frequency of the low-pass filter could as well change in a wide range, the amplitude of the dithers could be adjusted, the rate at which maximization (minimization) was achieved could increase or decrease, maximization or minimization of a metric could be selected. All these options gave an extreme versatility to the system. Gradient Descent Controller for the k-th beam multiplier U received power phase selection 3-phase f k 3 3 buffer capacitor array buffer to k-th phase shifter H G B C E amplifier LPF quantizer sign selection charge pump Figure 2: The architecture of the sub-controller in the phase controller circuit D CP C 3. Layout and Fabrication Since speed and wide frequency range tunability was an issue, it was decided to design the architecture using heterojunction bipolar transistors. Suitable, for this case, was the IBM SiGe 0.5μm AM BiCMOS process provided through MOSIS. The layout of the chip is illustrated in Fig. 3 and covers an area of 3mm x 3mm. The chips were housed in LCC84M packages, providing on one hand the 84 pins needed for complete control of the

4 system, and on the other hand fairly low pin parasitics. Figure 3: Layout of the chip 4. Testing Setup For testing purposes, we designed a PCB to both control the inputs and biases of the chip, and provide an interface between the chip and the measuring equipment or any other supporting circuitry. The chip had 29 digital and 36 analog (bias) inputs. In order to minimize the amount of supporting circuitry, latched shift registers and daisy-chained latched DACs, all serially connected, were incorporated on-board. This reduced the amount of external signals provided by a PC for controlling the chip, to only 4 digital signals: clock, data, load and clear. These signals were output from a DIO card at speeds up to 100kHz, sufficient enough for the correct operation of the system. A block diagram of the architecture of the board is shown in Fig. 4. Shift registers A Q1 29 CLK Q29 LD CR MOSIS SiGe BiCMOS chip High Speed buffers Ω 8 50Ω SMA connectors ` Phase Controller A DACs V1 CLK LD V36 CR 36 Testing Board Figure 4: Printed Circuit Board Architecture We used high speed buffers at the outputs as an intermediate layer between the chip and the external testing circuitry. The two main reasons for using these buffers were the following. First, the output impedance of the on-

5 chip buffers depended on the frequency at which the system operated, since the bias current of these buffers was directly linked to the bias current setting the dithering frequency. Were there not to be any external buffers, this would lead to a frequency-dependent output impedance and prohibit any measurement. The second reason is that, in order to have a low output impedance from the on-chip buffers, these should be driven with a large amount of current that would heat the chip to an extent where probably a cooler would be needed. The external high speed buffers had a constant input and output impedance with respect to frequency, had a gain of 1 up to 1.75GHz and were powered from different supplies than the chip. The outputs of the high speed buffers were then connected through 50Ω transmission lines to SMA connectors. In Fig. 5 are shown pictures of the top and bottom part of the testing board. Figure 5: Top and bottom part of the testing board To program the shift registers and the DACs, we developed a software utility using Visual C++. The utility provides a graphical interface to the user for programming the board, the ability to load settings as well as store them. A screen shot of the GUI is shown in Fig. 6. Figure 6: GUI for programming the testing board

6 5. Measurements 5.1 Oscillator We had designed the oscillators to be both frequency and amplitude tunable. The two controls were dependent in an almost linear fashion, i.e. doubling the bias current corresponding to the oscillation frequency required almost double the current for the amplitude bias, in order to keep the amplitude constant while frequency changed. In order to characterize the range of frequencies at which the oscillator could operate, the ratio between the current bias for frequency and that for amplitude was set at 5:1, keeping the amplitude constant for almost all frequencies and close to 20mV pp. The relation between bias current and oscillation frequency is shown in Fig. 7. As can be seen, there is a linear control of frequency with the bias current for a very wide range of almost 7 decades (orders of magnitude). V 20MHz V 12MHz V ref Figure 7: Frequency versus bias current Figure 8: Adaptation for a function with a global minimum 5.2 Adaptation We also did measurements to characterize the operation of the entire system. For initial characterization, instead of power maximization in a laser communication setup, we implemented a simple function with a global f V V, V max V, V, minimum using diodes and resistors. The exact function was ( 1, 2 ref ) = ( 1 2 V ref ) min( V1, V2, V ref ) 2V F where V 1 and V 2 were the outputs from two channels, V ref was a reference voltage and V F was the forward voltage of the diodes used. Function f has a global minimum at the point where V 1 =V 2 =V ref. Therefore, the desired response of the system would be for voltages V 1 and V 2 to follow closely voltage V ref. The output of the function was connected at the input of the system. For the purposes of the experiment we set the oscillation frequencies of the two channels used to 12MHz and 20MHz. V ref was a square wave provided from a function generator. The response of the system is shown in Fig. 8. As can be seen, signals V 1 and V 2 followed the square wave. When the reference voltage V ref increased, several ms were needed for signals V 1 and V 2 to reach the desired value. When V ref decreased, the adaptation occurred much faster. This was due to asymmetric gains of the charge pump for the increase and decrease rate. Adjusting appropriately these gains, it was possible to make the adaptation faster or slower, symmetric or asymmetric.

7 References [1] [2] [3] Schuster, J, Hakakha, H, and Korevaar, E, Optomechanical design of STRV-2 lasercom transceiver using novel azimuth/slant gimbal, SPIE, Vol. 2699, January 1996, pp [4] M.A. Vorontsov, Decoupled stochastic parallel gradient descent optimization for adaptive optics: integrated approach for wave-front sensor information fusion, J. Opt. Soc. Am. A, February 2002, Vol. 19, No. 2, pp [5] T. Weyrauch, M.A. Vorontsov, T.G. Bifano, J.A. Hammer, M. Cohen, and G. Cauwenberghs, Micro-Scale Adaptive Optics: Wavefront Control with Micro-Mirror Array and VLSI Stochastic Gradient Descent Controller, Applied Optics, vol. 40 (24), pp , [6] G. Carhart, M. Vorontsov, M. Cohen G. Cauwenberghs, and R.T. Edwards, Adaptive Wavefront Correction Using a VLSI Implementation of the Parallel Perturbation Gradient Descent Algorithm, in High-Resolution Wavefront Control: Methods, Devices, and Applications, Proc. SPIE, vol. 3760, 1999.