A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20

Transcription

1 A 6 th Order Ladder Switched-Capacitor Bandpass Filter with a center frequency of 10 MHz and a Q of 20 Joseph Adut,Chaitanya Krishna Chava, José Silva-Martínez March 27, 2002 Texas A&M University Analog and Mixed Signal Center Department of Electrical Engineering College Station, TX Design Password: secondo Design number: Design name: bandpassfilter Technology: SCN4ME_SUBM, lambda =.2 Fabricated on run: Layout size: Students: Advisor: T19P (TSMC_035) as T19PAC 2040 x 2040 microns Chaitanya Krishna Chava (chava@ee.tamu.edu) Joseph Adut (jadut@ee.tamu.edu) Dr. José Silva-Martínez Number of parts received: 40 Number of parts tested: 4 Number of parts functional: 4-1 -

2 LDO Regul ator LDO Regulator Figure1: Layout of the IC sent to MOSIS for fabrication Experiment Setup: Bandpass filter The experiment setup consists of a printed-circuit-board (PCB) containing the integrated circuit fabricated through MOSIS, matching networks, DC-bias, BNC cables, power combiners, and an Agilent 4395-A Network/Spectrum/Impedance Analyzer. The analyzer s RF output was used as the input signal, and the output was measured using the network analyzer capability. The frequency range of the analyzer is from 10 Hz to 500 MHz with 1 mhz resolution. The dynamic magnitude and phase accuracy are +/- 0.05dB and +/-0.3deg. Clock signal for the filters will be generated using an Agilent 81330A 2.5V/600MHz pulse generator. The first PCB has been manufactured, and the filter is functional. Due to design problems in the PCB, full characterization of filter parameters was not possible. A report on the filter performance will be submitted, as soon as the PCB troubleshooting has been completed, this could take 3-4 weeks. Experiment Setup: LDO Regulator The experiment setup to test LDO regulator consists of a printed-circuit-board (PCB) containing the integrated circuit fabricated through MOSIS, DC-bias, BNC cables, HP-function generator and an Agilent Infinium oscilloscope. Since the basic idea of the design is to test an improved frequency compensation scheme for LDO regulators, the square wave output of the function generator is used to provide excitation in the loop. The PCB is functional and some of the experimental results are summarized below

3 The circuit has two bias currents each in the range of 1u-10uA adjustable by the potentiometer. The range and variation of bias currents is verified experimentally, and these results are in good agreement with the expected ones. The circuit (voltage regulator) provides a constant output voltage for varying load currents. This property is verified for a maximum load current of 50mA for an output voltage of 2.8V. The input referred offset of the circuit is 58mV, higher than expected. This probably occurred because of the mismatch of the input of the differential pair. The differential pair used minimum length available in the technology (0.4um) thereby making it prone to the mismatches. The following diagram gives the step response of the circuit measured with (top trace) and without improved frequency compensation (bottom trace). The improvement in the stability of the circuit has removed oscillation previously present. Figure2: Step-response of LDO regulator with improved frequency compensation(blue) and without it(yellow) - 3 -

4 Design, Fabrication, and Testing of High Frequency Switched-Capacitor Filters Joseph Adut, George Thomas, Jose Silva-Martinez July 20, 2001 Project Submitted to MOSIS Fabrication Process: TSMC 0.35m. Texas AM University Analog and Mixed Signal Center Department of Electrical Engineering College Station, TX Project Descriptions The prototype in TSMC 0.35µm will consist of two projects. The primary objective of the first project is to design, layout and characterize a 2nd order switched-capacitor (SC) bandpass filter with a center frequency of 10 MHz at a clock frequency of 100 MHz. The operational transconductance amplifiers (OTA) have been designed for very high frequency operation. The speed of the OTA is critical for high operating frequencies which needs selection of a suitable OTA topology. In this design, we use the telescopic cascode OTA which has low parasitics, thereby we can push the nondominant pole to high frequencies. Output voltage swing is maximized by DC level shifting of the analog ground at the input, thus reducing the problem of low voltage swing which is associated with telescopic structure. The following performances were achieved for the OTA in the simulations using SpectreS. Gainbandwidth (GBW) of 700 MHz, DC gain of 58dB and phase margin (PM) of 51. The OTA is used with a SC common-mode feedback. The designed OTA has a settling time 3.3 ns for a bias current of 1.7mA for power consumption of 5mW. The objective of the second project is to design, layout and characterize a fully differential SC 6th order ladder bandpass filter with a quality factor (Q) higher than 20, a center frequency of 10MHz at a clock frequency of 60MHz. A variation of the folded OTA with high slew-rate and modest current consumption will be used. The OTA has been used in a fully differential SC amplifier configuration with discrete-time common-mode feedback, and fabricated in the AMI 0.5 µm process. Its main design features are DC gain of 58 db, GBW of 468 MHz, PM of 53, a slew rate of 150 V/s, and a 1 settling time of 6 ns (500mV differential input) for a capacitive load of 0.7pF, a bias current of 320 µa, and a power consumption of 2.1 mw. The prototype is functional, undergoing final tests. Measures to - 4 -

5 reduce capacitance spread, which relaxes OTA specifications and saves silicon area, have been employed in the filter. Simulation and Layout The transistor-level designs have been simulated using SpectreS simulator under the Analog Environment of Cadence IC 4.4.6, NCSU CDK Design Kit 1.2. SPICE models provided by MOSIS for the TSMC 0.35µm process have been used to verify design in the presence of parasitic capacitances and transistor non-idealities. A layout of the final designs will be created in the Virtuoso Environment. After using design-rule-checker (DRC) and layout-versusschematic (LVS) tools available under Cadence, postlayout simulations will be performed before submission of the designs. Transistors of various sizes, an OTA, an output buffer for each design will be included for characterization in the final layout. Testing The final stage of the projects will be experimental characterization of the fabricated chip. The estimated area of the chip is 5mm to be enclosed in a 64-pin PTQFP64A package. Clock signal for the filters will be generated using an Agilent 81330A 2.5V/600MHz pulse generator. Sony/Textronix AFG320 arbitrary function generator with two channels will be used to generate fully differential input sine-wave input signals up to 16MHz. A Rohde-Schwarz FSEB 20Hz-7Ghz spectrum analyzer will be utilized to measure the magnitude response of the filters. Project Designers: Contact-Person Advisor Mosis-Liaison Joseph Adut, George Thomas, Dr. Jose Silva-Martinez Joseph Adut (jadut@ee.tamu.edu) Dr. Jose Silva-Martinez Dr. Edgar Sanchez-Sinencio - 5 -