ICS1561A. Differential Output PLL Clock Generator. Integrated Circuit Systems, Inc. Features. Description. Block Diagram
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1 Integrated Circuit Systems, Inc. ICS1561A Differential Output PLL Clock Generator Description The ICS1561A is a very high performance monolithic PLL frequency synthesizer. Utilizing ICS s advanced CMOS mixed mode technology, the ICS1561A provides a low cost solution for high-end video clock or Teleclock generation. The ICS1561A has differential clock outputs (CLK and CLK*) that are compatible with industry standard video DACs & RAMDACs. Additional clock outputs, FDIV2, FDIV4 and FDIV8, provide frequencies which are 1/2, 1/4 and 1/8 the main clock frequency. Operating frequencies are selectable from a preprogrammed (customer defined) table. An on-chip crystal oscillator for generating the reference frequency is provided on the ICS1561A. The 728 is an excellent low-jitter Teleclock source for communications systems. When addressed at 1910 (13 hex) with a reference, the 728 provides an STS-3 (STM-1) differential clock that is compatible with SONET and ATM transmitters. Features High operation for extended video modes - up to 230 Compatible with Brooktree high performance RAMDACs Low Cost - Eliminates need for multiple ECL crystal clock oscillators in video display subsystems Advanced PLL for low phase-jitter Dynamic control of VCO sensitivity provides optimized loop gain over entire frequency range Strobed/Transparent frequency select options Small footprint - 20-pin DIP or SOIC packages available Fully backward compatible to ICS option capable of STS-3/STM-1 communication clock generation Block Diagram RAMDAC is a trademark of Brooktree Corporation. Teleclock is a trademark of Integrated Circuit Systems, Inc. ICS1561ARevB081694
2 Pin Configuration FS FS2 FS FS3 STROBE 3 18 FS4 VDD 4 17 AVSS XTAL FDIV8 XTAL FDIV4 FOUT 7 14 FDIV2 VSS 8 13 CLK Reserved 9 12 CLKIN AVDD VDDO ICS1561A 20-Pin DIP or SOIC Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 1 FS1 select input, TTL compatible. 2 FS0 select input, TTL compatible (LSB). 3 STROBE Negative edge clock for select inputs, TTL compatible. 4 VDD 5V power pin. 5 XTAL1 Crystal interface/ext. oscillator input. 6 XTAL2 Crystal interface. 7 FOUT Clock output, TTL compatible. 8 VSS Digital ground. 9 Phase-out Phase comparator output. 10 AVDD Analog VDD input. 11 VDDO Output stage VDD supply pin. 12 CLOCKN Complementary clock output, positive ECL. 13 CLOCK Clock output, positive ECL. 14 FDIV2 Clock/2 output, TTL compatible. 15 FDIV4 Clock/4 output, TTL compatible. 16 FDIV8 Clock/8 output, TTL compatible. 17 AVSS Analog ground. 18 FS4 select input, TTL compatible. 19 FS3 select input, TTL compatible. 20 FS2 select input, TTL compatible. 2
3 Absolute Maximum Ratings Supply voltage VDD V to +7V Ambient operating temp TO C to 70 C Storage temperature TS C to +150 C Input Voltage VIN V to VDD+0.5V Output Voltage VOUT V to VDD+0.5V Clamp Diode Current VIK & IOK ±30mA Output Current per Pin IOUT ±50mA Power Dissipation PD mW Values beyond these ratings may damage the device. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than the maximum rated voltages. For proper operation, it is recommended that Vin and Vout be constrained to >=VSS and <=VDD. DC Characteristics (Power Supply Voltage Volts) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL VDD=5V VSS 0.8 V Input High Voltage VIH VDD=5V 2.0 VDD V Input Leakage Current IIH VIN=VDD - 10 µa Output Low Voltage VOL IOL=8.0mA V Output High Voltage VOH IOH=4.0mA V Supply Current IDD VDD=5V - 30 ma Internal Pull-up Current RUP VDD=5V µa Input Pin Capacitance CIN FC=1-8 pf Output Pin Capacitance COUT FC=1-12 pf 3
4 Circuit Description Overview The ICS1561A is designed to provide the graphics system clock signals required by industry standard RAMDACs. One of 32 pre-programmed (user definable) frequencies may be selected under digital control. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference frequency. The ICS1561A uses the latest generation of frequency synthesis techniques developed by ICS and is completely suitable for the most demanding video applications. Digital Inputs The FS0-FS4 pins and the STROBE pin are used to select the desired operating frequency from the 32 pre-programmed frequencies in the ROM table of the ICS1561A. The FS0-FS4 and STROBE pins are each equipped with a pull-up and will be at a logic HIGH level when not connected. Transparent Mode - When the STROBE pin is held HIGH, the FS0 through FS4 inputs are transparent; that is, they directly access the ROM table. The synthesizer will output the frequency programmed into the location addressed by the FS0- FS4 pins. Latched Mode - When the STROBE pin is held LOW, the FS0-FS4 pins are ignored. The synthesizer will output the frequency corresponding to the state of the FS0-FS4 pins when the STROBE pin was last HIGH. In the event that the ICS1561A is powered-up with the STROBE pin held LOW, the synthesizer will output the frequency programmed into address 0 (i.e., the one selected with FS0 through FS4 at a logic LOW level). Divided Dot clock Outputs The ICS1561A has additional outputs which provide a /2, /4 and /8 of the main frequency. Synthesizer Description The reference frequency is generated by an on-chip crystal oscillator, or the reference frequency may be applied to the ICS1561A from an external frequency source. The ICS1561A generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a closed loop feedback system that drives the output frequency to be ratiometrically related to the reference frequency provided to the PLL. The phase-frequency detector shown in the block diagram drives the VCO to a frequency that will cause the two inputs to the phase frequency detector to be matched in frequency and phase. This occurs when: F(XTAL1) * Feedback Divider F(VCO)= Reference Divider This expression is exact; that is, the accuracy of the output frequency depends solely on the reference frequency provided to the part (assuming correctly programmed dividers). The divider programming is one of the functions performed by the ROM lookup table in the ICS1561A. The VCO gain is also ROM programmable which permits the ICS1561A to be optimized for best performance at each frequency in the table. The feedback divider makes use of a dual modulus prescaler technique that allows construction of a programmable counter to operate at high speeds while still allowing the feedback divider to be programmed in steps of 1. This is an improvement over conventional fixed prescaler architectures that typically impose a factor-of-four penalty (or larger) in this respect. A post divider may be inserted between the VCO and the CLK and CLK outputs of the ICS1561A. This is useful in generation of lower frequencies, as the VCO has been optimized for high frequency operation. Different post divider settings may be used for each frequency in the table. Output Stage Description The CLK and CLK outputs are each connected to the drains of P-Channel MOSFET devices. The source of each of these devices is connected to VDDO. Typical on resistance of each device is 15 Ohms. These outputs will drive the clock and clock* of a RAMDAC device when a resistive network is utilized. The divided outputs are high current CMOS type drives. 4
5 Application Information Power Supplies The ICS1561A has a VDDO pin which is the supply of +5 volt power to all output stages. This pin should be connected to the power plane (or bus) using standard high frequency decoupling practice. This decoupling consists of a low series inductance bypass capacitor, using the shortest leads possible, mounted close to the ICS1561A. The AVDD pin is the power supply for the synthesizer circuitry and other lower current digital functions. We recommend that RC decoupling or zener regulation be provided for this pin (as shown in the recommended application circuitry). This will allow the PLL to track through power supply fluctuations without visible effects. Crystal Oscillator and Crystal Selection The ICS1561A has circuitry onboard to implement a Pierce oscillator with the addition of only one external component, a quartz crystal. Pierce oscillators operate the crystal in anti (also called parallel) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when ordering crystals. Bus Clock Interface In some applications, it may be desirable to utilize the bus clock. To do this, connect the clock through a.047uf capacitor to XTAL1 (5) and keep the lead length of the capacitor to XTAL1 (5) to a minimum to reduce noise susceptibility. This input is internally biased at VDD/2. Since TTL compatible clocks typically exhibit a VOH of 3.5V, capacitively coupling the input restores noise immunity. The ICS1561A is not sensitive to the duty cycle of the bus clock; however, the quality of this signal varies considerably with different motherboard designs. As the quality of the bus clock is typically outside the control of the graphics adapter card manufacturer, it is suggested that this signal be buffered on the graphics adapter board. XTAL2 (6) must be left open in this configuration. ICS1561A Interface The ICS1561A should be located as close as possible to the video DAC or RAMDAC. The differential output CLOCK drivers are current sourcing only and are designed to drive resistive terminations in a complementary fashion. CLK and CLK connections should follow good ECL interconnection practice. Terminating resistors should be as close as possible to the RAMDAC. So-called series resonant crystals may also be used with the ICS1561A. Be aware that the oscillation frequency will be slightly higher than the frequency that is stamped on the can (typically %). As the entire operation of the phase-locked loop depends on having a stable reference frequency, we recommend that the crystal be mounted as closely as possible to the package. Avoid routing digital signals or the ICS1561A outputs underneath or near these traces. It is also desirable to ground the crystal can to the ground plane, if possible. 5
6 ICS1561A Standard Patterns ICS produces standard frequency patterns for the ICS1561A. These patterns include the majority of frequencies most customers require. Custom patterns are also available, although a significant volume commitment and/or one-time mask charge will apply. Contact ICS sales for details. ICS Part Number Video Clock Address (HEX) A B C D E F A B C D E F PwrDwn PwrDwn Reference Note: All frequencies above 180 in the standard patterns shown above are experimental and are not guaranteed. Order info: ICS1561AM-XXX or ICS1561AN-XXX (M = SOIC pkg., N = DIP pkg., XXX = Pattern number)
7 20-Pin DIP Package Ordering Information ICS1561AN-XXX Example: ICS XXXX N -XXX Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type N=DIP (Plastic) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 7
8 SOIC Packages (wide body) LEAD COUNT 14L 16L 18L 20L 24L 28L 32L DIMENSION L Ordering Information Example: ICS1561AM-XXX ICS XXXX M -XXX Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device PRODUCT PREVIEW documents contain information on products in the formative or design phase of development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. 8
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BiMOS II -BIT SERIAL INPUT, LATCHED SOURCE DRIVERS Data Sheet 262.4D GROUND 5 6 7 UCN55A CLOCK 2 CLK SHIFT REGISTER V DD 5 SERIAL 4 ST LATCHES OE V BB 4 OUT OUT 2 OUT OUT 4 SERIAL DATA OUT LOGIC SUPPLY
MC MOTOROLA CMOS SEMICONDUCTOR TECHNICAL DATA
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8-Bit, high-speed, µp-compatible A/D converter with track/hold function ADC0820
8-Bit, high-speed, µp-compatible A/D converter with DESCRIPTION By using a half-flash conversion technique, the 8-bit CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power.
MOSA ELECTRONICS. Features. Description. MS8870 DTMF Receiver
Features Complete DTMF receiver Low power consumption Adjustable guard time Central Office Quality CMOS, Single 5V operation Description O rdering Information : 18 PIN DIP PACKAGE The is a complete DTMF
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Features Three integrated phase-locked loops Ultra-wide divide counters
FailSafe PacketClock Global Communications Clock Generator
Features FailSafe PacketClock Global Communications Clock Generator Fully integrated phase-locked loop (PLL) FailSafe output PLL driven by a crystal oscillator that is phase aligned with external reference
24-bit Step Size, Resolution 3 Hz typ Exact Frequency Mode Built-in Digital Self Test 40 Lead 6x6 mm SMT Package: 36 mm 2. Phased Array Applications
Features Tri-band RF Bandwidth: Ultra Low Phase Noise -105 dbc/hz in Band Typ. Figure of Merit (FOM) -227 dbc/hz < 180 fs RMS Jitter 24-bit Step Size, Resolution 3 Hz typ Exact Frequency Mode Built-in
MK VCXO AND SET-TOP CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET MK2771-16 Description The MK2771-16 is a low-cost, low-jitter, high-performance VCXO and clock synthesizer designed for set-top boxes. The on-chip Voltage Controlled Crystal Oscillator accepts
Dual PLL Precision Synthesizer AD9578
Data Sheet Dual PLL Precision Synthesizer FEATURES Any output frequency precision synthesis 11.8 MHz to 919 MHz Better than 0.1 ppb frequency resolution Ultralow rms jitter (12 khz to 20 MHz)
6-Bit A/D converter (parallel outputs)
DESCRIPTION The is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I L technology. With an external reference voltage, the will accept input voltages
Low-Jitter, Precision Clock Generator with Two Outputs
19-2456; Rev 0; 11/07 E V A L U A T I O N K I T A V A I L A B L E Low-Jitter, Precision Clock Generator Ethernet Networking Equipment General Description The is a low-jitter precision clock generator optimized
500MHz TTL/CMOS Potato Chip
FEATURES:. Patent pending technology. Max input frequency > 1GHz. Operating frequency up to 500MHz with 2pf load. Operating frequency up to 450MHz with 5pf load. Operating frequency up to 300MHz with 15pf
DESCRIPTION FEARURES. Applications
FEARURES Complete UHF transmitter 450MHz to 1000MHz Frequency Range Data Rates up to 10kbps ASK Output Power to 10dBm on 50ohm load Low external part count Operate with Crystals or Ceramic Resonators SOT23-6
ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
78P2252 STM-1/OC-3 Transceiver
RFO LF LLBACK XTAL1 XTAL2 HUB/HOST PAR/SER 8BIT/$BIT DESCRIPTION The 78P2252 is a transceiver IC designed for 155.52Mbit/s (OC-3 or STM-1) transmission. It is used at the interface to a fiber optic module.
SKY2000. Data Sheet DUAL-TRACK MAGNETIC STRIPE F2F DECODER IC. For More Information. Solution Way Co., Ltd
SKY2000 Data Sheet MAGNETIC STRIPE F2F DECODER IC For More Information www.solutionway.com ydlee@solutionway.com Tel:+82-31-605-3800 Fax:+82-31-605-3801 1 Introduction 1. Description..3 2. Features...3
Spin Semiconductor FV-1 Reverb IC PN: SPN1001. Delay Memory DSP CORE. ROM and Program Control PLL. XTAL Drvr XTAL. Spin.
Featuring Virtual Analog Technology PN: SPN1001 FEATURES Integrated stereo ADC and DAC 8 internal demonstration programs + 8 external programs Easy customization with external EEPROM 3 potentiometer inputs
ICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET
DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate
8-bit shift register and latch driver
8-bit shift register and latch driver The BU2114 and BU2114F are CMOS ICs with low power consumption, and are equipped with an 8-bit shift register latch. Data in the shift register can be latched asynchronously.
The FS6128 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems.
PLL Clock Generator IC with VXCO 1.0 Key Features Phase-locked loop (PLL) device synthesizes output clock frequency from crystal oscillator or external reference clock On-chip tunable voltage-controlled
DEI3182A ARINC 429 DIFFERENTIAL LINE DRIVER
Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI3182A ARINC 429 DIFFERENTIAL LINE DRIVER FEATURES Adjustable
APPLICATIONS GENERAL DESCRIPTION FEATURES PIN CONFIGURATION PIN ASSIGNMENT /INH, Q0 PIN FUNCTION
CMOS Oscillation Frequency : 125MHz (MAX.) 3-State Output Built-in Oscillation Capacitor Built-in Oscillation Feedback Resistor Mini Mold SOT-26 Package APPLICATIONS Crystal Oscillation Modules Computer,
Features +5V ASK DATA INPUT. 1.0pF. 8.2pF. 10nH. 100pF. 27nH. 100k. Figure 1
QwikRadio UHF ASK Transmitter Final General Description The is a single chip Transmitter IC for remote wireless applications. The device employs s latest QwikRadio technology. This device is a true data-in,
ICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental
MIC5841/5842. General Description. Features. Ordering Information. 8-Bit Serial-Input Latched Drivers
MIC5841/5842 8-Bit Serial-Input Latched Drivers General Description Using BiCMOS technology, the MIC5841/5842 integrated circuits were fabricated to be used in a wide variety of peripheral power driver
Features VDD 2. 2 Clock Synthesis and Control Circuitry. Clock Buffer/ Crystal Oscillator GND
DATASHEET Description The is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a.5 MHz or 5.00
LM193/LM293/LM393/LM2903 Low Power Low Offset Voltage Dual Comparators
LM193/LM293/LM393/LM2903 Low Power Low Offset Voltage Dual Comparators General Description The LM193 series consists of two independent precision voltage comparators with an offset voltage specification
ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses
ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS670-02 Description The ICS670-02 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT
3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574. Features. Description. Block Diagram DATASHEET
DATASHEET 3.3 VOLT FRAME RATE COMMUNICATIONS PLL MK1574 Description The MK1574 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 khz clock input as a reference, and generates many