THE UNIVERSITY OF NAIROBI

Transcription

1 THE UNIVERSITY OF NAIROBI ELECTRICAL AND INFORMATION ENGINEERING DEPARTMENT FINAL YEAR PROJECT. PROJECT NO TITLE: A PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER BY: TUNDULI W. MICHAEL F17/2143/2004. SUPERVISOR: DR. V.K. ODUOL EXAMINER: MR. C. OMBURA MAY 2009.

2 OBJECTIVES Study the properties and characteristics of frequency synthesizers Study the properties and characteristics of phase-locked loops Design a phase-locked loop based frequency synthesizer for use in the 12 GHz range, with channel spacing of 36 MHz

3 FREQUENCY SYNTHESIS Frequency synthesis is the engineering discipline of dealing with the generation of multiple signal frequencies, all derived from a common reference or time base. Two ways of generating frequencies Building the waveform from ground up (Direct synthesis) Using an existing signal to generate another (Indirect synthesis) Methods of Frequency Synthesis 1) Direct Analogue (DA) synthesis 2) Direct Digital Synthesis (DDS) 3) Phase-Locked Loop

4 Important parameters of FS Phase noise Frequency range and step-size Switching time Comparative analysis of frequency synthesizers DA Very wideband, very high switching speed, excellent purity, Quite bulky, requires much hardware and is expensive, also complicated to apply digital or analogue modulation. DDS Simple and compact, good resolution, very high switching speed, phase-continuous switching and digital producibilty Limited bandwidth, spurious response limited by quantization and DAC performance PLL S Very wideband, relatively simple, moderate to good switching speed, low-cost, easy to apply analogue modulations, high level integration and low cost. Resolution complex to achieve esp. with integer-n, good quality oscillators are quite bulky, and digital is complicated to apply with sufficient accuracy.

5 PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER Phase-Locked Loop A phase locked loop is made up of the following components: Phase detector(pd) Loop filter Voltage controlled oscillator Applications Frequency synthesizers Modulation and demodulation of FM and AM signals FSK decoders Motor-speed control Frequency multiplications

6 Phase-locked Loop Frequency Synthesizer Is made up of: Phase detector Loop filter Voltage controlled oscillator (VCO) Divider Applications Satellites Radar systems Mobile phones Wireless LAN Home entertainment systems Car radios All wireless communication systems

7 Integer-N and fractional-n PLL synthesizers This types of PLL FS are because of different types of divider Integer-N PLL Synthesizer The divider is a simple counter that can count only integers The output at the VCO is given by the formula Fout = Fref (M) Necessary trade-offs in phase noise, frequency step-size, tuning speed, spurs size and operating frequency range. Fractional-N PLL Synthesizer Its divider is able to give a fractional number, the output of the VCO is : F out = (N + k/m) F ref Where k and M are integers Types Fractional divider-based Current injection-based Delta-sigma modulator-based Low phase noise, higher tuning speed and high frequency resolution

8 DESIGN AND ANALYSIS Design problem Design a phase-locked loop based frequency synthesizer in the 12 GHz range, with channel spacing of 36 MHz Design values Reference frequency = 360 MHz The divider numbers were calculated using the formula N.F = F out / F ref Where N.F is the divider number, integer (N) and fraction (F) F out is the VCO output frequency and F ref is reference To give N between 33 and 36 F between.033 and.933 The divider numbers are form to

9 Fractional-N PLL Synthesizer circuit Scope Control Signal Reference Pulse Generator XOR Phase Detector Phase difference butter Analog Filter Design1 -K- Gain ntinuous -Tim VCO Voltage -Controlled Oscillator In1 Out1 Convert to Square Wave Synthesized Signal Divided synthesized Divide Frequency by N or N+1 synm Fractional Constant State In 1 Carry Accumulator Terminator Carry Divide Frequency Single Tone Frequency Estimator Synthesized Frequency in Hz

10 Sample results N = 33 and F =.333, the VCO output is :

11 At N = 33 and F =.933, the VCO generates Sample Results

12 Sample Results N = 35 and F =.333, the VCO generates

13 N = 36 and F =.033, the VCO generates Sample results

14 Conclusion and Recommendations The designed circuit, generated frequencies that were desired as it was shown from the sample results. Recommendations 1) A further study in fractional spurs to get a more effective way of minimizing them 2) A study of SiGe synthesizers 3) Implementation of the design using SiGe BiCMOS technology

15 THE END THANK YOU!