Analog and Telecommunication Electronics

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1 Politecnico di Torino - ICT School Analog and Telecommunication Electronics C1 - PLL linear analysis» PLL basics» Application examples» Linear analysis» Phase error 08/04/ ATLCE - C DDC

2 Lesson C1: PLL linear analysis PLL basics How the PLL works Application examples Block diagram of the PLL PLL linear model PLL transfer function Parameters and transfer function Loop filter (RC, RRC, active, charge pump) Loop gain Phase error, transient and steady state References: 3.2, /04/ ATLCE - C DDC

3 Phase Lock Loops PLL working principle (lesson B1) Block diagram, phase error, parameters, capture/lock range PLL circuits (lesson B2) Analysis of PLLs (lesson B3 and B4) Applications (lessons B5, B6, B7) AM, FM, FSK, PSK demodulators Integer and fractional synthesizer, DDS data recovery and clock synchronization Lab 1: VCO, digital applications Lab 2: tone decoder, analog applications 08/04/ ATLCE - C DDC

4 Lesson B1: PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state References: 3.2, /04/ ATLCE - C DDC

5 PLL: where? Several PLLs are used in a radio system (cell phone) A: local oscillator for TX frequency translation B: local oscillator for RX frequency translation C: I/Q reference signal for RX D: I/Q reference signals for TX E: clock multipliers and data synchronizer 08/04/ ATLCE - C DDC

6 PLLs in the TX-RX system Syntetisers Generate reference signals Synchronizers and clock multipliers. 08/04/ ATLCE - C DDC

7 A real equipment B C D E A 08/04/ ATLCE - C DDC

8 Inside a P-RX All local oscillator signals generated from a unique reference by a PLL synthesizer 08/04/ ATLCE - C DDC

9 PLL applications Generate signals (phase) locked to a reference AM and FM coherent demodulators TV synchronization Frequency synthesizers Resynchronization Clock/Data recovery and separation (CDR) Bandpass filter with tunable parameters Center frequency Bandwidth and Q 08/04/ ATLCE - C DDC

10 Lesson B1 : PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state 08/04/ ATLCE - C DDC

11 Phase synchronization Angular frequency ω is the derivative of phase θ. Same frequency constant phase difference θe All oscillators exhibit tolerance and drift example 1 Separate oscillators cannot provide the same frequency example 2 PLL: generate a signal locked to a reference Constant θe same frequency 08/04/ ATLCE - C DDC

12 Phase Lock Loop block diagram Vi: input signal Vi(t) = Vi sin(ω i t+ θ i ) PD: Phase Demodulator V I PD V D F: loop filter VCO: Voltage Controlled Oscillator V O VCO F V C Vo: output signal (from VCO) Vo(t) = Vo cos(ω o t+ θ o ) 08/04/ ATLCE - C DDC

13 PLL parameters θe = θi -θo Vd = F(θe) Linear model: Vd = Kd θe PD gain: Kd Vc = Vd F(s) DC filter gain: F(0) Passive: linear, active: limited range Δω = G(Vc) Linear model: Δω o = Ko Vc VCO gain: Ko If Vc = Vco ω o = ω or (not always Vco = 0) Loop gain : DC loop gain: Kd Ko F(s) Kd Ko F(0) 08/04/ ATLCE - C DDC

14 Linearity: where? Any real circuit has a limited linearity range The above relations assume linearity in: Phase detector: Vd = Kd θe Some PD have intrinsic nonlinear transfer function VCO gain: Δω = Ko Vc Most VCO have nonlinear ω(vc) Loop filter: F(s) Passive; saturation if active 08/04/ ATLCE - C DDC

15 Lesson B1: PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state 08/04/ ATLCE - C DDC

16 PLL transfer function - 1 A PLL handles phases Angular frequency ω = derivative of phase θ Using L-transform 08/04/ ATLCE - C DDC

17 PLL transfer function - 2 Phase detector: Loop filter: VCO: Overall fdt: 08/04/ ATLCE - C DDC

18 PLL transfer function - 3 Loop equation PLL transfer function: = 08/04/ ATLCE - C DDC

19 Lock behavior The PLL senses and handles the phase The lock condition means ω o = ω i Starting state: ω o = ω i» With constant input frequency the phase difference, and therefore Vd do not change As ω i, changes, also θe and Vd are modified» The changes in Vd, filtered through F(s), shift the VCO» As long as ω o ω i, θe and Vd change continuously The only steady state condition is ω o =ω i (constant θe) This is the lock keeping mechanism 08/04/ ATLCE - C DDC

20 Phase error The phase error is defined as: e = i - o θ o = θ i H(s); θ e = θ i (1 - H(s)) Same denominator as H(s) Same parameters for time & frequency responses: for II-order damping e resonant frequency n 08/04/ ATLCE - C DDC

21 PLL math summary v i = V i sen (ω i t+ θ i ); v o = V o cos (ω o t+ θ o ) H(s) = θ o (s)/θ i (s) θ e = θ i θ o = θ i (1 - H(s)) Vd = Kd θe Vc = Vd F(s) ω or = ω o for Vc = Vco Δω = Ko Vc Loop gain DC loop gain PD gain: Kd DC filter gain: F(0) VCO gain: Ko G L (s) = Kd Ko F(s) G L (0) = Kd Ko F(0) 08/04/ ATLCE - C DDC

22 Choices for the loop filter F(s) Direct wire RC cell (lowpass) R-R-C cell V I PD V D II order cell Finite-gain amplifier F Infinite-gain amplifier V O VCO V C Charge pump circuits 08/04/ ATLCE - C DDC

23 Direct wire F(s) = 1 Vc = Vd F(s) order 0; PLL H(s) order 1 Only a first example, no real application! 08/04/ ATLCE - C DDC

24 H(s) order 1 frequency response H(s) = 1, o = i H(s) < 1, o i 08/04/ ATLCE - C DDC

25 RC cell filter F(s) order 1 H(s) order 2 Widely used simple filter 08/04/ ATLCE - C DDC

26 H(s) in a PLL with RC filter Response depends on n,, H(0) parameters Three parameters Two degrees of freedom: Ko*Kd, R*C Not possible to get independent n,, H(0) 08/04/ ATLCE - C DDC

27 R-RC filter F(s) order 1 H(s) order 2 Three degrees of freedom Independent control of n,, H(0) Most used filter 08/04/ ATLCE - C DDC

28 Filter with gain Needs active element Example: Op.Amp. amplifier Frequency response F(s) order 1 H(s) order 2, with 2 parameters (R2/R1, R2*C) 08/04/ ATLCE - C DDC

29 PLL order PLL order H(s) order H(s) order = F(s) order + 1 H(s) order 1 H(s) order 2 All cases parameter o parameters o and DC gain (F(0)) 08/04/ ATLCE - C DDC

30 Infinite gain In steady state Vc = Vd F(0) To change ωo, Vc and θe - must change The ratio between phase error θe and control signal Vc depends from Kd and F(0) Infinite gain (F(0) ), Vc 0 even for Vd = 0. For an infinite-gain locked PLL, the phase error e = 0 Two ways to get infinite gain High gain amplifier Charge pump 08/04/ ATLCE - C DDC

31 Infinite gain with amplifier Active integrator, based on Op Amp DC gain = open loop Op Amp gain 08/04/ ATLCE - C DDC

discharged through A or B Vc steady if Phase error = 0

32 Charge pump circuit A closes on Vi edge, opens on Vo edge B closes on Vo edge, opens on Vi edge C charged or discharged through A or B Vc steady if Phase error = 0 (edges at same time) Infinite gain 08/04/ ATLCE - C DDC

33 Infinite gain with charge pump Ideal integrator built with C + SW Similar behavior to open loop Op. Amp. Can be seen as a chopped Op Amp No need for amplifier Used with CMOS circuit needs high input impedance VCO 08/04/ ATLCE - C DDC

34 Lesson B1: PLL linear analysis PLLs: where? PLL basics How the PLL works Application examples Block diagram of the PLL PLL transfer function Parameters and transfer function Loop filter Loop gain Phase error, transient and steady state 08/04/ ATLCE - C DDC

35 Steady state phase error - 1 Defined as Computed as 08/04/ ATLCE - C DDC

36 Steady state phase error - 2 Depends from: Input signal i DC loop gain: Ko Kd F(0) 08/04/ ATLCE - C DDC

37 Phase error analysis Phase error depends from Signals Loop tytpe and parameters Signal: Phase step Frequency step, phase ramp Frequency ramp, parabolic phase Loop parameters loop filter F(s) Finite DC gain Infinite DC gain 08/04/ ATLCE - C DDC

38 Input signal: phase step No need to change the VCO frequency Steady state error with finite loop gain Always zero Steady state error with infinite loop gain Always zero PSK, phase modulations 08/04/ ATLCE - C DDC

39 Input signal: linear phase ramp The VCO frequency must be modified Steady state error with finite loop gain Constant Steady state error with infinite loop gain Always zero FSK, doppler with fixed relative speed 08/04/ ATLCE - C DDC

40 Input signal: quadratic phase ramp The VCO frequency must be modified Steady state error with finite loop gain Unbounded Steady state error with infinite loop gain Constant FSK, doppler with fixed acceleration 08/04/ ATLCE - C DDC

41 Summary for steady state phase error Input signal 08/04/ ATLCE - C DDC

42 Lesson B1 tests Mention some applications of PLLs. Draw the block diagram of a PLL. How are defined the parameters Kd, Ko, F(0)? Define the PLL transfer function H(s). Which is the relation between F(s) and H(s)? List the approximations of the PLL linear model. How to compute the steady state phase error? Evaluate θer value for linear phase ramp input to a PLL using phase detectors with finite/infinite gain Kd 08/04/ ATLCE - C DDC

Analog and Telecommunication Electronics

Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics C5 - Synchronous demodulation» AM and FM demodulation» Coherent demodulation» Tone decoders AY 2015-16 19/03/2016-1