Telecommunication Electronics

Transcription

1 Test 1 In the circuit shown in the diagram C1, C2 and C3 have negligible impedance at the operating frequency R1 = 120kΩ R2 = 220kΩ Rc = 6,8kΩ Val = 15 V hfe > 500 Vi C1 R1 R2 I1 Rc Ve Re1 Re2 C3 C2 V AL Vo a) Find (within 5%) the value of Re1+Re2 required to get a collector current Ic = 0,4 ma; evaluate the peak-to-peak output dynamic range (with no load). Base voltage Vb = 9,7 V (assuming Ib = 0); Emitter voltage Ve = 9 V (or 9,1 V) Re1+Re2 = 9V/0,4mA = 22,5 kω The maximum base current is 0,4mA/500 = 0,8 µa; the voltage drop Vrb on Rb (R1//R2) = 78 kω is Vrb = 78kΩ x 0,8µA = 62 mv, which is less than 1% of Vb. The error due to the Ib = 0 assumption is therefore less than 1%. The output can go from Ve + Vcesat (9,5 V) to Val (15); the output dynamic range is 5,5 V (p-p) b) For Re1=330Ω, evaluate the gain Av=Vo/Vi with linear transistor model; add a capacitor to limit the high frequency response to 15 khz (-3 db). Approximate gain Av = - Rc/Re = - 6,8k/330 = - 20,6; (this i san upper bound for the gain) Actual gain Av: Ib = Vi (1/(hie + (hfe+1) Re)); Vo = - Rc hfe Ib Av = Vo/Vi = - Rc hfe / (hie + (hfe+1) Re)) = - Rc / (1/gm + Re) = - 6,8k/(65+330) = - 17,2 A capacitor from Collector to Ground makes a low-pass cell. To get a cutoff frequency = 15 khz: Tau = 1/(2 π 15k) = 10,6 µs R = Rc = 6,8 k; C = tau/r = 10,6 µs/6,8 k = 1,56 nf DDC -TLCEscris811e - 10/11/

2 c) Draw the spectrum of the output signal in dbc (fundamental at 0dB), for an input signal Vi = 90 mvrms, with Re1 = 0, and without the capacitor mentioned in b). (use linear interpolation for values of In(x) not in the table). 90 mvrms --> 127 mv (peak); x = 4,89 (very close to 5; using 5 is acceptable) I1/Io = 1,62 + (1,787 1,62) 1,89/2 = 1,62 + 0,167 x 0,945 = 1,778 I2/Io = 0,92 + (1,285 0,92) x 0,945 = 1,265 I3/Io = 0,393 + (0,758 0,393) x 0,945 = 0,738 I2/I1 = 1, 265/1,778 = 0,711-2,95 db I3/I1 = 0,738/1,778 = 0,415-7,6 db d) A LC circuit tuned to ωi is added in parallel to Rc. Evaluate the Q required to get on the output Vo a spectral purity of at least 45 db, with the operating conditions in c). The most critical component is the second harmonic 2ωi (3ωi has lower amplitude, and higher attenuation). The 2ωi component is already 2,95 db below the fundamental. To get the required 45 db, the tuned circuit must provide a further attenuation of 45 2,95 = 42 db, which corresponds to a ratio 126. Therefore Zc(ωi) / Zc(2ωi) > 126 From the dissonace relation X = Q k 1/k 126 = Q x 1,5 ; Q = 126/1,5 = 84 Qmin = 84 Most common mistakes - Place a RL (nonexisting) in parallel with Rc (even when no load is specified) - Use F instead of ω to evacuate the time constant of added capacitor - Loose the negative sign of gain - Add to spectral purity (45 db) the attenuation of harmonics (most be subtracted) - Use for the dissonance X the value in db (instead of the ratio) DDC -TLCEscris811e - 10/11/

3 Test 2 An AM receiver operates in the range from 200 to 300 MHz. Modulating signal frequency can vary from 30Hz to 30kHz. The demodulator uses a single-branch synchronous AM detector, with reference signal obtained from a PLL. The PLL phase detector and the AM demodulator are analog 4-quadrant multipliers with Km = 0,5 [V -1 ], and input impedance 20 kω. The VCO center frequency For is 250 MHz; the output voltage a squarewave with levels 0 and 3,3 V. a) Draw the block diagram of the AM detector, and define the placement and the parameters of required filters. Block diagram as in slide B5 15; about the filters: - input signal: bandpass, MHz (slightly more than useful signal) - Loop filter: lowpass, cutoff evaluated in point d) - AM detector output: lowpass, cutoff 30 khz b) Insert the proper device to interface the VCO output with the PLL Phase detector and the AM demodulator; in this condition evaluate Kd (closed loop, θe in radians) and the AM detector gain (Ga = AM detector output/peak value of Vi) for Vi = 300 mvrms. The VCO output (0-3,3V) must go to the PD input through a highpass RC cell, to shift the DC component to 0, and get a squarewave with peak value 1,65 V. The cutoff frequency must be lower than the lowest Fi (200 MHz, 1,26 Gr/s). Since the PD has an input impedance of 20 kω, a suitable value is: C = tau/r = (1/1,26 Gr/s)/20k = 40 pf. (minimum value, can be larger) Kd = Km Vi Vo / 2 = 0,5 x 0,3 x 1,41 x 1,65 / 2 = 0,174 V/rad Ga = Km Vi Vo / 2 Vi = Km Vo/2 = 0,41 c) The loop filter F(s) is a R-C cell followed by an amplifier with gain 5. Evaluate the maximum phase error over the complete operating range, with Ko = 30 MHz/V (Ko defined by Fo = Ko Vc), and the corresponding error (% of full scale) at the AM output Va. (these values bring to malfunction repeat with Ko = 300 MHz/V) F = 50 MHz; Vc = F/Ko = 50/30 = 1,67V; Vd =1,67/5 = 0,33V (+ and -) θe = Vd/Kd = 0,33/0,174 = 1,89 rad (max θe, at extremes of operating interval). This value is higher than π/2, and outside the operating range of the PD (if working, the AM output becomes negative). With corrected values (Ko = 300 MHz/V): Vd = 0,033V ; θe = Vd/Kd = 0,189 rad The corresponding error of Va is 1 cos 0,189 = 1-0,982 = 0,18; Max Error 18% DDC -TLCEscris811e - 10/11/

4 d) Find the cutoff frequency of the loop filter to get a capture range from 225 to 275 MHz. Assuming that the lock range (with F = 50 MHz) correspond to the full excursion of the PD output, the correction voltage required for F = 25 MHz is ½ full excursion. In this case the filter pole must be placed one octave below 25 MHz, that is at 12.5 MHz. The PLL can have a lock range which does not correspond to the full excursion of the PD output; to consider this case we can use a linear model for the PD (Vd = Kd θe) or use the actual PD transfer function Vd = Kd sin θe. Linear PD model: Vdmax = Kd x θemax = 0,174 V/rad x π/2 = 0,273 V (+ or -) Vcmax = 5 x 0,273 = 1,37 V; F = Vc x Ko = 1,37 x 30 = 41 MHz (lock range/2) The control voltage required to get F = 25 MHz is Vc = 25 MHz / Ko = 0,833 V The pole position is Fp = 25 x 0,833 / 1,37= 15,2 MHz Sine PD model The actual maximum output Vdmax from the PD is Kd (the max value of sin x is 1): Vdmax = Kd x 1 = 0,174 V; Vcmax = 5 x 0,174 = 0,87 V; F = Vc x Ko = 0,87 x 30 = 26,1 MHz (lock range/2) The control voltage required to get F = 25 MHz is Vc = 25 MHz / Ko = 0,833 V The pole position is Fp = 25 x 0,833 / 0,87= 23,9 MHz This last is the most correct answer. Most common mistakes - Direct coupling of VCO with the multiplier; keep the 3,3 V peak value at the input of PD; - Use 3,3 V/2 = 1,65 as resting point for Vd; this is true for digital PD: XOR of FF. The analog PD has quiescent output Vd = 0. DDC -TLCEscris811e - 10/11/

5 Test 3 An A/D conversion system has 12 input channels; each channel has bandwidth from DC to 25kHz, and flat spectral power density, decreasing at 40 db/dec from 50 khz to 1 MHz. The ADC has 12-bit output, and uses three flash A/D converters, each with 4-bit resolution and 100 ns conversion time, and D/A converters with 70 ns settling time, connected in a residue configuration (without pipeline). The S/H acquisition time Tacq is 110 ns. a) Draw the block diagram of the complete A/D converter, specifying the precision required for each basic flash ADC, and evaluate the total number of comparators. Find the maximum conversion rate allowed by this converter on each channel, and the maximum sampling rate of the S/H-ADC combination. block diagram in slide C3 67 (only three stages, 4-bit each) precision for each block: - 12 bit the first - 8 bit the second - 4 bit the third Number of comparators: 15 in each flash ADC; 45 total conversion time Tc = 100 x x 2 = 440 ns sampling time = Tc + Tacq = 550 ns max sampling rate = 1,82 Ms/s sampling rate for each channel: 1,82M/12 = 151 ks/s b) The input anti-alias filters have cutoff frequency 25 khz. Find the number of poles required to get an aliasing noise with the same power of the quantization noise, for sampling rate 80 ks/s. SNRq = 73,7 db The signal must go down 73,7 db from 25kHz to = 55 khz The inpu spectum falls 40 db/dec after 50 khz; at 55 khz the attenuation As is As = (55/50) 2 = (1,1) 2 = 1,21, corresponding to 1,65 db The antialis filter must provide a 73,7 1,7 = 72 db rolloff Single-pole attenuation: 55/25 = 2,2, corresponding to 6,85 db Number of poles P = 72/6,85 = 10,5 11 poles DDC -TLCEscris811e - 10/11/

6 c) The S/H has a sampling jitter Tja = 7 ns. Evaluate the related amplitude error (as % of full scale) and the SNRj = (signal power)/(sampling jitter error power), for full scale sine input signals. Is it possible to estimate the effect of this jitter error on the ENOB (without the complete ENOB evaluation)? Max signal slew rate (signal at full scale and max frequency): SRmax = 25k x 2 x pi x S/2 = 78,5k S Corresponding amplitude error deltav = Tja x SRmax = 78,5kV/s x 7 ns x S = 0,55 m S = 0,055% S The quantization step is S/2^12 = S/4k = 0,025% The error caused by sampling jitter is more than twice the quantization error; this will impact ENOB (about 2 bit worse) SNRj = Ps/Pej = (S 2 /8)/((0,55 m) 2 (S 2 /12)) = 66,9 db d) Find the clock rate required to get the same SNRq with a differential A/D for each channel (1-bit differential converter, no adaptation), and define the specs of the antialias filter for this ADC. Find the clock rate required to get the same SNRq with a differential A/D for each channel (1-bit differential converter, no adaptation), and define the specs of the antialias filter for this ADC. To track a 25 khs signal the differential converter must have a Slew Rate SRd SRd = γ x Fck >= 78,5k S To get the same SNRq: γ = S/4k (S/4k) x Fck = 78,5 k S; Fck = 78,5 x 4 M = 314 MHz A single pole filter provides an attenuation 314M/25k = 12,96k 82,2 db A single-pole RC cell is adequate for anti-aliasing. Most common mistakes - not considering spectrum rolloff already present in the input signal; - use a pipeline architecture for the converter - using 16 comparators in the 4-bit ADCs (instead of 15) - use a single comparator in each ADC block DDC -TLCEscris811e - 10/11/