Analog and Telecommunication Electronics

Transcription

1 Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D4 - Signal conditioning» Protection circuits» Amplifiers» Anti-aliasing filter» Multiplexer» Sample/Hold AY /04/ ATLCE - D DDC 2016 DDC 1

2 Lesson D4: signal conditioning Overall conversion system design Signal conditioning Protection circuits Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits, Sampling jitter noise Total system error (ENOB) Other parameters: SFDR, SINAD, THD References: Elettronica per Telecom.: Filtro anti-alias; 4.4 Circuiti S/H Design with Op Amp : 9.7 S/H amplifiers 16/04/ ATLCE - D DDC 2016 DDC 2

3 A/D/A system block diagram Conditioning Acquisition P protezione Protection ADC chain DAC chain 16/04/ ATLCE - D DDC 2016 DDC 3

4 Complete ADC chain Input protection circuits Block signals which may damage the other circuits Amplifier Make signal level compatible with ADCF input range Optimize SNRq Anti-alias filter Makes signal bandwidth compatible with sampling rate Multiplexer (for multiple channel systems) Sample/Hold or Track Hold Sampling (discretize in the time axis) A/D Converter Quantization (discretize in the amplitude axis) 16/04/ ATLCE - D DDC 2016 DDC 4

5 Multiple channel system Control signals 16/04/ ATLCE - D DDC 2016 DDC 5

6 Input protection circuits Signal from the field: Electrostatic charges EMI, noise Direct contacts (unplanned) Need to limit input voltage within safe limits, to avoid damage to the system Input protection circuits Diode clamp Special devices (zener diodes, varistor, ) 16/04/ ATLCE - D DDC 2016 DDC 6

7 Input operating range The safe (no damage) input range Vi MAX -Vi MIN depends from the power supply Val. Vi MAX V V AL+ With power off, Val = 0!! Vi MIN V AL- 16/04/ ATLCE - D DDC 2016 DDC 7

8 Amplitude limiter A unit with nonlinear (clipping) transfer function limits input voltage between Vmax and Vmin Vmax Vmax V i Vmin Vmin Vi 16/04/ ATLCE - D DDC 2016 DDC 8

9 Amplitude limiting circuit Clamp towards power supply V AL+ V OUT limited between Val+ and Val- V IN V OUT V AL- Zener diodes to GND V IN V OUT V OUT limited to zener voltage GND Specific devices V OUT limited by V(I) of Z V IN GND Z V OUT In all circuits, the resistance R limits the input current when the protection is active 16/04/ ATLCE - D DDC 2016 DDC 9

10 Test: design of protection circuit Design R for a Zener protection circuit with the following specs: protection from contacts towards ± 500 V, any duration maximum zener power dissipation 5 W Evaluate value and power of R V IN V OUT GND 16/04/ ATLCE - D DDC 2016 DDC 10

11 Lesson D4: signal conditioning Protection circuits Differential and instrumentation amplifiers Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 16/04/ ATLCE - D DDC 2016 DDC 11

12 ADC input dynamic The A/D converter has an input dynamic range unipolar: 0... S, 0 5 V, 0 10 V bipolar: -S/2 + S/ V, V To get maximum SNRq the signal must fill all the usable input dynamic range amplifier (o attenuator) level shifter (bipolar/unipolar) Match signal level to system (ADC) dynamic range 16/04/ ATLCE - D DDC 2016 DDC 12

13 Signal types The ADC accepts specific signal types voltage or current (V/I) single ended or differential (S/D) The unit which matches the dynamic range and the signal type is the conditioning amplifier Many configurations: V V, V I, I I, I V S S, S D, D S, D D 16 choices + gain! 16/04/ ATLCE - D DDC 2016 DDC 13

14 Voltage amplifier Single-ended voltage amplifier Op. Amp. With feedback A V high Zi V V U» Rs does not affect A V»low Ru» Rc does not affect A V I R R Rs V S V d + V I - A d V E R 1 R 2 V U Rc 16/04/ ATLCE - D DDC 2016 DDC 14

15 Transresistance amplifier Current-to-voltage converter V U I R I M I M R M I I I- - I I V d + A.O. V U 16/04/ ATLCE - D DDC 2016 DDC 15

16 Single-ended and differential signals single-ended signal noise Signal + noise Differential signal noise (common mode) Differential signal 16/04/ ATLCE - D DDC 2016 DDC 16

17 Differential signals Differential signals are protected from common mode noise Differential signals do not emit noise Some transducers have differential outputs Fast A/D converters operate with differential input signals To handle differential signals: Single-ended / differential converters Differential amplifiers Instrumentation amplifiers 16/04/ ATLCE - D DDC 2016 DDC 17

18 Common mode rejection A differential amplifier must : Amplify differential signals by a known amount A D Keep common mode signals at a low level: low A C ( 0) The key parameter is the A D /A C ratio A D /A C CMRR (Common Mode Rejection Ratio) Ideal: CMRR 16/04/ ATLCE - D DDC 2016 DDC 18

19 Differential and common mode signals V U = A 1 V 1 -A 2 V 2 = A D V D + A C V C V U = A D (V 1 -V 2 ) + A C (V 1 +V 2 )/2 V D = V 1 -V 2 V C = (V 2 + V 1 )/2 V 1 = V C + V D /2 V 2 = V C -V D /2 V U = (A D + A C /2)V 1 -(A D -A C /2)V 2 A D = (A 1 + A 2 )/2 A C = A 1 -A 2 V D /2 V 1 V D /2 A D, A- C A 1, A+ 2 V U Differential amplifier: A C = 0, therefore A 1 = A 2 V C V 2 16/04/ ATLCE - D DDC 2016 DDC 19

20 Differential amplifier R3 R1 R4 R2 A C = Vu/V C = 0 Zero common mode gain. V D /2 A D, A C A 1, A 2 R3 V 1 R1 - V U A D = Vu/V D = -R3/R1 The circuit amplifies only differential signals V C V D /2 V 2 R2 R4 + AO CMRR 16/04/ ATLCE - D DDC 2016 DDC 20

21 Effects of source impedance Rs Functional specification: Differential amplifier with high CMRR Real-world transducers have equivalent resistance Rs If Rs1 Rs2, no symmetry in classic differential amplifier A purely common signal (Vs1 = Vs2) generates a differential component, which is amplified Worse CMRR Need for high Zi, to remove effects of Rs unbalance Add voltage followers at both inputs Merge VF to get gain, reduce offset, lower noise instrumentation amplifier 16/04/ ATLCE - D DDC 2016 DDC 21

22 Standard differential amplifier Z V I1 1 R1 V S1 R1 Rs1 R1 Rs1 Z I1 R1 R3 Z V I2 2 R2 R4 V S2 R2 R4 Rs2 R2 R4 V S1 Rs2 V S2 V 2 Z I2 R2 V 1 - R4 + AO V U If Rs1 Rs2, gains are no longer balanced A common mode signal (Vs1 = Vs2) becomes differential (V1 V2) and is amplified. Worse Common Mode Rejection (CMRR) 16/04/ ATLCE - D DDC 2016 DDC 22

23 Symmetric input impedance Voltage followers increase input impedance A = 1 high Ri low Ru R3 R1 R4 R2 A D Rs1 V S1 V 2 Rs2 V S2 V V 1 R1 - + V 2 R2 R4 R3 AO This circuit provides high Zi on both inputs; no partition of Vs with Rs Balanced for any value of Rs 16/04/ ATLCE - D DDC 2016 DDC 23

24 Instrumentation amplifier Moving gain into the first stage reduces total noise and offset R7 R5 V R3 V' (V 2 2 R3 R1 V' V 1) 2 1 R4 R2 R5 R6 1 R6 V R5 R7 V 1 R1 - + V 2 R2 R4 AO V U V U (V 2 R5 V 1) 2 R6 R3 1 R1 16/04/ ATLCE - D DDC 2016 DDC 24

25 From single-ended to differential Two amplifiers with the same Av Inverting: Av = - R2/R1 Noninverting: Av = R3/R4 + 1 Vu = Vs(R3/R4 +1 -R2/R1) Problems: Different delay in the two paths Requires many precise R V S R R 2 R 3 V U Better solution: Fully differential circuits Op. Amp. with differential output R 4 16/04/ ATLCE - D DDC 2016 DDC 25

26 Fully differential amplifier High frequency A/D conversion (RF band 120 MHz) From Op Amps for everyone, Texas Instruments, SLOD006B 16/04/ ATLCE - D DDC 2016 DDC 26

27 Lesson D4: signal conditioning Protection circuits Differential and instrumentation amplifiers Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 16/04/ ATLCE - D DDC 2016 DDC 27

28 Anti-alias filter Every signal has a nominal bandwidth (where usefuln information is contained), but inludes also outband components (noise, distortion, ) Even sampling within the Nyquist rule (higher than twice the bandwidth), outband signals are folded inside the useful band, and cause Aliasing noise The aliasing noise depends on two parameters: Shape of outband spectrum Sampling rate 16/04/ ATLCE - D DDC 2016 DDC 28

29 Inband folding of signal spectrum Out-band signal folded by sampling into the useful band Quantization noise Reconstruction filter mask 16/04/ ATLCE - D DDC 2016 DDC 29

30 Aliasing noise f B = useful bandwidth (also reconstruction filter bandwidth): f S = sampling rate: The signal from f B /2 to f B is folded in the useful band aliasing noise Aliasing noise: overlap of baseband and aliased spectra X S (ω) Main spectrum (baseband) f S /2 f B Secondary spectra (alias) f S f 16/04/ ATLCE - D DDC 2016 DDC 30

31 Example of aliasing noise Ideal signal: No outband power No aliasing X S (f) f F B FS /2 F S Real signal: Outband power Some aliasing X S (f) Amount of aliasing depends on F B F S -F B F S f Signal (outband power) Filter (outband attenuation) Folded in band noise aliasing noise 16/04/ ATLCE - D DDC 2016 DDC 31

32 Anti-alias filter design - simplified Signal/(aliasing noise) SNR A Level of outband signal: S Filter: Attenuation SNR A db at f S -f B ; no attenuation at f B From f B to f S -f B frequency ratio R = (f S -f B )/f B Same attenuation R by a single pole RP attenuation if P poles (P x R(dB)) Another approach: A single pole: _ 6 db/octave [20 db/decade] From f B to f S -f B attenuation Ap Ap(dB) = 6 * log 2 (f S -f B )/f B db [or = 20 * log 10 (f S -f B )/f B ] Required number of poles: P = SNR A / Ap 16/04/ ATLCE - D DDC 2016 DDC 32

33 Anti-alias filter design - complete Near cutoff, filters can drop faster than 20dB/dec The actual attenuation depends also from filter type Bessel, Butterworth, Chebischeff, Elliptic, The required number of poles can be evaluated using proper design tools e.g. FILTERCAD, by Linear Technology, free on website 16/04/ ATLCE - D DDC 2016 DDC 33

34 Reducing aliasing noise Lower outband signal level More steep input filter (more expensive) Increase sampling rate Fs (oversampling) Moves alias spectra away from baseband Brings also higher sample rate (more expensive) Oversampling A/D chain Anti alias input filter (analog, simple) High rate sampling Fast A/D conversion --> high bit rate Bit rate reduction with digital filter (decimation) Move complexity analog digital domains 16/04/ ATLCE - D DDC 2016 DDC 34

35 Lesson D4: signal conditioning Protection circuits Differential and instrumentation amplifiers Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 16/04/ ATLCE - D DDC 2016 DDC 35

36 Multiple channels system multiplexer Control signals 16/04/ ATLCE - D DDC 2016 DDC 36

37 Multiplexer Allows to use the same functional units (S/H and A/D) for several channels Must select one channel among N Must not modify the selected signal Must block other channels Multiplexer parameters Equivalent series resistance Ron Leakage current Ioff Insulation/feedthrough Settling time Input range.. 16/04/ ATLCE - D DDC 2016 DDC 37

38 Multiplexer structure Switches built with MOS (or CMOS) transistors Decoding and command circuits SW Select V Ii V U 16/04/ ATLCE - D DDC 2016 DDC 38

39 Multiplexer error sources MOS switch model ON: resistor Ron OFF: leakage current Ioff + parallel capacitor Cds ON channel Partition from Vi to Vo caused by Ron OFF channels Offset caused by leakage currents of open switches Feedthrough from other channels (through Cds) Dynamic parameters Switching delay Bandwidth (RC low-pass cells) 16/04/ ATLCE - D DDC 2016 DDC 39

40 Ron error V S R S SW VU Only one switch is closed (ON) to select the input channel V S connected to V U ouput. A ON switch has an equivalent resistance R ON. R S R ON From V S to V U the gain is < 1, due to the voltage divider made by the load resistance R L. V S R L V U 16/04/ ATLCE - D DDC 2016 DDC 40

41 Ioff error V S I OFF VU Only one switch is closed (ON) to select the input channel V S connected to V U ouput. All other switches are open (OFF). Any OFF switch has a leakage current I OFF. R S R ON The sum of all I OFF causes an offset voltage V UOFF at the output. I OFF R L V UOFF 16/04/ ATLCE - D DDC 2016 DDC 41

42 Frequency limit V S R S R ON C P V U The parasitic capacitance of multiplexer and load limit the transferred signal bandwidth. The signal path includes the lowpass cell R ON / C P. The Cgd and Cds parasitic capacitances generate respectively pedestal and feedthrough errors (as in S/H circuits). 16/04/ ATLCE - D DDC 2016 DDC 42

43 Where to place the multiplexer The multiplexing operation changes the signal spectrum Example: two DC signals become squarewave The mux must be placed after the filter S/H and ADC can be used on many channels (each sampling and conversion is independent from previous values) the filter cannot be used on multiple channels (keeps track of previous signal values) 16/04/ ATLCE - D DDC 2016 DDC 43

44 Lesson D4: signal conditioning Protection circuits Differential and instrumentation amplifiers Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 16/04/ ATLCE - D DDC 2016 DDC 44

45 Sample-Hold unit Function: sample the input analog signal I(t) Sampling at t = ts multiply input signal by δ(ts) Keep the sample value at the output (O) as long as required for A/D conversion: HOLD operation I(t) O(t) t t S1 t S2 16/04/ ATLCE - D DDC 2016 DDC 45

46 Track-Hold operation Actual circuits behavior Before the next sampling operation the circuit must acquire the new value The complete sequence is» Tracking: O(t) = I(t)» Sampling: O = I(ts)»Hold: O(t) = I(ts)» New tracking I(t) O(t) t t S1 t S2 16/04/ ATLCE - D DDC 2016 DDC 46

47 Track-Hold operation sequence Track Sample Hold Acquisition output = input reading the analog signal value transition from Track to Hold constant output, corresponding to sampled value the ADC operates during this phase transition from Hold to Track track hold track sample Acq. sample hold Acq. 16/04/ ATLCE - D DDC 2016 DDC 47

48 Basic Circuit: Track and Hold state The Sample/Hold is an analog memory capacitor switch Track: SW ON Hold: SW OFF T H T H T 16/04/ ATLCE - D DDC 2016 DDC 48

49 Tracking phase During tracking Vu = Vi: The S/H is a unity-gain amplifier (or K-gain) Static errors Gain, offset, (nonlinearity) Dynamic parameters and errors Bandwidth» Defines signal which can be tracked Settling time» Depends on Slew Rate & required precision» Non-linear behavior 16/04/ ATLCE - D DDC 2016 DDC 49

50 Tracking: gain error R ON Partition of Vi between Rg/Ron and R L Gain error Lowpass RC cell Bandwidth limit Settling time for transient response Offset, nonlinearity, 16/04/ ATLCE - D DDC 2016 DDC 50

51 Tracking: step response Step Vi input Output Vo with II order transient Steady state error Settling time 16/04/ ATLCE - D DDC 2016 DDC 51

52 Sampling transient errors Time error Delay in SW opening aperture delay: t A Delay changes aperture jitter: t JA Sampling jitter: ΔV JA = t JA * SR max T H settling time t S Amplitude errors: Pedestal: charge injection through the SW ΔV P = ΔVc Cp/(Cp+Cm) V JA V P Track Hold t A t JA V C Settling time t S < quantization error ADC can start here 16/04/ ATLCE - D DDC 2016 DDC 52

53 Sampling jitter The S H transition occurs after an aperture delay T A T A is not constant; is affected by a noise: T J sampling jitter The sampling jitter causes an amplitude error V = T J * max slew rate with sine signal: V = T J ω V = T J ω S/2 With full scale sine signal at ω = 2 п F A : SNRj = Ps/Pj = (S 2 /8)/(T J ω S/2) 2 /12 [sine/triangle distribution] SNRj = 1.5 (T J п F A ) log 10 (T J п F A ) (db) 16/04/ ATLCE - D DDC 2016 DDC 53

54 Sampling jitter: example Sampling jitter is caused by switch command noise and clock jitter A critical parameter for digital radio systems To be evaluated independently from sampling rate Numeric example: max T J to sample 300 MHz signal with SNRj = 82 db? SNRj = log 10 (T J п F A ) = 82 db 20 log 10 (T J п F A ) -80 db log 10 (T J п F A ) = -4 T J п F A = 10-4 T J = 10-4 / п 300 MHz T J = 10-4 ns = 0.1 ps (100 fs) 16/04/ ATLCE - D DDC 2016 DDC 54

55 Sampling: pedestal error C C Partition of the Gate command signal between Cc and Cm Pedestal error ΔVp = ΔVc Cc/(Cc+Cm) 16/04/ ATLCE - D DDC 2016 DDC 55

56 Pedestal compensation Switch built with complementary MOS devices Compensation of pedestal error a) Complementary transistor b) Dummy device 16/04/ ATLCE - D DDC 2016 DDC 56

57 Basic circuit: hold errors The charge stored on the capacitor changes Decay error Poor isolation of input signal Feedthrough error Dielectric polarization Slow change of stored voltage (long term effect) Decay Ideal Hold Decay and feedthrough 16/04/ ATLCE - D DDC 2016 DDC 57

58 Decay error Switch OFF: Vo(t) = V i(ts) Output = voltage previously stored on the capacitor The capacitor discharges through R L and I OFF (leakage) Decay error 16/04/ ATLCE - D DDC 2016 DDC 58

59 Feedthrough error C P Switch OFF: Vo(t) = V i(ts) Output = voltage previously stored on the capacitor Input signal partitioned between Cp and Cm Feedthrough error 16/04/ ATLCE - D DDC 2016 DDC 59

60 Acquisition The output reaches the input (within the specified precision) after the acquisition time Tacq Depends on bandwidth slew rate Acquisition time Error band S H S H 16/04/ ATLCE - D DDC 2016 DDC 60

61 Error handling Decay Increase Cm Isolate load Pedestal Low parasitics Increase Cm Compensate with opposite sign pedestal Feedthrough Low parasitics Increase Cm Gain and offset Use feedback circuits 16/04/ ATLCE - D DDC 2016 DDC 61

62 Pedestal, feedthrough, Hold capacitor Feedthrough: partition of Vi between C DS and Cm Pedestal: partition of Vg between C GD and Cm Decay: discharge of Cm on the load and for switch leakage Z L 16/04/ ATLCE - D DDC 2016 DDC 62

63 Selecting the hold capacitor Cm General rule to reduce decay, pedestal, feedthrough: Reduce parasitic capacitance» selection of MOS switch Increase the hold capacitor Cm Acquisition time depends on the hold capacitor Cm With increase of Cm» Errors are reduced»t ACQ increases Most integrated S/H have basic Cm (low value) inside, with a pin to add external capacitors to increase Cm» Proper selection to limit dielectric polarization errors (long term memory of the dielectric material) 16/04/ ATLCE - D DDC 2016 DDC 63

64 Input output isolation Two voltage follower isolate input source and load Floating switch Complex command» Higher feedthrough and pedestal To avoid sum of gain and offset errors Move feedback to get a unique voltage follower 16/04/ ATLCE - D DDC 2016 DDC 64

65 Integrator S/H Single feedback loop Reduced gain and offset errors Switch with one side tied to ground simpler command 16/04/ ATLCE - D DDC 2016 DDC 65

66 Lesson D4: signal conditioning Protection circuits Differential and instrumentation amplifiers Anti-aliasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 16/04/ ATLCE - D DDC 2016 DDC 66

67 Total error An ADC system includes several functional units Each unit introduces errors and noise Amplifier: Gain, offset, nonlinearity, band limits Filter: outband signal SNRa Sample/Hold: sampling jitter SNRj A/D converter: quantization SNRq. Actual accuracy depends from all these elements not just the bit number N of the ADC How to define / evaluate the total error? 16/04/ ATLCE - D DDC 2016 DDC 67

68 Total SNR Key parameter: total Signal/Noise ratio: SNR t SNR t comes from several sources: Quantization, aliasing, sampling jitter, Conditioning chain errors (linear) Independent variables Maximum error/noise voltage add voltages: Vnmax = Vni Total error/noise power Pnt add power: Pnt = Pni Compute SNR t 1 SNR t P P nt s 10 log P P ni s ; for each term: P P ni s 10 SNR 10 i 16/04/ ATLCE - D DDC 2016 DDC 68

69 Effective Number of Bits: ENOB SNR t can be expressed as Equivalent Number Of Bits (for sine signal) Computed from SNR t (depends on signal level; usually measured or evaluated with full-scale sine input signal) ENOB = (SNR t - 1,76)/6 = SNR t /6-0,3 Includes all noise/error sources (quantization, aliasing, sampling jitter, ) Represents the number of actually useful bits of the A/D conversion system 16/04/ ATLCE - D DDC 2016 DDC 69

70 Lesson D4 test questions Draw a circuit suitable as input protection in a A/D system. How can the aliasing noise be reduced? Which are the benefits of differential signals? Which errors can be introduced by a multiplexer? Describe the sequence of states in a Sample/Hold. Which is the relation between sampling jitter error and signal frequency? Which are the benefits and drawback of increasing the memory capacitor in a S/H circuit? Which parameter best describes the actual precision of a A/D conversion system? 16/04/ ATLCE - D DDC 2016 DDC 70