Telecommunication Electronics

Transcription

1 Test 1 In this amplifier C1, C2 and C3 have negligible impedance at the operating frequency. R1 = 82k R2 = 27k RL = 22 k Re =?? Rc =?? Val = 15 V hfe > 500 Vi C1 R1 R2 I1 Rc Re Ve C3 C2 RL V AL Vu a) Find the value of Re required to get a collector current Ic = 0,4 ma, and find the peak-topeak output dynamic range ΔVuv without the load RL. (assume Vcesat = 0,3V). Vbase = Val R2/(R1+R2) = 15 x 27 / 109 = 3, 71V; Ve = 3,11 V Re = Ve/Ie = 3,11/0,4 = 7,79 kω ΔVuv = Val (Ve + Vcesat) = 15 3,41 = 11,59 V [Val = 12V: b: Ve = 2,37V, Re = 5,93 kω, ΔVuv = 9,33V] b) Connect the load RL (through C2). Find the value of Rc which provides, from the DC operating point, symmetric excursion on Vu. Evaluate the gain Av = Vu/Vi with linear transistor model, and evaluate the new peak-to-peak output dynamic range ΔVul. Voltage drop on Rc: Vrc = ΔVuv/2 = 11,59/2 = 5,8 V Rc = Vrc/Ic = 5,8/0,4 = 14,5 kω Actual collector load Rc = Rc//RL = 15,5//22 = 8,74 kω gm = Ic/Vt = 0,4/26 = 15,38 ma/v Gain: Av = - gm Rc = 15,38 x 8,74 = - 134,4 ΔVul = ΔVuv RL /(Rc+RL) = 11,59 x 22 / 36,5 = 6,98 V [Rc = 11,66 kω, Rc = 7,62 kω, gm = 15,38 ma/v, Av = - 117,2, ΔVul = 6,09 V] DDC -TLCEscris911d.doc - 23/11/ :03:00 1

2 c) Evaluate the amplitude (in V or mv) of the fundamental Vu component, with Vi = 10 mvrms, taking into account the nonlinearity of BE junction. (use linear interpolation for intermediate values of x) 10 mvrms 14,14 mvpeak X = 14,14/26 = 0,544 (x = 0,5 is acceptable approximation, more precise results require linear interpolation) Gm(0,5) = 15,38 x 0,485/0,5 = 14,92 ma/v Gm(1) = 15,38 x 0,8928 = 13,73 ma/v Interpolation: ΔGm = (14,92 13,73) x 0,044/0,5 = 0,104 Gm(0,544) = 14,92-0,104 = 14,82 ma/v Vu(ωi) = Vu(ωi) Rc Gm(0,544) = 10 x 8,74 x 14,82 = 1,295 Vrms 1,826 Vpeak [1,129 Vrms, 1,803 Vpeak] d) Modify the circuit to get a gain Vu/Vi = 3 (+- 5%), with the same load RL. The best technique is to add emitter feedback with a new Re1 resistor (not bypassed by the capacitor C3). First approximation: Av = Rc /Re1 ; Re1 = Rc / Av = 8,74/3 = 2,91 kω [2,54 kω] More correct: Av = hfe Rc / (hei + (hfe+1)re1) ; Re1 = 2,84 kω [2,45 kω] e) Add a LC resonant circuit with Q = 100 in parallel to Rc; evaluate the ratio between the fundamental component and the second harmonic for the collector current Ic and for the output voltage Vu (in dbc, use 0dB for the fundamental component). Assume x = 0,5; I1/I2 = 0,124 18,1 db (ratio for Ic components) X = Q k 1/k = 100 x 1,5 = ,5 db (attenuation of LC tuned circuit) Total ratio for Vu components: 18,1 + 43,5 = 61,6 db [Q = 120: 45,1 db, 63,2 db] Most common mistakes - evaluate Rc from the full Vu swing (Rc = ΔVuv /Ic) - reduce the gain lowering Rc or RL (more power, no precise gain) - evaluate gain considering Re - amplitude of fundamental in db DDC -TLCEscris911d.doc - 23/11/ :03:00 2

3 Test 2 The VCO of a PLL operates from 90 to 110 MHz. The Phase Detector is a CMOS XOR gate with Vdd = 2,5V. The VCO has central frequency For = 100 MHz, gain Ko = 40 MHz/V, 10 kω input impedance at the Vc input. The loop filter is a RC cell, with R = 3 kω. a) The PLL is used to generate the reference signal for a single-branch synchronous AM demodulator. Find the maximum error (% of full scale) at the AM output when the input signal frequency moves over the operating range. Maximum frequency shift (lock range) ΔFol = 10 MHz [R = 5 k] Required control voltage to the VCO ΔVcl = ΔFol/Ko = 10/40 = 0,25 V Actual required Vd, taking into account the voltage divider with VCO input resistane: ΔVdl = 0,25 x 13/10 = 0,325 V [0,375 V] Kd = 2,5/п = 0,795 V/rad At the ends of the operating range: θe = Vd/Kd = 0,325/0,795 = 0,408 rad AM demodulator output Eam = 1 cos θe = 1 0,917 8,3% [10,9%] b) Find the filter DC gain F(0) required to get a maximum phase error er <= 0,1 rad over the operating range. Draw the diagram of the loop filter (use an Operational Amplifier). To reduce θe from 0, 408 to 0,1, the loop gain must be increased by a factor 4,08; this is the gain of the amplifier, if placed before the RC filter cella. If the amplifier is after the cell, or if the amplifier includes the low pass loop filter, the low output impedance removes the voltega patition with VCO input resistance; the gain can be reduced to 4,08 x 10/13 = 3,138. A suitable choice for the filter amplifer is a noninverting voltage amplifier with Op Amp. DDC -TLCEscris911d.doc - 23/11/ :03:00 3

4 c) The VCO has linear fo(vc) characteristic. Find the position of the loop filter pole which gives a capture range, with the amplifier, from 95 to 105 MHz. Two solutions are given: both are accepted in the written test. Case 1 The change of control voltage to reach the ends of the range is ΔVcm = 10 MHz/40 = 0,25 V The voltage required to move the VCO to the ends of the capture range is ΔVcc = 5/40 = 0,125 V The filter must divide Vd by 2 for Fi Fo = 5 MHz pole at 2.5 MHz Case 2 When the loop is not locked, the voltage change at Vd can reach 2,5/2 = 1,25 V, which is further amplified by the filter (gain 3,136). The max Vc voltage is 3,92 V. Capture is achieved when the VCO receives a control voltage change Vcc = 0,125 V. To get this valua with a input frequency 5 MHz, the loop filter must have a pole at Fp = 5MHz x 0,125 / 3,92 = 159 khz d) Insert at the inputs of the PD two frequency dividers (respectively :M and :N), and find the M, N values to be used for a frequency synthesizer in the range MHz, with resolution 1 khz, using a reference frequency 100 MHz. Discuss (qualitatively) the VCO settling time. The frequency resolutionof a synthesizer corresponds to the PD input frequency. In this case ve weed: - a divider by on the Fr path (100 MHz 1 khz) - a divider programmable from to in the VCO-PD path. The loop filter must be designed for the input frequency 1 khz, and may have rather long settling time. Fractional synthesizer architecture can be used to increase the settling speed. Most common mistake - not take into account voltage partition caused by VCO input impedance -.. DDC -TLCEscris911d.doc - 23/11/ :03:00 4

5 Test 3 An A/D conversion system has 16 input channels; each channel has bandwidth from DC to 20kHz, and flat spectral power density till at least 1 MHz. The ADC has 12-bit output, and uses four flash A/D converters, each with 3-bit resolution and 90 ns conversion time, and D/A converters with 50 ns settling time, connected in a residue configuration (no pipeline). The S/H acquisition time Tacq is 100 ns. a) Draw the block diagram of the complete A/D converter, specifying the precision required for each basic block (ADC+DAC); draw the block diagram of a single ADC block, and evaluate the total number of comparators (for the 12-bit ADC). Find the maximum conversion rate of the S/H-ADC combination (Fc), and the maximum sampling rate (Fs) achievable on each channel. Block diagram of complete residue ADC from slide Diagram of single block (3-bit flash ADC) from slide. Precision from MSBs unit: 12, 9, 6, 3 bits Total conversion time Tc = 4 x T(ADC) + 3 x T(DAC) + S/H = 4 x x = 610 ns Maximum conversion rate Fc = 1/Tc = 1,64 Ms/s Maximum sampling rate for each channel Fs = Fc/16 = 102 ks/s b) The input anti-alias filters have cutoff frequency 25 khz and 7 poles; find the aliasing noise amplitude Ea and the signal-to-aliasing noise power ratio (SNRa), for sampling rate 100 ks/s, triangular input signals. The frequency which is folded into baseband by sampling is = 80 KHz. A single pole from 25 khz to 80 khz has a attenuation 80/25 = 3,2 10,1 db The total drop is SNRa = 10,1 x 7 = 70,7 db (voltage ratio) The corresponding amplitude error is Ea = S/3.428k 0,292 S 10^-3 (peak-to-peak) c) Evaluate the total ENOB, considering only quantization and aliasing errors. SNRq = 6 N + 1,76 = 73,76 db SNRa = 70,7 db 23,768 10^6 power ratio 11,749 10^6 1/SNRt = (1/23,77 + 1/11,75) 10^-6 = 0,127 10^-6-68,96 db ENOB = (68,96 1,76)/6 = 11,14 DDC -TLCEscris911d.doc - 23/11/ :03:00 5

6 d) Evaluate the max S/H sampling jitter Tja to get a sampling jitter error Eja equal or les than ¼ the quantization step, for full scale sine input signals at the maximum allowed frequency. The maximum sampling jitter error is Eja = Tja x SRmax Eq = S/2^12 = S/4k; ¼ Eq = S/16k SRmax = V = 20k x 2п x S/2 = 62,8 k S Tja = (1/16k)(1/62,8k) = 1/1 G = 1 ns (approximated) SNRa = 12 x = 84 db e) Find the clock rate Fck required to get the same SNRq with a differential A/D for each channel (1-bit differential converter, no adaptation), and define the specs of the antialias filter for this ADC. Quantization step for the Nyquist ADC: Quantization step for the differential ADC: S/2^12 = S/4k γ Maxi input for the differential ADC: V = γ/ω Tck = γ Fck / ω = S/2 γ = V / ω S/2 Fck = S/2^N Fck = ω 2^N / 2 = 257,3 MHz Most common mistakes - mistakes in the ADC block diagram - DDC -TLCEscris911d.doc - 23/11/ :03:00 6