Analog & Telecommunication Electronics

Transcription

1 Problem 1 A [data and solution case B] In this amplifier C2 can be considered an open circuit, while C1, C4 and C3 have negligible impedance at the operating frequency. R1 =?? R2 = 68 k [82k] Re1 + Re2 = 8 k Rc =?? RL = 20 k Vcc = 15 V hfe > 500 Vi C1 R1 R2 I1 Rc Ve C2 C3 Re1 Re2 V CC RL C4 Vu a) Find the value of R1 required to get a collector current Ic = 0,5 ma (assume Vbe = 0,6V); select a suitable standard (E12) value, and find the actual Ic (to be used in the following). Evaluate the p-to-p output dynamic range without the load RL ( Vuv), with Vcesat = 0,2V. Select Rc to get symmetric Vco. Due to the high current gain β = hfe: Ie = Ic = 0,5 ma; Ib 1 μa; first step can be an approximated solution with Ib =0: Ve = Ie (Re1+Re2) = 0,5 ma x 8 kω = 4 V To get Ic = 0,5 ma: Vb = 4 + 0,6 = 4,6 V = Vbb Vbb Rb I1 Ve Re1 Re2 Vbb = Vcc R2 / (R1 + R2); R1 = (Vcc Vbb) R2 / Vbb = (15-4,6) 68kΩ / 4,6 = 153 kω E12: R1 = 150 kω [180k] (150 kω acceptable) (drop Vrb on Rb: 68k//150k x 1 μa = 47k x 1 μ = 47 mv, negligible, compared with Vbb) Actual Ic with R1 = 150 kω: Ic = (15 68 / (150+68) 0,6)) / 8 = 0,504 ma. No load output dynamic range: Vuv from Vcc to (Ve+Vcesat) Ve = Vb 0,6 = 4V; Vcesat = 0,2V; Vco = 15 (4+0,2) 10,8 V Drop on Rc: Vrc = Vcv/2 = 5,4 V; Rc = Vrc/Ic = 5,4/0,504 = 10,7 kω E12 value: Rc = 10 kω (used in the following, but also 12 kω is acceptable) BJT parameters: hie = Vt hfe / Ic = 26 mv x 500 / 0,504 ma = 25,8 k gm = Ic/Vt = 0,504/26 = 19,38 ma/v ; 1/gm = 51,6 Ω (hie or gm are needed for the following questions) b) Find the value of Re1 which provides a gain Av = Vu/Vi 20, with the load RL (use linear transistor model and the E12 value from a) for Rc). The gain of a CE amplifier can be approximated as Av = - Zc/Ze; Zc = Rc//RL = 10//20 = 6,67 kω Av = 20, therefore Re1 = 6,67/20 = 333 Ω (upper bound). Vi = Ib hie + Ib Re1 (hfe+1); Ib = Vi/(hie + Re1(hfe+1)) Vu = - hfe Ib Zc = - hfe Zc Vi/(hie + Re1(hfe+1)) Vi R1 //R2 Ib hie Re 1 hfe Ib Rc Vo RL Av = Vu/Vi = hfe Zc / (hie + Re1(hfe+1)); Av (hie + Re1(hfe+1)) = hfe Zc Re1 = (hfe Zc - Av hie) / ( Av (hfe+1)) = (hfe Zc - Av Vt hfe/ic) / ( Av (hfe+1)) Since hfe >> 1, Re1 = (Zc - Av Vt/Ic) / ( Av ) = Zc/ Av - 1/gm Re1 = ,6 = 281 Ω since the specification is for minimum gain, we must take the lower standard value: Re1 = 270 Ω DDC -ATLCEscris160718k.doc - 21/07/ :15:00 1

2 c) Draw the spectrum (in dbc) of the collector current Ic and of the output signal Vo with C4 connected directly to the emitter, sine input Vi = 100 mvrms, taking into account the nonlinearity of BE junction. To get peak value from rms, multiply by SQRT(2) Vi = 100mVrms 141,4 mvpeak. Normalized input amplitude: x = Vi/Vt = 5,43 Value not in the table; can be approximated with 5, or interpolation 5-7 (better) II harmonic: x = 7: I2/I1 = 0,795 (R7) x = 5: I2/I1 = 0,719 (R5) x = 5,43; I2/I1 = R(5) + (R(7)-R(5)) x 0,43/2 = 0, ,076 x 0,215 = 0,735-2,67 dbc; III harmonic: x = 7: I3/I1 = 1,0104/1,8511 = 0,546 x = 5: I3/I1 = 0,7585/1,7868 = 0,424 x = 5,43; I3/I1 = R(5) + (R(7)-R(5)) x 0,43/2 = 0, ,122 x 0,43/2 = 0,450-6,93 dbc; Since the load is resistive, the collector current Ic and the output voltage Vo have the same spectral content. d) Rc is replaced by a LC circuit, with resonant frequency ωi and Q = 150 [250] (includes the effects of load RL). Evaluate in dbc the level of the highest spurious in the output spectrum. The overall spectrum comes form the harmonic content caused by nonlinearity and the frequency response of the Collector impedance (the tuned circuit). In this case the highest spurious is the II harmonic. III harm. has lower level and higher attenuation from the resonant circuit. Collector current Ic ratio II harm/fundamental (from question b): 0,735-2,67 db Attenuation II harm (by the tuned circuit): X = Q k 1/k = 150 x 1,5 = db Total level of II harm: ,67 = - 49,7 dbc [54,1 dbc]. DDC -ATLCEscris160718k.doc - 21/07/ :15:00 2

3 Problem 2 A [data and solution case B] An ADC system has 8 input channels with bandwidth from DC to 100kHz, and flat spectral power density till 1 MHz. The system provides 10-bit output, and uses flash 5-bit ADCs with 70 [60] ns conversion time, and DACs with 30 ns settling time, connected in a residue configuration with pipeline. The S/H acquisition time Tacq is 90 [80] ns. a) Draw the block diagram of the complete A/D converter, specifying the precision required for each basic block (ADC+DAC); Find the maximum sampling rate of the S/H-ADC combination (Fr), and the maximum conversion rate (Fs) achievable on each channel. Block diagram in the text page 256 (single-bit stages), and in slides D3 70 (multibit residue). Interstage amplifier gain: 2^5 = 32. Total number of comparators: (2^5 1) x 2 = 31 x 2 = 62. The precision required by ADCs and DACs depends from the position in the chain. To evaluate correctly the residue, the cell that evaluates MSBs must have a precision corresponding to full resolution (10 bits). Second stage requires 5-bit precision. To get the complete result each sample must go through the complete chain; for each 5-bit flash ADC the timing specifications are: S/H acquisition time Taq 90 ns 90 ADC conversion time Tc 70 ns 70 DAC settling time Tst 30 ns 30 Tct = 190 [170] ns (single stage) Due to the pipeline structure, this is also the equivalent total conversion time, but the result is available after a Latency time Tlat = Tct + Tacq + Tc = 350 ns. The maximum sampling rate of the ADC+S/H system is Fr = 1/Tct = 1/190ns = 5,26 [5,88] Ms/s; for a single channel the maximum sampling rate is Fsmax = 5,26/8 = 657 [735] ks/s Warnng: Multiplexing a multistage pipelined ADC requires proper handling of intermediate results to rebuild the correct result for each sample. b) For a sampling rate Fs = 400 ks/s (on a single channel), and anti-alias filter with cutoff frequency Fc = 100 khz, find the number of poles P required to get a signal-to-aliasing noise power ratio SNRa = 65 db. Discuss how to reduce the number of poles of the input filter. With 400 ks/s sampling rate the frequency range folded into baseband is khz. Therefore we need a 65 db attenuation from 100 to 300 khz. The attenuation of a single pole from 100 to 300 khz is 300/100 = 3 9,54 db. To get the specified 65 db we need at least P = 65/9,54 = 6,8 7 poles. This is a worst-case figure, for anti-alias filter built as a chain of single real-pole cells (order 1). Filters using II order cells with complex pole pairs can provide more steep cutoff, and the same attenuation is achieved with reduced number of poles. To release the specification on input filter the most simple technique is to increase the sampling rate. In this case the ADC can go up to 675 [735] ks/s; with 600 [700] ks/s the 65 db attenuation is required from 100 to 500 khz; single pole 14 db [100 to 600 khz; single pole 15,6 db]; to get 65 db attenuation the filter can use only 5 poles [same for 700 ks/s]. DDC -ATLCEscris160718k.doc - 21/07/ :15:00 3

4 c) Find the sampling jitter Tj required to get a signal-to-sampling jitter noise SNRj = 70 db (with full scale input signal). The jitter error Vj can be evaluated as: Vj = SRmax Tj = 100k 2 π S/2 Tj The jitter error power (flat amplitude distribution) is: Pj = ( Vj)^2/12 = (100k 2 π S/2 Tj)^2/12 Signal power, ffor full-scale sine input: Ps = S^2/8. 70 db correspond to a power ratio 10^7 (voltage ratio 3,16 10^3), SNRj = Ps/Pj = (S^2/8)/((100k π S Tj)^2/12) = 10^7 Tjmax = 1,23 ns d) Evaluate the ENOB, considering quantization, aliasing, and jitter errors. Contributions from different noise sources are: SNRq = 1,76+6N = 61,76 db 1,5 10^6 SNRa = 65 db 3,16 10^6 (min SNRa; with 7 poles will be slightly higher) SNR j = 70 db 10 10^6 Total noise power Pnt = Ps (1/1,5 + 1/3,16 + 1/10) 10^-6 = Ps 1,08 10^-6 SNRt = Ps/Pnt = 0, ^6-0, = 59,68 db ENOB = (59,68 1,76)/6 = 57,9/6 = 9,65 bit This number is very close to the ADC bit number (10) because quantization noise is the main error source (lowest SNR is SNRq) e) Find the clock rate Fckd of a differential converter which provides the same SNRq of the 8 bit flash. The maximum slew rate of a differential converter is SRmax = γ /Tck = γ Fck; To keep the same SNRq the differential step γ must correspond to the quantization interval Ad; in this case (10-bit ADC): γ = S/2^10 To track the input signal without overload error the slew rate must be equal (or higher) than the maximum signal slew rate SRmax. For the 100 khz signal SRmax = 100k 2 π S/2 = 314k S (S/2^10) Fckd = 314k S Fckd = 314k x 2^10 = 321 MHz DDC -ATLCEscris160718k.doc - 21/07/ :15:00 4

5 Problem 3 A [data and solution case B] A Power Supply Unit uses a mains transformer (50 Hz) with Vs = 20Vrms, a full wave rectifier bridge, and a ripple filter with C = 1000 [500] μf. The load sinks a current IL from 0 to 0,6 A. a) Evaluate the DC component Vodc and the ripple Vor for the output voltage Vo, with minimum and maximum load current. Assume a forward voltage drop 1 V on each diode. Evaluate the peak current in the diodes (Idmax), assuming conduction for 1/5 of the halfperiod, and triangular current waveform. Vs = 20 V Vspeak = 28,28 V; with 2 V drop on diodes Vsp = 26,28 V IL = 0: no ripple; Vor = 0, Vodc = 26,28V; IL = 0,6 A: Vor = I t/c = 0,6 10m /1m = 6 [12] Vpp Vodc = Vp Vor/2 = 26,28 3 = 23,28 [20,28]V (Actual Vodc range for IL 0 0,6 A: 23,28 26,28 V) Charge to load in each half-period (10 ms): Q1 = IL T = IL 10ms = 0,6 A x 10 ms = 6 m Charge through diode for T1 = T/5 = 10ms/5 = 2ms. With triangular current shape: Q2 = Idmax 2ms/2. Q1 = Q2 Idmax = 6 A b) Add a voltage regulator at the filter output, with a Zener reference (Vzo=15 [12] V, Rz=18 Ω) and a power BJT (current gain = 25 to 100, Vbe = 0,8V). Assume the regulator input voltage Vi be provided by ideal voltage sources Vor and Vodc of question a). Design R1 to get a minimum current in the Zener Izmin = 5 ma, for the specified range of load currents. Evaluate the output DC voltage Vodc and the ripple Vor with load current IL = 0,6 A. The Zener circuit includes R1 and Dz. R1 must provide the required current to Zener and to BJT Base (Ib) in the worst case, that is with min input voltage and max out current. I O Minimum voltage from rectifier-filter cell: V1min = Vodc- Vor/2 = 23,28 3 = 20,28 [17,28] V (V1min = 20 [17] V in the following). V I R 1 D Z I B V O Vu Max out current max base current required for Q1, evaluated for minimum current gain: Ibmax = 0,6/25 = 24 ma Current in R1 for Iomax: I1max = Ibmax + Izmin = = 29 ma Base voltage: Vb = Vzo + Izmin Rz = x 5 ma = 15,09 [12,09] V R1 = (V1min 15,09)/I1max = 5,14/29 = 179 [75,5] Ω. Closest standard value is 180 Ω, but 179 is a Max value, so a better choice is 150 [68] Ω. Output voltage Vudc = Ve = Vb Vbe; Vb = Vdc Rz/(R1+Rz) + Vzo R1/(R1+Rz) = 15,88 V Drop Vd caused by base current: Req = R1//Rz = 16 Ω ; Vd = Req x Ib = 16 x 24 ma = 0,386 V Considering this drop: Vb = 15,88 0,39 = 15,5V Vudc = 15,5 0,8 = 14,7 [11,3] V Output voltage (Vur) (ripple) Vur = Vir Rz/(R1+Rz) = 6 x 18/168 = 0,643 [2,3] Vpp DDC -ATLCEscris160718k.doc - 21/07/ :15:00 5

6 c) Evaluate the maximum power dissipated on the regulator BJT (ILmax = 0,6A). For Tjmax=150 C and Junction-case thermal resistance Rjc = 6 C/W, evaluate the maximum case-ambient thermal resistance Rca for operation up to ambient temperature Ta = 80 C. The Max power dissipation on the series regulator element (the BJT) occurs when Io = Iomax = 0,6 A and Vin = Vimax = 26,3 V. Since Vin = Vimax only on ripple peaks, power can be evaluated also with reference to Vidc=23,3 V. Pdmax = Vcemax x Icmax T Power on BE junction is 0,8 x 24m 20 mw; not considered J Vcemax = Vin Vo = 26,3 15 = 11,3 V [23,3-15=8,3] Icmax = 0,6 A; Pdmax = 11,3 x 0,6 = 6,78 W Tj = Ta + Pd Rtot ; Rtot = (Tj Ta)/Pd; Rtot = (150 80)/6,78 = 10,3 C /W; Rtot = Rjc + Rca; The max thermal resistance of the heatsink is: Rca = 10,3 6 = 4,3 C /W (slightly different numeric results can be obtained wit different assumptions and approximations) P D R 1 Rjc R Z Rca T C T A d) Replace the linear regulator with a switching regulator with input from the circuit in a); Draw the schematic diagram and plot the waveforms of current in the inductor and in the diode, for CCM operation; evaluate the duty cycle range required to get Vout = 15 V. The input voltage range is (with some margin): 20 26,5 V. SW L Assuming ideal switch and diode, the required range of duty cycle is from 15/20 to 15/26,5 V I D V L V O 0,75 > D > 0,566 (with ideal SW and diode) I L [for data set B the math result is 0,57 > D > 1,07, but D > 1 is clearly not possible. That means the SW regulator cannot work over the full specified range. It could work properly for an output voltage 12V, as for the linear regulator]. I SW e) Describe the main benefit and the causes of losses in a switching regulator. Provide quantitative evaluation for some of these losses The main benefit of switching regulators is the high efficiency, coming from low power dissipation in the regulation element (ideally 0) Switch: ON state: in a real switch Ron is not 0; losses are related with I^2 Ron OFF state: switch leakage currents not relevant in most cases Transient: at state change, I and V are not 0. Causes power dissipation in the SW, and losses related with speed (fast switches have lower losses). Diode: ON state: a real diode has forward voltage drop (reduced with low-drop diodes) OFF state: diode leakage current Transient: at state change, I and V are not 0. Fast diodes have lower transient losses. Inductor: Series resistance of the coil Ferromagnetic core losses Capacitors: Equivalent series resistance (ESR) DDC -ATLCEscris160718k.doc - 21/07/ :15:00 6

7 Summary of results Quest. Result [A] Result [B] 1a R1 = 150 kω Rc = 10 kω Ic = 0,504 ma Vco = 10,8 V 1b Re1 = 270 Ω (281 Ω).. 1c x = 5,43; II harm: -2,67 dbc; III harm -6,93 dbc 1d II harm level = - 49,7 dbc. 1e 2a Tct = 190 ns, Fsmax = 675 ks/s; Tlat = 350 ns 2b P = 7 poles P = 5 poles 2c Tjmax = 1,23 ns 2d ENOB = 9,65 2e Fckd = 321 MHz 3a Vor = 6 Vpp Vodc = 23,28 V Imax = 6 A 3b R1 = 179 Ω (150 Ω); Vudc = 14,7 V; Vur = 0,643 Vpp 3c Rcamax 4,3 C /W. 3d Dmin = 0,566 Dmax = 0,75. 3e DDC -ATLCEscris160718k.doc - 21/07/ :15:00 7