FET INPUT HIGH SPEED VOLTAGE FOLLOWER/BUFFER AMPLIFIER
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1 MILPRF3853 CERTIFIED FACILITY M.S.KENNEDY CORP. 707 Dey Road Liverpool, N.Y FEATURES: Industry Wide LH0033/EL2005 Replacement Low Input Offset 2mV Low Input Offset Drift 25μV/ C FET Input, Low Input Current 50pA High Slew Rate 500V/μS Wide Bandwidth 0MHz High Output Current ±00mA Available to DLA SMD FET INPUT HIGH SPEED VOLTAGE FOLLOWER/BUFFER AMPLIFIER (35) DESCRIPTION: The MSK 0033(B) is a high speed, wide bandwidth voltage follower/buffer amplifier that is pin compatible with all other 0033 designs. The FET input is cascaded to force the input characteristics to remain constant over the full input voltage range. Significantly improved performance in sample and hold circuits is achieved since the DC bias current remains constant with input voltage. The FET input also makes the MSK 0033 very accurate since it produces extremely low input bias current, input offset voltage and input offset voltage drift specifications. Transistion times in the range of 2.5 ns make the MSK 0033 fast enough for most high speed voltage follower/buffer amplifier applications. EQUIVALENT SCHEMATIC 0033 TYPICAL APPLICATIONS PINOUT INFORMATION Sample And Hold Impedance Buffers For A to D's High Speed Line Drivers CRT Deflection Driver Positive Driver Power Supply Input Offset Preset Offset Adjust Negative Driver Power Supply Negative Power Supply Output Positive Power Supply 8588 Rev. E 2/
2 ABSOLUTE MAXIMUM RATINGS 0 ±VCC IOUT VIN TC Supply Voltage Output Current Differential Input Voltage Case Operating Temperature (MSK 0033B) (MSK 0033) ±20V ±20mA ±20V 55 C to +25 C 0 C to +85 C TST TLD TJ RTH Storage Temperature Range Lead Temperature Range (0 Seconds) Junction Temperature Thermal Resistance Junction to Case Output Devices Only 65 C to +50 C 300 C 75 C 65 C/W ELECTRICAL SPECIFICATIONS Parameter Test Conditions Group A Subgroup MSK 0033B MSK 0033 Min. Typ. Max. Min. Typ. Max. Units STATIC Supply Voltage Range 3 8 ±0 ±5 ±8 ±0 ±5 ±8 V Quiescent Current VIN=0V ±9 ±22 ±9 ±25 ma INPUT Offset Voltage Short Pin 6 to Pin 7 VIN=0V ±2.0 ±0 ±5 ±5 mv Offset Voltage Drift Offset Adjust Short Pin 6 to Pin 7 VIN=0V Pin 6=open RPOT=200Ω From Pin 7 to Pin 9 2,3,2,3 ±25 ±250 Adjust to Zero Adjust to Zero μv/ C mv Input Bias Current 9 VCM=0V ±50 ±00 ±50 ±500 pa Either Input 2,3 ±2 ±0 ±2 na Input Impedance 3 F=DC Ω Power Supply Rejection Ratio 2 ±0V VS ±20V db Input Noise Density 3 F=0Hz to KHz.5.5 μvrms Input Noise Voltage 3 F=KHz 0 0 nv/ Hz OUTPUT Output Voltage Swing VIN=±V RL=KΩ ±2 ±2.5 ±2 ±2.5 V Output Current VIN=±0.5V RL=00Ω ±90 ±0 ±90 ±0 ma Settling Time to % 2 3 2V step ns Bandwidth (3dB) 3 VIN=VRMS RL=KΩ 0 0 MHz TRANSFER CHARACTERISTICS Slew RateRising Edge VOUT=±0V V/μS Slew RateFalling Edge VOUT=±0V V/μS Voltage Gain RS=00Ω VIN=VRMS F=KHz V/V NOTES: Unless otherwise specified ±VCC = ±5 VDC. 2 Measured within a high speed amplifier feedback loop. 3 Devices shall be capable of meeting the parameter, but need not be tested. Typical parameters are for reference only. Industrial grade devices shall be tested to subgroups and unless otherwise specified. 5 Military grade devices ('B' suffix) shall be 00% tested to subgroups,2,3 and. 6 Subgroup 5 and 6 testing available upon request. 7 Subgroup, TA=TC=+25 C Subgroup 2,5 TA=TC=+25 C Subgroup 3,6 TA=TC=55 C 8 Electrical specifications are derated for power supply voltages other than ±5VDC. 9 Measurement made 0.5 seconds after application of power. Actual DC continuous test limit is 2.5 na at 25 C. 0 Continuous operation at or above absolute maximum ratings may adversely effect the device performance and/or life cycle Rev. E 2/
3 APPLICATION NOTES HEAT SINKING To determine if a heat sink is necessary for your application and if so, what type, refer to the thermal model and governing equation below. Thermal Model: RθSA = ((TJ TA)/PD) (RθJC) (RθCS) = ((25 C 80 C) /.6W) 65 C/W.5 C/W = = 5.2 C/W The heat sink in this example must have a thermal resistance of no more than 5.2 C/W to maintain a junction temperature of no more than +25 C. OFFSET VOLTAGE ADJUST See Figure. To externally null the offset voltage, connect a 200Ω potentiometer between Pins 7 and 0 and leave Pin 6 open. If offset null is not necessary, short Pin 6 to Pin 7 and remove the 200Ω potentiometer. Do not connect Pin 7 to Vcc. Governing Equation: TJ=PD x (RθJC + RθCS + RθSA) + TA Where TJ = Junction Temperature PD = Total Power Dissipation RθJC = Junction to Case Thermal Resistance RθCS = Case to Heat Sink Thermal Resistance RθSA = Heat Sink to Ambient Thermal Resistance TC = Case Temperature TA = Ambient Temperature TS = Sink Temperature Example: This example demonstrates a worst case analysis for the buffer output stage. This occurs when the output voltage is /2 the power supply voltage. Under this condition, maximum power transfer occurs and the output is under maximum stress. Conditions: VCC = ±6VDC VO = ±8Vp Sine Wave, Freq. = KHz RL = 00Ω For a worst case analysis we will treat the ±8Vp sine wave as an 8 VDC output voltage..) Find Driver Power Dissipation PD = (VCCVO) (VO/RL) = (6V8V) (8V/00Ω) = 60mW 2.) For conservative design, set TJ=+25 C Max. 3.) For this example, worst case TA=+80 C.) RθJC = 65 C/W from MSK 0033B Data Sheet 5.) RθCS = 0.5 C/W for most thermal greases 6.) Rearrange governing equation to solve for RθSA CURRENT LIMITING See Figure. If no current limit is required, short Pin to Pin 2 and Pin 9 to Pin 0 and delete Q thru Q connections. Q through Q and the Rlim resistors form a current source current limit scheme and current limit resistor values can be calculated as follows: +Rlim Vbe Rlim Vbe Isc Isc Since current limit is directly proportional to the baseemitter voltage drop of the 2N2222's and 2N2907's in the current limit scheme, the current limit value will change slightly with ambient temperature changes. The baseemitter voltage drop will decrease as temperature increases causing the actual current limit point to decrease. POWER SUPPLY BYPASSING Both the negative and the positive power supplies must be effectively decoupled with a high and low frequency bypass circuit to avoid power supply induced oscillation. An effective decoupling scheme consists of a 0. microfarad ceramic capacitor in parallel with a.7 microfarad tantalum capacitor from each power supply pin to ground Rev. E 2/
4 TYPICAL APPLICATIONS 8588 Rev. E 2/
5 TYPICAL PERFORMANCE CURVES Rev. E 2/
6 MECHANICAL SPECIFICATIONS WEIGHT=2.8 GRAMS TYPICAL ALL DIMENSIONS ARE ±0.00 INCHES UNLESS OTHERWISE LABELED ORDERING INFORMATION Part Number MSK0033 Screening Level Industrial MSK0033B 8000ZX MILPRF3853 Class H DLA SMD M.S. Kennedy Corp. 707 Dey Road, Liverpool, New York 3088 Phone (35) FAX (35) The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make changes to its products or specifications without notice, however, and assumes no liability for the use of its products. Please visit our website for the most recent revision of this datasheet Rev. E 2/
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