Page 1. Telecommunication Electronics TLCE - C4 27/10/ DDC 1. Politecnico di Torino ICT School. Lesson C4: signal conditioning

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1 Politecnico di Torino ICT School Telecommunication Electronics C4 Signal conditioning» Protection circuits» Amplifiers» Antialiasing filter» Multiplexer» Sample/Hold Lesson C4: signal conditioning Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) Reference: Signal conditioning sect. 4.6, Sample / Hold sect /10/ TLCE C DDC 27/10/ TLCE C DDC A/D/A system block diagram Complete ADC chain P protezione Protection Conditioning ADC chain Acquisition DAC chain Input protection circuits Block signals which may damage the other circuits Amplifier Make signal level compatible with ADCF input range Optimize SNRq Antialias filter Makes signal bandwidth compatible with sampling rate Multiplexer (for multiple channel systems) Sample/Hold or Track Hold Sampling (discretize in the time axis) A/D Converter Quantization (discretize in the amplitude axis) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Multiple channel system Input protection circuits Signal from the field: Electrostatic charges EMI, noise Direct contacts (unplanned) Need to limit input voltage within safe limits, to avoid damage to the system Input protection circuits Diode clamp Special devices (zener diodes, varistor, ) Control signals 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 1

2 Input operating range Amplitude limiter The safe (no damage) input range Vi MAX Vi MIN depends from the power supply Val. Vi MAX V V AL A unit with nonlinear (clipping) transfer function limits input voltage between Vmax and Vmin Vmax Vmax V i With power off, Val = 0!! Vmin Vmin Vi Vi MIN V AL 27/10/ TLCE C DDC 27/10/ TLCE C DDC Amplitude limiting circuit Test: design of protection circuit Clamp towards power supply V OUT limited between Val and Val V AL V IN V AL V OUT Design R for a Zener protection circuit with the following specs: protection from contacts towards ± 500 V, any duration maximum zener power dissipation 5 W Zener diodes to GND V OUT limited to zener voltage V IN GND V OUT Evaluate value and power of R Specific devices V OUT limited by V(I) of Z In all circuits, the resistance R limits the input current when the protection is active V IN GND Z V OUT V IN GND V OUT 27/10/ TLCE C DDC 27/10/ TLCE C DDC Lesson C4: signal conditioning Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) ADC input dynamic The A/D converter has an input dynamic range unipolar: 0... S, 0 5 V, 0 10 V bipolar: S/2 S/2 5 5 V, V To get maximum SNRq the signal must fill all the usable input dynamic range amplifier (o attenuator) level shifter (bipolar/unipolar) Match signal level to system (ADC) dynamic range 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 2

3 Signal types Voltage amplifier The ADC accepts specific signal types voltage or current (V/I) single ended or differential (S/D) Singleended voltage amplifier Op. Amp. With feedback The unit which matches the dynamic range and the signal type is the conditioning amplifier Many configurations: V V, V I, I I, I V S S, S D, D S, D D 16 choices gain! VU R1 A = = V R V I 2 high Zi» Rs does not affect A V»low Ru» Rc does not affect A V 1 Rs V S V d A d V I V E R 1 R 2 Rc 27/10/ TLCE C DDC 27/10/ TLCE C DDC Transresistance amplifier Differential signals Currenttovoltage converter Differential signals are protected from common mode noise Differential signals do not emit noise V = I R U I M I M I I I R M Some transducers have differential outputs Fast A/D converters operate with differential input signals I I V d A.O. To handle differential signals: Singleended / differential converters Differential amplifiers Instrumentation amplifiers 27/10/ TLCE C DDC 27/10/ TLCE C DDC Singleended and differential signals Common mode rejection singleended signal noise Signal noise A differential amplifier must : Amplify differential signals by a known amount A D Keep common mode signals at a low level: low A C ( 0) Differential signal noise (common mode) Differential signal The key parameter is the A D /A C ratio A D /A C CMRR (Common Mode Rejection Ratio) CMRR 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 3

4 Differential and common mode signals Differential amplifier = A 1 V 1 A 2 V 2 = ADVD ACVC = AD (V 1 V 2 ) AC (V 1 V 2 )/2 VD = V 2 V 1 VC = (V 2 V 1 )/2 V 1 = VC VD/2 V 2 = VC VD/2 = (AD AC/2)V 1 (AD AC/2)V 2 AD = (A 1 A 2 )/2 AC = A 1 A 2 V D /2 Differential amplifier: AC = 0, therefore A 1 = A 2 V C V 1 V D /2 V 2 AD, AC A 1, A 2 R 3 R4 = R1 R2 A C = Vu/V C = 0 Zero common mode gain. A D = Vu/V D = R3/R1 The circuit amplifies only differential signals CMRR V C V D /2 V D /2 R3 V 1 R1 AO V 2 R2 R4 27/10/ TLCE C DDC 27/10/ TLCE C DDC Effects of input impedance Zi Standard differential amplifier Functional specification: Differential amplifier with high CMRR classic differential amplifier Asymmetric Zi causes different partition with Rg A purely common signal (Vs1 = Vs2) generates a differential component, which is amplified.»worse CMRR Need for symmetric Zi Z = R1 I1 R1 V1 = VS1 Rg1 R1 Z = R2 R4 I2 V = V 2 S2 R2 R4 Rg2 R2 R4 V S1 Rg1 Rg2 V S2 Z I1 V 1 R1 V 2 R2 R4 Z I2 R3 AO instrumentation amplifier A common mode signal (Vs1 = Vs2) becomes differential (V1 V2) and is amplified. Low Common Mode Rejection (CMRR) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Voltage followers at the inputs A = 1 high Ri low Ru R3 R4 = = R1 R2 A D V 1 V 2 Symmetric input impedance V 1 R1 V 2 R2 R4 This circuit provides the same high Zi on both inputs R3 AO Instrumentation amplifier Add gain in the first stage (voltage follower) R7 = R5 V 1 R3 V 1 R1 V' 2 V' 1 = R5 R6 R5 (V R7 2 V1 ) 2 1 R6 V R2 AO 2 V 2 R4 R 3 R4 = R1 R2 R5 R3 = (V2 V1 ) 2 1 R6 R1 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 4

5 From singleended to differential Fully differential amplifier Two amplifiers with the same Av inverting»av = R2/R1 noninverting» Av = R3/R4 1» Vu = Vs(R3/R4 1 R2/R1) V S R 1 R 2 R 3 Op. Amp. with differential output Fully differential circuits R 4 High frequency A/D conversion (RF band 120 MHz) From Op Amps for everyone, Texas Instruments, SLOD006B 27/10/ TLCE C DDC 27/10/ TLCE C DDC Lesson C4: signal conditioning Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) Antialias filter Every signal has a nominal bandwidth (where usefuln information is contained), but inludes also outband components (noise, distortion, ) Even sampling within the Nyquist rule (higher than twice the bandwidth), outband signals are folded inside the useful band, and cause Aliasing noise The aliasing noise depends on two parameters: Shape of outband spectrum Sampling rate 27/10/ TLCE C DDC 27/10/ TLCE C DDC Inband folding of signal spectrum Example of aliasing noise Outband signal folded by sampling into the useful band Quantization noise Reconstruction filter mask f B = useful bandwidth (reconstruction filter bandwidth): 12 khz f S = sampling rate: 50 ks/s The signal from f B to f S f B is folded in the useful band from 12 to 38 khz This signal becomes aliasing noise Adds to other noise sources: quantization, 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 5

6 Antialias filter design simplified Signal/(aliasing noise) SNR A Level of outband signal: S Filter: Attenuation SNR A db at f S f B ; no attenuation at f B From f B to f S f B frequency ratio R = (f S f B )/f B Same attenuation R by a single pole RP attenuation if P poles (P x R(dB)) Another approach: A single pole: _ 6 db/octave [20 db/decade] From f B to f S f B attenuation Ap Ap(dB) = 6 * log 2 (f S f B )/f B db [or = 20 * log 10 (f S f B )/f B ] Required number of poles: P = SNR A / Ap Antialias filter design complete Near cutoff, filters can drop faster than 20dB/dec The actual attenuation depends also from filter type Besse, Butterworth, Chebischeff, Elliptic, The required number of poles can be evaluated using proper design tools e.g. FILTERCAD, by Linear Technology, free on website 27/10/ TLCE C DDC 27/10/ TLCE C DDC Reducing aliasing noise Lower outband signal level More steep input filter (more expensive) Increase sampling rate Fs (oversampling) Moves alias spectra away from baseband Brings also higher sample rate (more expensive) Oversampling A/D chain Anti alias input filter (analog, simple) High rate sampling Fast A/D conversion > high bit rate Bit rate reduction with digital filter (decimation) Move complexity analog digital domains Lesson C4: signal conditioning Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Multiple channels system Multiplexer multiplexer Control signals Allows to use the same functional units (S/H and A/D) for several channels Must select one channel among N Must not modify the selected signal Must block other channels Multiplexer parameters Equivalent series resistance Ron Leakage current Ioff Insulation/feedthrough Settling time Input range.. 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 6

7 Multiplexer structure Switches built with MOS (or CMOS) transistors Decoding and command circuits SW Select ON channel Partition from Vi to Vo caused by Ron Multiplexer error sources OFF channels offset caused by leakage currents (open switches) feedthrough from other channels V Ii Dynamic parameters Switching delay bandwidth (RC lowpass cells) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Ron error Ioff error V S R S SW VU Only one switch is closed (ON) to select the input channel V S connected to ouput. V S I OFF VU Only one switch is closed (ON) to select the input channel V S connected to ouput. All other switches are open (OFF). A ON switch has an equivalent resistance R ON. R S R ON Any OFF switch has a leakage current I OFF. R S R ON From V S to the gain is < 1, due to the voltage divider made by the load resistance R L. V S R L The sum of all I OFF cuases an offset voltage OFF at the output. ΣI OFF R L OFF 27/10/ TLCE C DDC 27/10/ TLCE C DDC Frequency limit Where to place the multiplexer V S R S R ON C P The Cgd and Cds paritic capacitances generate respectively pedestal and feedthrough errors (as in S/H circuits). The parasitic capacitance of multiplexer and load limit the transferred signal bandwidth. The signal path includes the lowpass cell R ON / C P. The multiplexing operation changes the signal spectrum Example: two DC signals become squarewave The mux must be placed after the filter S/H and ADC can be used on many channels (each sampling and conversion is independent from previous values) the filter cannot be used on multiple channels (keeps track of previous signal values) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 7

8 Lesson C4: signal conditioning Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) SampleHold unit Function: sample the input analog signal I(t) Sampling at t = ts multiply input signal by δ(ts) Keep the sample value at the output (O) as long as required for A/D conversion: HOLD operation I(t) O(t) t S1 t S2 t 27/10/ TLCE C DDC 27/10/ TLCE C DDC TrackHold operation Actual circuits behavior Before the next sampling operation the circuit must acquire the new value The complete sequence is» Tracking: O(t) = I(t)» Sampling: O = I(ts)»Hold: O(t) = I(ts)» New tracking I(t) O(t) TrackHold operation sequence Track output = input reading the analog signal value Sample transition from Track to Hold constant output, corresponding to sampled value Hold the ADC operatis during this phase Acquisition transition from Hold to Track track hold track t S1 t S2 t sample Acq. sample hold Acq. 27/10/ TLCE C DDC 27/10/ TLCE C DDC Basic Circuit: Track and Hold state The Sample/Hold is an analog memory capacitor switch Track: SW ON Hold: SW OFF During tracking Vu = Vi: the S/H is a unitygain amplifier (or Kgain) Static errors gain, offset, (nonlinearity) Dynamic parameters and errors Settling time» Depends on required precision Bandwidth Tracking phase T H T H T 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 8

9 Tracking: gain error Tracking: step response Step Vi input Output Vo with II order transient Partition of Vi between Rg and R L Gain error Lowpass Rc cell Bandwidth limit Settling time for transient response Offset, nonlinearity, Settling time Steady state error 27/10/ TLCE C DDC 27/10/ TLCE C DDC Time error Delay in SW opening aperture delay Delay changes aperture jitter Amplitude error pedestal Vj Vj = Tj * SR Transient T H settling time Amplitude error S H Aperture time Sampling Settling time The S H transition occurs after an aperture delay T A T A is not constant; is affected by a noise: T J sampling jitter Sampling jitter The sampling jitter causes an amplitude error V = T J * slew rate with sine signal: V = T J ω V With full scale sine signal at ω = 2 п F A : SNRj = Ps/Pj = (S 2 /8)/(T J ω S/2) 2 /12 SNRj = 1.5 (T J п F A ) log 10 (T J п F A ) (db) 27/10/ TLCE C DDC 27/10/ TLCE C DDC Sampling jitter: example Sampling: pedestal error Sampling jitter is caused by switch command noise and clock jitter A critical parameter for digital radio systems To be evaluated independently from sampling rate C C Numeric example: Tj to sample 300 MHz signal with SNRj = 82 db? SNRj = log 10 (T J п F A ) = 82 db 20 log 10 (T J п F A ) 80 db log 10 (T J п F A ) = 4 T J п F A = 10 4 T J = 10 4 / п 300 MHz T J = 10 4 ns = 0.1 ps (100 fs) Partition of the Gate command signal between Cc and Cm Pedestal error 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 9

10 Basic circuit: hold error Hold state: decay error The charge stored on the capacitor changes Decay error Poor isolation of input signal Feedthrough error Dielectric polarization Slow change of stored voltage (long term effect) Decay Ideal Hold Switch OFF: Vo(t) = V i(ts) Output = voltage previously stored on the capacitor Decay and feedthrough The capacitor discharges through R L and I OFF (leakage) Decay error 27/10/ TLCE C DDC 27/10/ TLCE C DDC Basic circuit: feedthrough error Acquisition C P The output reaches the input (within the specified precision) after the acquisition time Tacq Depends on bandwidth slew rate Acquisition time Switch OFF: Vo(t) = V i(ts) Output = voltage previously stored on the capacitor Input signal partitioned between Cp and Cm Feedthrough error S H S H Error band 27/10/ TLCE C DDC 27/10/ TLCE C DDC Decay Increase Cm Isolate load Pedestal Low parasitics Increase Cm Compensate with opposite sign pedestal Feedthrough Low parasitics Increase Cm Gain and offset Use feedback circuits Error handling Pedestal, feedthrough, Hold capacitor Feedthrough: partition of Vi between C DS and Cm Pedestal: partition of Vg between C GD and Cm Decay: discharge of Cm on the load and for switch leakage Z L 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 10

11 Selecting the hold capacitor Cm General rule to reduce decay, pedestal, feedthrough: Reduce parasitic capacitance» selection of MOS switch Increase the hold capacitor Cm Acquisition time depends on the hold capacitor Cm With increase of Cm» Errors are reduced»t ACQ increases Most integrated S/H have basic Cm (low value) inside, with a pin to add external capacitors to increase Cm» Proper selection to limit dielectric polarization errors (long term memory of the dielectric material) Input output isolation Two voltage follower isolate input source and load Floating switch Complex command» Higher feedthrough and pedestal To avoid sum of gain and offset errors Move feedback to get a unique voltage follower 27/10/ TLCE C DDC 27/10/ TLCE C DDC Pedestal compensation Switch built with complementary MOS devices Single feedback loop Reduced gain and offset errors Integrator S/H Compensation of pedestal error a) Complementary transistor b) Dummy device Switch with one side tied to ground simpler command 27/10/ TLCE C DDC 27/10/ TLCE C DDC Lesson C4: signal conditioning Total error Protection circuits Differential and instrumentation amplifiers Antialiasing filters (parameters) Multiplexer Sample/Hold circuits Parameters Basic circuits Total system error (ENOB) Each unit introduces errors and noise Amplifier: Gain, offset, nonlinearity, band limits Filter: Outband signal Sample/Hold: sampling jitter A/D converter: quantization Actual accuracy depends from all these elements not just the bit number N of the A/D 27/10/ TLCE C DDC 27/10/ TLCE C DDC Page DDC 11

12 Key parameter: total Signal/Noise ratio: SNR t SNR t comes from several sources: Quantization, aliasing, sampling jitter Conditioning chain errors Total SNR Independent variables Maximum error/noise voltage add values: Vmax = Σ Vni Total error/noise power add the power: Pnt = Σ Pni Compute SNR t SNR 1 Pnt Pni i 10 log ; SNR t P s P P = = ni = s Ps Effective Number of Bits: ENOB SNR t can be expressed as Equivalent Number Of Bits (for sine signal) Computed from SNR t (measured or evaluated with fullscale input signal) ENOB = (SNR t 1,76)/6 = SNR t /6 0,3 Includes all noise/error sources (quantization, aliasing, sampling jitter, ) Represents the number of actually useful bits of the A/D conversion system 27/10/ TLCE C DDC 27/10/ TLCE C DDC Lesson 7 test questions Draw a circuit suitable as input protection in a A/D system. How can the aliasing noise be reduced? Which are the benefits of differential signals? Which errors can be introduced by a multiplexer? Describe the sequence of states in a Sample/Hold. Which is the relation between sampling jitter error and signal frequency? Which are the benefits and drawback of increasing the memory capacitor in a S/H circuit? Which parameter best describes the actual precision of a A/D conversion system? 27/10/ TLCE C DDC Page DDC 12