Summary of Last Lecture

Transcription

1 EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch bandwidth limitations Switch induced distortion Sampling switch conductance dependence on input voltage Clock voltage boosters Sampling switch charge injection & clock feedthrough EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page Summary of Last Lecture DAC Converters (continued) Segmented current-switched DACs DAC dynamic non-idealities DAC design considerations Self calibration techniques Current copiers EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page

2 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 3 6bit DAC (6+0)- MSB DAC uses calibrated current sources I/ I/ Current Divider I EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 4

3 Current Divider Inaccuracy due to Device Mismatch M & M mismatch results in the two output currents not being exactly equal: Id+ I Id = di I I = I I d d d d d d W di d d L = + dvth W I d V GS V th L I/ I/ M M I Ideal Current Divider I/+dI d / M M I I/-dI d / Real Current Divider M& M mismatched Problem: Device mismatch could severely limit DAC accuracy Use of dynamic element matching (next few pages) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 5 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 6

4 Dynamic Element Matching During Φ During Φ () I = I o +Δ () I = I o Δ ( ) ( ) I () = I o Δ () I = I o +Δ ( ) ( ) I o / I I o / I f clk Average of I : I () () I + I = ( Δ ) + ( +Δ ) Io = / error Δ I o Io EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 7 Note: For optimum current division accuracy clock frequency is divided by two for each finer division Problem: Frequency of operation drastically reduced Note: What if the same clock frequency is used? EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 8

5 Dynamic Element Matching During Φ During Φ I o /4 I o /4 I o / () () I = Io( + Δ) I = Io( Δ) () () I = I ( Δ ) I = I ( + Δ ) o o f clk I 3 I 4 I I () 3 = = I () I 4 o ( + Δ ) ( + Δ )( + Δ ) I () 3 = = I () I 4 o ( Δ ) ( Δ )( Δ ) / error Δ I 3 () I3 + I = Io = 4 Io = 4 () 3 ( + Δ )( + Δ ) + ( Δ )( Δ ) ( + Δ Δ ) f clk I / error Δ E.g. Δ = Δ = % matching error is (%) = 0.0% I o EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 9 Bipolar -bit DAC using dynamic element matching built in 976 Element matching clock frequency 00kHz INL <0.5LSB! EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 0

6 Example: Stateof-the-Art current steering DAC Segmented: 6bit unit-element 8bit binary EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page

7 DAC In the Big Picture Learned to build DACs Convert the incoming digital signal to analog DAC output staircase form Some applications require filtering (smoothing) of DAC output reconstruction filter Analog Input Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 3 DAC Reconstruction Filter Need for and requirements depend on application Tasks: Correct for sinx/x droop Remove aliases (stair-case approximation) DAC Input Sinx/x DAC Output 0.5 B f s / x x Normalized Frequency f/f s EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 4

8 Reconstruction Filter Options Reconstruction Filters Digital Filter DAC SC Filter CT Filter Reconstruction filter options: Continuous-time filter only CT + SC filter Digital and SC filter possible only in combination with oversampling (signal bandwidth B << f s /) Digital filter Band limits the input signal prevent aliasing Could also provide high-frequency pre-emphasis to compensate inband sinx/x amplitude droop associated with the inherent DAC S/H function EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 5 DAC Reconstruction Filter Example: Voice-Band CODEC Receive Path Receive Output f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz GSR Reconstruction Filter & sinx/x Compensator f s = 8kHz Note: f max sig = 3.4kHz f DAC s = 8kHz sin(π f max sig x T s )/(π f max sig xt s ) = -.75 db droop due to DAC sinx/x shape Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, IEEE Journal of Solid-State Circuits, Vol.-SC-7, No. 6, pp.04-03, Dec. 98. EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 6

9 Summary D/A Converter D/A architecture Unit element complexity proportional to B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB(B )+ binary weighted LSB(B ) complexity proportional (( B -) + B ) -DNL compromise between the two Static performance Component matching Dynamic performance Time constants, Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending on the application, reconstruction filter may be needed EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 7 What Next? Analog Input ADC Converters: Need to build circuits that "sample Need to build circuits for amplitude quantization Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization "Bits to Staircase" Reconstruction Filter EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 8

10 Analog-to-Digital Converters Two categories: Nyquist rate ADCs f sig max ~ 0.5xf sampling Maximum achievable signal bandwidth higher compared to oversampled type Resolution limited to max. -4bits Oversampled ADCs f sig max << 0.5xf sampling Maximum possible signal bandwidth lower compared to nyquist Maximum achievable resolution high (8 to 0bits!) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 9 MOS Sampling Circuits EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 0

11 Ideal Sampling In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor C v IN φ S C v OUT Output Dirac-like pulses with amplitude equal to V IN at the time of sampling φ In practice not realizable! T=/f S EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page Ideal Track & Hold Sampling φ v IN S C v OUT φ T=/f S V out tracks input for ½ clock cycle when switch is closed Acquires exact value of V in at the instant the switch opens "Track and Hold" (T/H) (often called Sample & Hold!) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page

12 Ideal T/H Sampling Continuous Time time T/H signal (Sampled-Data Signal) Track Hold Clock Discrete-Time Signal EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 3 Practical Sampling Issues φ v IN M C v OUT Switch induced noise due to M finite channel resistance Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough Clock jitter EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 4

13 kt/c Noise φ 4kTRΔf v IN M C v OUT v IN R S C v OUT Switch resistance & sampling capacitor form a low-pass filter Noise associated with the switch resistance results in Total noise variance= the output (see noise analysis in Lecture ) In high resolution ADCs kt/c noise at times dominates overall minimum signal handling capability (power dissipation considerations). EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 5 Sampling Network kt/c Noise For ADCs sampling capacitor size is usually chosen based on having thermal noise smaller or equal or at times larger compared to quantization noise: Assumption: Nyquist rate ADC Choose C such that thermal noise level kbt Δ C B C kbt V FS B C kbt VFS Δ is less (or equal) than Q noise For a Nyquist rate ADC :Total quantization noise power EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 6

14 Sampling Network kt/c Noise Required C min as a Function of ADC Resolution B B C kbt V FS C min (V FS = V) pf 0.8 pf 3 pf 06 pf 5,800 pf C min (V FS = 0.5V) 0.0 pf.4 pf 5 pf 84 pf,00 pf The large area required for C limit highest achievable resolution for Nyquist rate ADCs Oversampling results in reduction of required value for C (will be covered in oversampled converter lectures) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 7 Sampling Acquisition Bandwidth The resistance R of switch S turns the sampling network into a lowpass filter with finite time constant: τ = RC v IN R φ S C v OUT Assuming V in is constant during the sampling period and C is initially discharged Need to allow enough time for the output to settle to less than ADC LSB determines minimum duration for φ or maximum clock frequency φ v out ( t) = v v invout δv in t /τ ( e ) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 8

15 Sampling: Effect of Switch On-Resistance tx tx t / τ V V <<Δ since V = V ( e ) in out out in Ts T τ s Ve in <<Δ orτ << V ln in Δ Worst Case: V = V in FS v IN φ R S C v OUT Ts 0.7 Ts τ << ln B B ( ) 0.7 R << fcln Bf C s B ( ) s φ t x Example: B = 4, C = 3pF, f s = 00MHz T s /τ >> 9.4, or 0τ <<T s / R << 40 Ω T=/f S EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 9 Switch On-Resistance Switch MOS operating in triode mode: W VDS di IDtriode ( ) = μcox VGS VTH VDS, L R dv Dtriode ( ) ON DS V 0 DS R ON = = W W μc V V C V V V L L ( ) μ ( ) ox GS th ox DD th in Let us call V =0 R then R R ON Ro = Vin V V DD in o o th = W μc V V L ( ) ox DD th VGS = V DD -V in V in φ V DD M C EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 30

16 Sampling Distortion Simulated 0-Bit ADC & T s / = 5τ V DD V th = V V FS = V Sampling Switch modeled: v out v in = e τ T V in VDD V th Results in HD=-4dBFS & HD3=-5.4dBFS EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 3 Doubling sampling time (or ½ time constant) Results in: HD improved from -4dBFS to -70dBFS ~30dB HD3 improved from - 5.4dBFS to -76.3dBFS ~5dB Sampling Distortion Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior to a tolerable level 0bit ADC T s / = 0 τ V DD V th = V V FS = V EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 3

17 Sampling Distortion Effect of Supply Voltage 0bit ADC & T s / = 5τ VDD Vth = V V FS = V Effect of higher supply voltage on sampling distortion HD3 decrease by (V DD /V DD ) HD decrease by (V DD /V DD ) 0bit ADC & T s / = 5τ V DD V th = 4V V FS = V EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 33 Sampling Distortion SFDR sensitive to sampling distortion - improve linearity by: Larger V DD /V FS Higher sampling bandwidth Solutions: Overdesign Larger switches Issue: Increased switch charge injection Increased nonlinear S &D junction cap. Maximize V DD /V FS Decreased dynamic range if V DD const. Complementary switch Constant & max. V GS f(v in ) 0bit ADC T s /τ = 0 V DD V th = V V FS = V EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 34

18 Practical Sampling Summary So Far! kt/c noise C kbt VFS B Finite R sw limited bandwidth 0.7 R << B fc s v IN φ M v OUT C g sw = f (V in ) distortion Vin W g = g for g μc V V VDD V = th L ( ) ON o o ox DD th EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 35 Sampling: Use of Complementary Switches φ g o g n o g o T =g on + g o p φ B g o p φ φ B Complementary n & p switch advantages: Increase in the overall conductance Linearize the switch conductance for the range V thp < Vin < Vdd - V thn EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 36

19 Complementary Switch Issues Supply Voltage Evolution Supply voltage has scaled down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 37 Complementary Switch Effect of Supply Voltage Scaling g effective g o n g o T =go n + g o p φ g o p φ B φ φ B As supply voltage scales down input voltage range for constant g o shrinks Complementary switch not effective when V DD becomes comparable to xv th EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 38

20 Boosted & Constant V GS Sampling V GS =const. OFF ON Gate voltage V GS =low Device off Beware of signal feedthrough due to parasitic capacitors Increase gate overdrive voltage as much as possible + keep V GS constant Switch overdrive voltage independent of signal level Error due to finite R ON linear (to st order) Lower R on lower time constant EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 39 Constant V GS Sampling (= the switch input terminal) EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 40

21 Constant V GS Sampling Circuit VDD=3V P_N M M M3 M8 M6 VP 00ns P C PB C C3 M P M4 M5 M9 VS.5V MHz Va Vg M Vb Chold This Example: All device sizes:0μ/0.35μ All capacitor size: pf (except for Chold) Note: Each critical switch requires a separate clock booster Sampling switch & C EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 4 VDD=0 3V M 0ff C PB 0 3V Clock Voltage Doubler C M Saturation mode 0 3V 0 (3V-V th M ) 0 0 M Triode VDD=3V M off 3V 0 3V (3V-V M th ) (6V-V M th ) Acquire charge C C PB 3V 0 0 3V P P VP =clock 0 3V VP 3V 0 a) Start up b) Next clock phase EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 4

22 Clock Voltage Doubler M 0ff 3V ~6V VDD=3V C PB 0 3V P VP M 0 3V (6V-V M th ) (3V-V M th ) ~ 3V Acquires C charge 3V 0 M Triode Both C & C charged to VDD after one clock cycle Note that bottom plate of C & C is either 0 or VDD while top plates are at VDD or VDD c) Next clock phase EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 43 Clock Voltage Doubler VDD=3V VDD M M P_Boost R C PB C R VDD P 0 VP Clock period: 00ns *R & R=GOhm dummy resistors added for simulation only EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 44

23 Constant V GS Sampler: Φ Low VDD=3V ~ VDD (boosted clock) M3 Triode OFF VDD C3 M4 Sampling switch M is OFF VDD M Triode Input voltage source OFF M OFF VS.5V MHz Chold pf Device OFF C3 charged to ~VDD EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 45 Constant V GS Sampler: Φ High M8 C3 previously charged to VDD VDD C3 pf M9 VS.5V MHz M Chold pf M8 & M9 are on: C3 across G-S of M M on with constant VGS = VDD EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 46

24 Constant V GS Sampling Input Switch V Gate Chold Signal Input Signal EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 47 Clock Multiplier M7 & M3 for reliability Remaining issues: -V GS constant only for V in <V out -Nonlinearity due to Vth dependence of Mon bodysource voltage Boosted Clock Sampling Complete Circuit Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp Switch EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 48

25 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 49 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors Ca & Cb charged to VDD MS off Hold mode EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 50

26 Advanced Clock Boosting Technique clk high Sampling Switch clk high Top plate of Ca & Cb connected to gate of sampling switch Bottom plate of Ca connected to V IN Bottom plate of Cb connected to V OUT VGS & VGD of MS VDD & ac signal on G of MS average of V IN & V OUT EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 5 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect (technology used allows connecting bulk to S) Reported measured SFDR = 76.5dB at f in =00MHz EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 5

27 Constant Conductance Switch Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 53 Constant Conductance Switch OFF Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 54

28 Constant Conductance Switch M Constant current constant g ds ON M replica of M & same VGS as M M also constant g ds Note: Authors report requirement of 80MHz GBW for the opamp for bit 50Ms/s ADC Also, opamp common-mode compliance for full input range required Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp , Dec. 000 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 55 Switch Off-Mode Feedthrough Cancellation Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IF-sampling frontend," ISSCC 00, Dig. Techn. Papers, pp. 34 EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 56

29 Practical Sampling φ V i M C V o R sw = f(v i ) distortion Switch charge injection & clock feedthrough EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 57 Sampling Switch Charge Injection & Clock Feedthrough Switching from Track to Hold V G V H V G V i +V th V i V i M V O V L V O V i ΔV t C s t off t First assume V i is a DC voltage When switch turns off offset voltage induced on C s Why? EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 58

30 Sampling Switch Charge Injection MOS xtor operating in triode region Cross section view L D Distributed channel resistance & gate & junction capacitances G C ov C ov L S C j sb B C j db D C HOLD Channel distributed RC network formed between G,S, and D Channel to substrate junction capacitance distributed & voltage dependant Drain/Source junction capacitors to substrate voltage dependant Over-lap capacitance C ov = L D xwxc ox associated with G-S & G-D overlap EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 59 Switch Charge Injection Slow Clock V H V i V G Device still conducting V i +V th V L t- t off t Slow clock clock fall time >> device speed During the period (t- to t off ) current in channel discharges channel charge into low impedance signal source Only source of error Clock feedthrough from C ov to C s EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 60

31 V G Switch Clock Feedthrough Slow Clock VG C ov D V H V i V i +V th Cov Δ V = ( Vi+ Vth VL) C + C ov s C s V L V O V i ΔV t Cov ( V i+ V th V L) Cs Vo = Vi+ΔV Cov Cov Cov Vo = Vi ( Vi+ Vth VL) = Vi ( Vth VL) C s C s Cs V = V ( + ε ) + V o i os Cov Cov where ε = ; Vos = ( Vth VL) C C s s t- t off t EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 6 Switch Charge Injection & Clock Feedthrough Slow Clock- Example V G 0μ/0.8μ V G V i M VO V H V i +V th C s =pf V i ' ov μ ox μ th L C = 0.fF/ C = 9fF/ V = 0.4V V = 0 V L V O V i ΔV t Cov 0μx0.fF/ μ ε = = =.% Cs pf Allowing ε = /LSB ADC resolution < ~9bit Cov Vos = ( Vth VL) = 0.4mV C s t- t off t EECS 47- Lecture 7 DAC Design (continued)- Nyquist Rate ADCs 007 H.K. Page 6