Lab 8: SWITCHED CAPACITOR CIRCUITS

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1 ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 8 Lab 8: SWITCHED CAPACITOR CIRCUITS Goal The goals of this experiment are: - Verify the operation of basic switched capacitor cells, - Measure the frequency response of SC filters - Compare results with the parameters evaluated from the mathematical model, - Verify the operation of SC acive integrators and amplifiers. Instruments and equipment The switches can use single MOS devices (in the CD4007 MOS array), or complete switches (CD4066 quad switch array). Each solution requires proper supply voltage and switch command voltage levels. The switch command (clock) comes from an additional external signal source, or is locally generated with a CD4093 IC (quad NAND gate with Schmitt trigger input). Input signal is provided by a sine/square signal generator (audio frequency range). Some circuits require input signal with offset. If offset is not provided by the signal source, it can be obtained adding a DC level to the sine/square wave. Other instruments are standard bench equipment: oscilloscope, power supply, breadboard. Design For switches built with the CD4007 use a single supply voltage (Vdd = 14V), and add an offset (about Vdd/2) to the input signal. With the CD4066 switches use dual power supply (+ and 5V), and 0V DC offset input signal. Clock levels must be compatible with the CD4066 switch array. To use only one external signal source, the clock is generated on the breadbord with a squarewave generator, using a Schmitt trigger gate (CD 4093) or an Op Amp with positive feedback. The inverted clock can be obtained from a gate in the same 4093 IC used as inverter. The report must include the schematic diagrams of all the circuits you design, build and test (including the clock generator), with part list and pin numbers of ICs. Topographic diagrams can be useful for measurements and testing, but should not appear in the report. Most common problems and mistakes In CMOS circuits inputs cannot be left floating. Every input pin must receive a voltage corresponding to a correct logic state. This applies to unused inputs in the CD4066 and CD4093) No IC pin can accept a voltage external to the supply range; this rule applies both to clock and analog input signals. Acknowledgement This lab and parts of these instructions come from a lab experiment of the course Elettronica Analogica e di potenza (prof. F. Fiori), May

2 Homework Design Design a squarewave generator using the CD 4093 quad NAND gate with Schmitt trigger input. Power supply: 10 V (+ and 5V) Output frequency: 1 khz 100 khz (tunable with a potentiometer) This circuit can be used as clock source in all the following experiments. The Switched Capacitor circuits require complementary command signal to the switch pair used to build the SPDT (Singe Pole Doble Throw or two-way) switches. The two switches should never be closed at the same time; if the complementary command signals for the switches are obtained with an inverter (as 1a and 1b in fig 1), both switches are closed for a shor time (XX in the timing diagram) due to propagation delay of the inverter. This increases noise at the output. Command signals which drive switches to ON state should never overlap, such as 2a/b. These signals can be obtained with combinatorial networks from 1a/b. 1a / \ / \ / \ 1b \ / \ / \ / Overlap XXX XXX XXX 2a \ / \ / \ / 2b / \ / \ / \ Fig 1 Not-overlapped clocks (2a/b) 2a/b can can be obtained from 1a/b with delays and a simple combinatorial network. Before building and measuring the switched capacitor circuits, build and verify the clock source. The signal source on the bench must be used for input signal (sinewave). Analysis Evaluate the Vout/Vin transfer function and the step response (from SC circuit theory) for all circuits proposed in the following sections. Device selection All circuits can use for the switches the CD 4007 MOS array, or the CD4066 (quad CMOS switch array). The two ICs have different requirements for power supply, control voltage and signal handling. Verify the instructions, the data sheets, and use your circuit and device knowledge!. s based on CD4066 have slightly better performance, due to better switch parameters. 2

3 Order 1 low-pass SC cell The circuit is a basic lowpass SC cell. The switches can be built using single n-mos transistors (CD4007) or integrated switches (CD4066/4016). Cf is the Switched capacitor. Evaluate the Vout/Vin transfer function from SC circuit theory. For both circuits: Cf = 22 nf; Ct = 270 nf Before starting circuit wiring, draw the complete schematic diagrams of the circuit with pin numbers of ICs. with CD4007 (single MOS devices) used as switches (Fig 1a). Use the n-mos devices for the switches, and a p-n MOS pair to build the inverter. For correct biasing of each device, build the inverter using the p and n MOS with Drains connected respectively to Vdd and Vss. Power supply: +12V Use an external clock source CLK at 20 KHz, duty cycle DC = 0,5, Vh = 10V, and VL = 0V Input: sinewave with: Vpeak = 1,5 V, Vdc = 2 V (use the offset command) Figure 1a SC lowpass cell single MOS devices with the CD40066 quad switch (fig 1b). This circuit operatis with bipolar sinewave (DC = 0). Power supply: + and - 5 V. Use the CD4093 for the clock source and the inverter. Input: sinewave with: Vpeak = 1 V, Vdc = 0 V Vin M1 Cf M2 C T Vout Figure 1b SC lowpass cell with CD 4066 Use the oscilloscope to verify operation and measure the input and output voltages. - Measure the transfer function (Bode diagram), and find the -3 db bandwidth. - Replace the M1-Cf-M2 group with the equivalent resistor. Verify circuit operation and discuss changes in Vout (rebuild the SC cell after this experiment). - Describe the change in the output signal whith clock rate from 100kHz to 1 khz. - Apply at the input a squarewave with same level and DC as sinewave, Fi = 100 Hz. Verify and explain the output waveform. - With squarewave input, set the clock rate Fs at 100 khz, 20 khz, 5 khz, 1 khz; describe and explain the changes in the output waveform. - Measure the time constant for one of the previous clock rate, and compare with expected value. Simulate parasitic capacitances with external capacitor from both ends of M1 and M2 to ground (apply one external capacitor at a time). Verify and explain the effects on the transfer function. 3

4 SC active integrator The circuit in figure 2 is an active integrator which uses a SC cell as input resistance. The switches can be built using single n-mos transistors (CD4007) or integrated switches (CD4066 see fig 1b). Cf is the Switched Capacitor. Evaluate the Vout/Vin transfer function from SC circuit theory. Before starting circuit wiring, draw Figure 2 SC active integrator the complete schematic diagrams of the circuit with pin numbers of ICs (this is actually a general rule, to be followed for any experiment). with CD4007 MOS used as switches Use the n-mos devices for the switches, and a p-n MOS pair to build the inverter. For correct biasing of each device, build the inverter using the p and n MOS with Drains connected respectively to Vdd and Vss. Power supply: +12V Use an external clock source CLK at 20 KHz, duty cycle DC = 0,5, Vh = 10V, and VL = 0V Input: sinewave with: Vpeak = 2 V, Vdc = 2 V (use the offset command) with the CD40066 quad switch Power supply: +- 5 V. Use the CD4093 for the clock source and the inverter. Input: sinewave with: Vpeak = 1 V, Vdc = 0 V Capacitors: Cf = 22 nf; Ct = 270 nf Use the oscilloscope to verify operation and measure the input and output voltages. Apply at the IN input a squarewave with: Frequency 100 Hz, Peak value Vp = 250 mv, Vdc = 0 V (use the offset command) - Verify circuit operation. Explain why the output saturates. - Replace the M1-Cf-M2 group with the equivalent resistor. Verify circuit operation and discuss changes in Vout (rebuild the SC cell after this experiment). - Add a 1 Mohm R in parallel to CT; verify and explain changes in Vout. - Measure the integrator constant, and compare with the value computed from Fck, Cf, CT. - Set the clock rate Fs at 100 khz, 20 khz, 5 khz, 1 khz; describe and explain the changes in the output waveform. - Change the offset of the IN signal; describe and motivate the effects on Vout. Simulate parasitic capacitances with external capacitor from both ends of M1 and M2 to ground (apply one external capacitor at a time). Verify and explain the effects on the transfer function. This circuit and the following ones can be built using the CD 4093 as clock generator and the CD 4066 quad switch. In this case use +-7V supply and do not apply offset to input signal.. 4

5 Parasitic insensitive SC active integrator Rebuild the active SC integrator using the 4-switch cell (circuit in figure 3). (an inverter not shown in the diagram - is required to get the Φ1 and Φ 2 commands). Switches can use the single MOS of CD 4007, or the CNOS switches in the CD4066 IC (see fig 1b). Verify the circuit operation, with the same procedure as for the previous active integrator. Simulate parasitic capacitances with external capacitor from both ends of C1 and C2 to ground. Verify and explain the effects on the transfer function. Modify the switch commands to get a noninverting integrator, and verify the new circuit operation. Φ1 Φ2 Φ1 Φ2 Figure 3 SC active integrator with 4-SW cell SC Amplifier This is the last experiment, to be done only after completition of the previous ones. Use the same MOS, Op Amp, and power supply as in previous circuits (with an additional CD4007, to use nmos for all switches). Cf = 22 nf; Ct = 270 nf Evaluate the Vout/Vin transef function from SC circuit theory. Figure 4 SC amplifier Clock CLK at Fck = 20 KHz, DC = 0,5, Vh = 10V, VL = 0V Apply at the IN input a squarewave with: Frequency 100 Hz Peak value Vp = 250 mv DC component Vdc = 250 mv (use the offset command) - Verify circuit operation. - Measure the gain of the amplifier - Verify amplifier bandwidth with M3 off. This circuit can be built using the CD 4093 as clock generator and the CD 4066 quad switch. In this case use +-5V supply and do not apply offset to input signal. 5

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