High-speed Serial Interface

Transcription

1 High-speed Serial Interface Lect. 9 PLL (Introduction) 1

2 Block diagram Where are we today? Serializer Tx Driver Channel Rx Equalizer Sampler Deserializer PLL Clock Recovery Tx Rx 2

3 Clock Clock: Timing reference signal Usually modeled as sinusoidal = cos + But in digital systems, Sinusoidal Clock in HSI Only transition (rising or falling) edges are of interest for sampling (0 and phases) Different requirements on PLL 3

4 Phase Absolute phase = cos + : Increases with time but within (-π, π) Relative phase Often relative phase relative to reference is more important Ref = + 1 x = + 2 4

5 What is phase Absolute phase Relative phase Phase Phase time time 5

6 PLL Phase locking loop Aphase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. wikipedia PLL-based refers to any kinds of phase-tracking circuits Ex) CDR, costas-loop Applications Clock generation System clocks for any digital systems LO in RF systems Tx clock in HSI Filtering out noisy input Clock and data recovery 6

7 Phase-tracking by PLL Distance time Cameraman can only control the accelerator (velocity) Distance: Integral of velocity Control of velocity in order to lock the distance After locking, distance and velocity should be the same 7

8 Phase-tracking by PLL Absolute phase time Phase: Integral of frequency PLL: Control of frequency in order to lock the phase After locking, phase and frequency should be the same 8

9 Phase-tracking by PLL Phase-tracking analysis with relative phase Similar to step response in control engineering Relative phase phase=ϕ ref slope=0 slope=ω PLL5 - ω ref time 9

10 Phase-tracking by PLL 10

11 Block Diagram 4 main components Phase detector Loop filter Voltage-controlled oscillator s Output signal is phase-locked to input signal Should have the same frequency (without dividers) and phase Input Pre Phase Detector Loop Filter Voltage Controlled Oscillator Post Output Main 11

12 Block Diagram Phase detector (PD) PD detects phase difference between two inputs Various types of PD Mixer (XOR): classic type of PD Phase frequency detector: most popular PD Tri-state PD: PD used for data pattern Input Pre Input: θ in -θ div [rad] Phase Detector Output: Voltage or current Loop Filter Voltage Controlled Oscillator Post Output Main 12

13 Block Diagram Loop filter Loop filter controls characteristic of phase response Stability Loop bandwidth: how fast the loop tracks input phase change. Input Pre Phase Detector Loop Filter input: Voltage or current output: Voltage Voltage Controlled Oscillator Post Output Main 13

14 Block Diagram Voltage-controlled oscillator Oscillator whose frequency is controlled by input voltage. VCO can also be implemented in the form of CCO or DCO. Output phase is integral of VCO frequency. Input Pre Phase Detector Loop Filter input: Voltage Voltage Controlled Oscillator Output: Phase [rad] Post Output Main 14

15 Block Diagram s are employed to produce desired output frequency different from input frequency External reference clock is usually generated from a crystal oscillator, which has very stable signal but very limited frequency ranges less than about 100MHz = Input Pre Phase Detector Loop Filter Voltage Controlled Oscillator Post Output Main 15

16 Time-Domain Analysis Phase tracking of PLL with multiplier type PD: ω in =ω out 16

17 Time-Domain Analysis Frequency tracking of PLL with multiplier type PD: ω in ω out 17

18 Time-Domain Analysis For digital (1 or 0) signals, XOR gate PD 18

19 Time-Domain Analysis Phase tracking of PLL with XOR PD: ω in =ω out 19

20 Time-Domain Analysis Frequency tracking of PLL with XOR PD: ω in ω out 20

21 S-domain analysis Useful for stability analysis Pre- and post- dividers are not included VCO is modeled as 1/s representing integrator Units are different at each node = () 1+() = () 1+ () 1 ϕ ref [rad] [rad] Phase Detector Voltage [V] Loop [V] [rad] Controlled Filter Oscillator ϕ vco K PD H LF (s) K VCO s Main 21 1 M

22 S-domain analysis Assuming a loop filter with 1-pole and 1-zero Transfer function of the filter is; () = ( + ) + Then we can derive closed-loop transfer function as; = () = ( + ) + 1+ ( + ) + 1 = ( + ) ++ ( + ) 1 = ( + ) +(+ ) + 22 = Stability? Final value of the step response? Second-order system

23 PLL Step Response PLL PLL DLL 23

24 What is DLL?? In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line. wikipedia DLL is also a kind of phase-locked loop since DLL output clock tracks the phase of input reference clock. In general, it is called DLL if phase-locked loop is capable of controlling only its output phase and has no internal oscillator. 24

25 DLL block diagram DLL has no voltage-controlled oscillator Instead, voltage-controlled delay-line is employed. DLL doesn t include divider in the feedback loop. The transfer function is; = () 1+() = () 1+ () External Clock source ϕ ref [rad] [rad] Phase Detector Voltage [V] Loop [V] [rad] Controlled Filter Delay-line ϕ vco K PD H LF (s) K VCDL No divider 25

26 DLL transfer function Assuming a loop filter with 1-pole and 1-zero Loop filter transfer function; DLL closed-loop transfer function; = () 1 + () = ( + ) + = ( + ) + 1+ ( + ) + = ( + ) ++ ( + ) = ( + ) = DLL is always stable No overshoot for step response 1st-order system

27 PLL vs. DLL Steady-state error in step response PLL: = lim{1 }=lim =0 DLL: = lim{1 }=lim = + 0 if K>>0, 0 27