Project #2 for Electronic Circuit II

Transcription

1 Project #2 for Electronic Circuit II Prof. Woo-Young Choi TA: Hyunkyu Kim, Minkyu Kim June 7, Deadline : 6:00 pm on June 23, Penalties for late hand-in. - Team Students are expected to form a team of two members to do the project and hand in one project report. Equal grades will be given to the members of the same team. Each team must do its own simulation and analysis. - MOS PSpice parameters Use Level 7 PSpice parameters for 0.25 μm CMOS process. The course homepage has PSpice 17.2 student version, level 7 PSpice parameters as well as PSpice basic manual. - Design rules 1. VDD = 2.5V μm length of gate 2μm μm width of gate 200μm 6. Body of pmos must connect to VDD 7. Body of nmos must connect to GND - Goal You are expected to design a FM demodulator based on PLL. Your design will be evaluated based on following criteria: 1. How well you satisfy the specifications. 2. How well your circuit demodulates the input FM signal. 3. How good your design report is.

2 I. Ring-type Voltage Controlled Oscillator Design [20] Design a ring-type VCO that satisfies the given design goals. The circuit configuration is given below. (The circuit configuration is not ideal due to the limitation on the number of transistors you can use in PSPICE). M1 M1 M1 Vout M2 M2 M2 0.5 pf 0.5 pf 0.5 pf Vcont M3 Vcont M3 <Fig. 1> Ring-type voltage controlled oscillator schematic Design Goals Parameter Value 680 MHz to 720 MHz Target oscillation V cont = 1.25 V VCO gain (KVCO) 150MHz/V ~ 300MHz/V You should include the following in the report. (1) Simulation results - Plot V out in time domain at the target frequency. - Plot V out in frequency domain at the target frequency. And show the control voltage. - Plot oscillation frequency vs. V cont. Control voltage range is 0.8 V to 2.25 V. And find out the maximum & minimum frequency of your VCO. (2) Average VCO gain (K vco ) - (Maximum frequency Minimum frequency)/1.45

3 II. FM Demodulator Design [30] Design a FM demodulator using PLL structure. Input FM signal is provided by VSFFM source in PSpice (VOFF = 1.25, VAMPL = 1.25, FC = 700 meg, MOD = 1, FM = 50 meg). FM Modulator Phase Detector R Demodulated Signal Voltage Controlled Oscillator C <Fig. 2> FM demodulator block diagram For Phase Detector, use CMOS 2-input XOR along with an CMOS invertor shown in Fig. 3 and 4. Use following transistor sizes for XOR and Inverter. A B X X <Fig. 3> CMOS XOR gate schematic <Fig. 4> CMOS inverter schematic

4 Transistor sizes for Phase Detector block Transistor type XOR gate Inverter PMOS W = 12.5 um / L = 0.25 um W = 25 um / L = 0.25 um NMOS W = 5 um / L = 0.25 um W = 10 um / L = 0.25 um Determine the values for R and C in FM demodulator s loop filter. C must be lower than 500 pf and R should be lower than 5 kω. You need to optimize this loop filter to satisfy our given limitation of settling time & demodulated signal quality. Overall system must satisfies the butterworth condition (Q = 1/ 2). The meaning of settling time is time required for the demodulation signal to be stably comes out. (Voltage peak to peak variation of each period < 0.05 V) Design Goal Parameter Settling time (Locking time) Demodulated frequency Quality Factor Value Lower than 300ns 650MHz, 700MHz, 750 MHz Q = 1/ 2 (Butterworth Condition) You should include the following items in the report. (1) Simulation results - Plot output signal from VCO & input FM signal in time domain. - Plot the output signal from VCO & input FM signal in frequency domain. There must be 3 high points at 650 MHz, 700 MHz, 750 MHz when output signal is plotted in frequency domain. - Plot Demodulated signal(v cont ) in time domain and find out settling time. - Prove the demodulated signal(v cont ) is matched to given FM signal. (2) System Analysis - Derive the gain of phase detector (K PD ) using two rectangular signals which phase difference is 0 to π (Use VPULSE source to generate rectangular signals) - Derive close loop transfer function of your FM demodulator using transfer functions of phase detector, VCO, and loop filter. Use the values from the simulation for all parameters. You must clearly prove that your system is butterworth condition.

5 IV. Design Report [50] You should write a design report in which you clearly explain how you come up with your transistor W/L values and what values you have achieved for design specifications. All your design results should be summarized in Design Summary Sheet. Place the Design Summary Sheet right after the cover page of your report. Three extra points will be given if your report is written in English. You have to think about the contents below to get points in the design report. Even if the reasoning is not exactly correct, I will give score if it is based on the results of the simulation or the background knowledge from the lecture. Part I. - Specify how do you set up W or L values of each NMOS & PMOS. - Discuss about how target oscillation frequency can be achieved. - Discuss about how oscillation can be started in ring oscillator. - Discuss about how V cont and M3 can control oscillation frequency. Part II. - Describe how do you optimized the loop filter of FM demodulator and discuss about the relationship between the loop filter s pole and settling time. - Discuss about the problems of FM demodulator when gain of phase detector(k PD ) is not linear. - Discuss about the problems of FM demodulator when gain of VCO (K VCO ) is high or low - Discuss about why demodulated signal is not ideal sine wave.

6 Design Summary Sheet Name 1: Name 2: Student ID No.: Student ID No.: < Ring-type VCO Design > (W/L) 1 (W/L) 2 (W/L) 3 Vcont = 1.25V Min. frequency Max. frequency Average VCO gain < FM Demodulator Design > R C Settling(Locking) time Demodulated Frequency Quality Factor K PD K VCO Transfer Function of FM demodulator