Concepts of Oscillators
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1 Phase-Locked Loops Concepts of Oscillators Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering
2 Overview Readings B. Razavi, Design of Integrated Circuits for Optical Communications, Chap. 6, 2003, McGraw-Hill. Outline General considerations Ring oscillators Voltage-controlled oscillators 4-1
3 Feedback System Vout H(s) (s) Vin 1 H(s) If for s = j 0, H( j 0) = 1, then the closed-loop gain approaches infinity at 0. Under this condition, the circuit amplifies its own noise components at 0 indefinitely. 4-2
4 Feedback System Evolution of oscillatory system with time A noise component at 0 experiences a total gain of unity and a phase shift of 180o,returning to the subtractor as a negative replica of the input. Upon subtraction, the input and the feedback signals give a larger difference. Thus, the circuit continues to regenerate, allowing the component at 0 to grow. 4-3
5 Barkhausen Criteria If H( j 0) = 180o, then VX = V0 + H( j 0) V0 + H( j 0) 2V0 + H( j 0) 3V0 +. If H( j 0) > 1, then VX (divergent). If H( j 0) < 1, then V X V0. 1 H ( j 0 ) Barkhausen criteria If a negative-feedback circuit has a loop gain that satisfies two conditions: H( j 0) 1 and H( j 0) = 180o, then the circuit may oscillate at 0. In order to ensure oscillation in the presence of temperature and process variations, we typically choose the loop gain to be at least twice or three times the required value. 4-4
6 Barkhausen Criteria Various views of oscillatory feedback system The second Barkhausen criterion as H( j ) = 180o denotes an additional frequency-dependent phase shift that ensures the feedback signal enhances the original signal. 4-5
7 Ring Oscillators 4-6
8 One-Pole Feedback System The open-loop circuit contains only one pole, thereby providing a maximum frequency-dependent phase shift of 90o. Since the common-source stage exhibits a dc phase shift of 180o due to the signal inversion from the gate to the drain, the maximum total phase shift is 270o. The loop therefore fails to sustain oscillation growth. 4-7
9 Two-Pole Feedback System Two significant poles appear in the signal path, allowing the frequencydependent phase shift to approach 180o. Unfortunately, this circuit exhibits positive feedback near zero frequency due to the signal inversion through each common-source stage. As a result, it simply latches up rather than oscillates. 4-8
10 Two-Pole Feedback System with Additional Signal Inversion The loop contains only two poles: one at E and another at F. The frequencydependent phase shift can therefore reach 180o, but at a frequency of infinity. Since the loop gain vanishes at very high frequencies, the circuit does not satisfy both of Barkhausen s criteria at the same frequency, failing to oscillate. 4-9
11 Three-Stage Ring Oscillator If the three stages are identical, the total phase shift around the loop,, reaches 135o at = P,E ( P,F = P,G) and 270o at =. Consequently, equals 180o at <, where the loop gain can be still greater than or equal to unity. Neglecting the effect of gate-drain overlap capacitance and denoting the transfer function of each stage by A0/(1 + s/ 0), we have for the loop gain: A03 H (s ) 3 s 1 0 The circuit oscillates only if the frequency-dependent phase shift equals 180o, i.e., if each stage contributes 60o. tan 1 osc 60o 0 osc
12 Three-Stage Ring Oscillator Find the minimum voltage gain per stage: the loop gain at osc is equal to unity. A3 0 1 osc A0 = 2. a three-stage ring oscillator requires a low-frequency gain of 2 per stage, and it oscillates at a frequency of 3 0, where 0 is the 3-dB bandwidth of each stage. Waveforms of a three-stage ring oscillator: Since each stage contributes a frequencydependent phase shift of 60o as well as a low-frequency signal inversion, the waveform at each node is 240o (or 120o) out of phase with respect to it neighboring nodes. 4-11
13 Linear Model of Three-Stage Ring Oscillators The closed-loop transfer function is A03 3 Vout (s ) A03 1 s / 0 3 Vin (s ) A03 1 s / 0 A s / 0 3 The close-loop system exhibits three poles: 3 s 1 A A 1 j s1 = ( A0 1) 0, s2,3 0 2 Since A0 is positive, the pole s1 leads to a decaying exponential term: exp[( A0 1) 0t ], which can be neglected in the steady state. 4-12
14 Poles of three-stage ring oscillator for various values of gain Neglecting the effect of s1, the output waveform is A 3 A 2 V out (t ) a exp 0 0t cos 0 0t 2 2 If A0 > 2, the exponential envelope grows to infinity. In practice, as the oscillation amplitude increases, the stages in the signal path experience nonlinearity and eventually saturation, limiting the maximum amplitude. If the small-signal loop gain is greater than unity, the circuit must spend enough time in saturation so that the average loop gain is still equal to unity. 4-13
15 Differential Implementation of Three-Stage Ring Oscillators The number of stages in a ring oscillator is determined by various requirements, including speed, power dissipation, noise immunity, etc. In most application three to five stages provide optimum performance (for differential implementation). 4-14
16 Ring Oscillator Using CMOS Inverters Linear Nonlinear When the circuit is released with all inverters at their trip point, the oscillation begins with a frequency of A / 2 but, as the amplitude grows and the circuit becomes nonlinear the frequency shifts to 1/(6TD) which is a lower value. 4-15
17 Multi-Stage Ring Oscillators Five-stage single-ended ring oscillator fosc = 1/(10TD) Four-stage differential ring oscillator Loop gain function A04 H (s ) 4 s 1 0 Oscillation freq.: tan osc o 45 o 4 osc = 0 Minimum voltage gain: A0 1 2 A0 2 osc 1 0 VX1 VY1 VY2 VX2 VX3 VY3 VX4 VY4 t TD 4-16
18 Ring Oscillator Design Stages in a ring oscillator Determine the maximum voltage swings When M1 is fully on, its gate and drain voltages are equal to VDD and VDD ISS RP, respectively. For M1 to remain in saturation, we have ISS RP VTH, i.e., the peak-to-peak swing at each drain must not exceed VTH. 4-17
19 Determine the minimum supply voltage Assuming the inputs vary between VDD and VDD ISSRP, As VY = VDD, M1 carries all of ISS and 2I SS VP VDD VTH ncox (W / L )1,2 As V1 falls and V2 rises, ID1 + ID2 = ISS, VGS1 = V1 VP and VGS2 = V2 VP, 1 1 ncox W / L 1,2 V1 VP VTH 2 ncox W / L 1,2 V2 VP VTH 2 I SS I SS VP V1 V2 2VTH V1 V2 2 2 ncox (W / L )1,2 4-18
20 If V1 and V2 vary differentially, then V1 = VCM + V and V2 = VCM V, where VCM = VDD ISSRP/2, yielding 1 4 I SS V P V CM V TH (2 V )2 2 n C ox (W / L )1,2 V P,min VCM VTH I SS nc ox (W / L )1,2 for V = 0. (ID1 = ID2 = ISS /2). Waveform Vp varies at twice the oscillation frequency. (frequency doublers) Minimum supply voltage: suppose Vp,min VISS, VISS denotes minimum required voltage across ISS. VDD RP I SS I SS VTH VISS 2 ncox (W /L )1,2 V DD V ISS V TH I SS R I P SS n C ox (W / L )1,
21 Voltage-Controlled Oscillators 4-20
22 Voltage-Controlled Oscillators (VCOs) An ideal VCO is a circuit whose output frequency is a linear function of its control voltage: out = 0 + KVCO Vcont 0 represents the intercept corresponding to Vcont = 0. KVCO denotes the gain or sensitivity of the circuit (expressed in rad/s/v). The achievable range, 2 1, is called the tuning range. 4-21
23 Performance Parameters of VCOs Center frequency The center frequency is determined by the environment in which the VCO is used. For example, in the clock generation network of a microprocessor, the VCO may be required to run at the clock rate or even twice that. Tuning range The required tuning range is dictated by two parameters: the variation of the VCO center frequency with process and temperature the frequency range necessary for the application. To minimize the effect of noise in Vcont, the VCO gain must be minimized, a constraint in direct conflict with the required tuning range. The allowable range of Vcont is from V1 to V2 and the tuning range must span at least 1 to 2, then KVCO must satisfy the following requirement: K VCO 2 1 V 2 V1 4-22
24 Performance Parameters of VCOs (cont d) Tuning linearity The tuning characteristics of VCOs exhibit nonlinearity, i.e., their gain, KVCO, is not constant. Such nonlinearity degrades the settling behavior of phaselocked loops. For this reason, it is desirable to minimize the variation of KVCO across the tuning range. For a given tuning range, nonlinearity inevitably leads to higher sensitivity for some region of the characteristic. Output amplitude It is desirable to achieve a large output oscillation amplitude, thus making the waveforms less sensitive to noise. The amplitude trades with power dissipation, supply voltage, and even tuning range. 4-23
25 Performance Parameters of VCOs (cont d) Power dissipation As with other analog circuits, oscillators suffer from trade-offs between speed, power dissipation, and noise. Supply and common-mode rejection Oscillators are quite sensitive to noise, especially if they are realized in single-ended form. Noise may be coupled to the control line of a VCO as well. For these reasons, it is preferable (but not always possible) to employ differential paths for both the oscillation signal and the control line. Output signal purity The electronic noise of the devices in the oscillator and supply noise lead to noise in the output phase and frequency. These effects are quantified by jitter and phase noise and determined by the requirements of each application. 4-24
26 VCO circuit design Conventional delay elements Current-starved inverter Variable Cload Vcont IN IN OUT Vcont OUT Vcont Be sensitive to power supply noise. Use an on-chip voltage regulator to reduce the effect of power supply noise. But it is not effective for operation at high frequency since a voltage regulator inherently has poor ac rejection. it reduce the useful power supply range, making it undesirable for low-supply applications. 4-25
27 Current-starved n-stage VCO MBp Vcont M4 ID4 M3 Vosc M2 ID1 Vcont MBn Biasing M1 n-stage Ring Osc. 4-26
28 Current-starved n-stage VCO Determine the oscillation frequency Output capacitance: 3 Ctot Cout Cin Cox' (W p L p Wn Ln ) Cox' (W p L p Wn Ln ) 2 o/p cap. of the delay stage i/p cap. of the next stage 5 Cox' (W p L p Wn Ln ) 2 ID4 M3 Total delay time: Vm M2 0 Vm charged time: t1 Ctot Vm I D4 ID1 VDD Vm I D1 C V Unity stage delay time td t1 t2 tot DD ID Ctot VDD Vm discharged time: t2 Ctot (We set ID1 = ID4 = ID, Vm = VDD /2). Oscillation frequency f osc Average current drawn by VCO: I avg n VDD Ctot n VDD Ctot f osc T ID 1 ID n td n C tot V DD 4-27 Average power dissipation of VCO: Pavg VDD I avg VDD I D
29 CSA ring oscillator Current steering amplifier (CSA) cell (or current steering logic, CSL) Ib Vin M1 M2 Vout M1: input device, M2: load When Vin is high, M1 turns on, sinking the bias current Ib, while M2 shuts off. The on resistor of M1 defines the output low voltage, VOL. When Vin is low, M1 turns off and Ib is steered to M2. The resistor of the diode-connected M2 defines the output high voltage, VOH. Output voltage swing: (W / L)1 (W / L) 2 2 I b V VOH VOL Vth Ib fosc, V (W / L)1 (W / L) 2 K ' Since the current source always operates in saturation, very small switching noise is generated. 4-28
30 CSA ring oscillator Three-stage CSA ring oscillator Vout Vcont Yang, JSSC, Apr The frequency of the CSA ring oscillator is practically independent of power supply. The maximum useful frequency of the VCO is limited by the saturation voltage of the cascoded PMOS current source in the charge-pump circuit. 4-29
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